Changeset 8f035cb in rtems


Ignore:
Timestamp:
Jun 27, 2018, 6:57:08 AM (11 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
71af1a4
Parents:
b706b4a
git-author:
Sebastian Huber <sebastian.huber@…> (06/27/18 06:57:08)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/29/18 08:04:37)
Message:

riscv: Implement _CPU_Context_volatile_clobber()

Update #3433.

Location:
cpukit/score/cpu/riscv
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/riscv/include/rtems/score/cpu.h

    rb706b4a r8f035cb  
    416416  (((value&0xff) << 8) | ((value >> 8)&0xff))
    417417
    418 static inline void _CPU_Context_volatile_clobber( uintptr_t pattern )
    419 {
    420   /* TODO */
    421 }
     418void _CPU_Context_volatile_clobber( uintptr_t pattern );
    422419
    423420static inline void _CPU_Context_validate( uintptr_t pattern )
  • cpukit/score/cpu/riscv/riscv-context-volatile-clobber.S

    rb706b4a r8f035cb  
    11/*
     2 * Copyright (c) 2018 embedded brains GmbH
    23 * Copyright (c) 2015 Hesham Almatary <hesham@alumni.york.ac.uk>
    34 *
     
    3637SYM(_CPU_Context_volatile_clobber):
    3738
    38         .macro  clobber_register reg
    39         addi    t0, t0, -1
    40         mv      \reg, t0
    41         .endm
    42 
    43         clobber_register        a0
    44         clobber_register        a1
    45         clobber_register        a2
    46         clobber_register        a3
    47         clobber_register        a4
    48         clobber_register        a5
    49         clobber_register        a6
     39        addi    a1, a0, 1
     40        addi    a2, a0, 2
     41        addi    a3, a0, 3
     42        addi    a4, a0, 4
     43        addi    a5, a0, 5
     44        addi    a6, a0, 6
     45        addi    a7, a0, 7
     46        addi    t0, a0, 8
     47        addi    t1, a0, 9
     48        addi    t2, a0, 10
     49        addi    t3, a0, 11
     50        addi    t4, a0, 12
     51        addi    t5, a0, 13
     52        addi    t6, a0, 14
    5053
    5154        ret
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