Index: c/src/lib/libcpu/powerpc/mpc8xx/Makefile.am
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/Makefile.am	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
+++ c/src/lib/libcpu/powerpc/mpc8xx/Makefile.am	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
@@ -0,0 +1,10 @@
+## 
+## $Id$
+## 
+
+AUTOMAKE_OPTIONS = foreign 1.4
+
+SUBDIRS = include console-generic clock timer vectors cpm mmu
+
+include $(top_srcdir)/../../../../../automake/subdirs.am
+include $(top_srcdir)/../../../../../automake/local.am
Index: c/src/lib/libcpu/powerpc/mpc8xx/README
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/README	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
+++ c/src/lib/libcpu/powerpc/mpc8xx/README	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
@@ -0,0 +1,19 @@
+#
+#  $Id$
+#
+
+Various non BSP dependant support routines.
+
+clock - Uses the MPC860/MPC821 PIT (Programmable interval timer) to
+	generate RTEMS clock ticks.
+
+console_generic - Uses the MPC860/MPC821 SCCs and SMCs to to serial I/O.
+
+include - console.h: function declarations for console related functions
+
+timer - Uses the MPC860/MPC821 timebase register for timing
+	tests.  It only uses the lower 32 bits
+
+vectors - MPC860/MPC821 specific vector entry points.
+	Includes CPU dependant, application independant
+	handlers: alignment.
Index: c/src/lib/libcpu/powerpc/mpc8xx/clock/Makefile.am
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/clock/Makefile.am	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
+++ c/src/lib/libcpu/powerpc/mpc8xx/clock/Makefile.am	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
@@ -0,0 +1,30 @@
+## 
+## $Id$
+## 
+
+AUTOMAKE_OPTIONS = foreign 1.4
+
+PGM = ${ARCH}/clock.rel
+
+## C sources
+C_FILES = clock.c
+
+clock_rel_OBJECTS = $(C_FILES:%.c=${ARCH}/%.o)
+
+include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
+include $(top_srcdir)/../../../../../automake/lib.am
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+AM_CFLAGS = $(CFLAGS_OS_V)
+
+$(PGM): $(clock_rel_OBJECTS)
+	$(make-rel)
+
+all-local: ${ARCH} $(PGM)
+
+EXTRA_DIST = $(C_FILES)
+
+include $(top_srcdir)/../../../../../automake/local.am
Index: c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
+++ c/src/lib/libcpu/powerpc/mpc8xx/clock/clock.c	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
@@ -0,0 +1,188 @@
+/*  clock.c
+ *
+ *  This routine initializes the PIT on the MPC8xx.
+ *  The tick frequency is specified by the bsp.
+ *
+ *  Author: Jay Monkman (jmonkman@frasca.com)
+ *  Copyright (C) 1998 by Frasca International, Inc.
+ *
+ *  Derived from c/src/lib/libcpu/ppc/ppc403/clock/clock.c:
+ *
+ *  Author: Andrew Bray <andy@i-cubed.co.uk>
+ *
+ *  COPYRIGHT (c) 1995 by i-cubed ltd.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of i-cubed limited not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      i-cubed limited makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/lib/libcpu/hppa1_1/clock/clock.c:
+ *
+ *  COPYRIGHT (c) 1989-1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#include <bsp.h>
+#include <clockdrv.h>
+#include <rtems/libio.h>
+
+#include <stdlib.h>                     /* for atexit() */
+#include <mpc8xx.h>
+
+extern rtems_cpu_table           Cpu_table;             /* owned by BSP */
+
+volatile rtems_unsigned32 Clock_driver_ticks;
+extern volatile m8xx_t m8xx;
+
+void Clock_exit( void );
+ 
+/*
+ * These are set by clock driver during its init
+ */
+ 
+rtems_device_major_number rtems_clock_major = ~0;
+rtems_device_minor_number rtems_clock_minor;
+ 
+/*
+ *  ISR Handler
+ */
+rtems_isr Clock_isr(rtems_vector_number vector)
+{
+  m8xx.piscr |= M8xx_PISCR_PS;
+  Clock_driver_ticks++;
+  rtems_clock_tick();
+}
+
+void Install_clock(rtems_isr_entry clock_isr)
+{
+#ifdef EPPCBUG_SMC1
+  extern unsigned32 simask_copy;
+#endif /* EPPCBUG_SMC1 */
+  
+  rtems_isr_entry previous_isr;
+  rtems_unsigned32 pit_value;
+  
+  Clock_driver_ticks = 0;
+  
+  pit_value = (BSP_Configuration.microseconds_per_tick *
+               Cpu_table.clicks_per_usec) - 1 ;
+  
+  if (pit_value > 0xffff) {           /* pit is only 16 bits long */
+    rtems_fatal_error_occurred(-1);
+  }  
+  if (BSP_Configuration.ticks_per_timeslice) {
+    
+    /*
+     * initialize the interval here
+     * First tick is set to right amount of time in the future
+     * Future ticks will be incremented over last value set
+     * in order to provide consistent clicks in the face of
+     * interrupt overhead
+     */
+    
+    rtems_interrupt_catch(clock_isr, PPC_IRQ_LVL0, &previous_isr);
+    
+    m8xx.sccr &= ~(1<<24);
+    m8xx.pitc = pit_value;
+    
+    /* set PIT irq level, enable PIT, PIT interrupts */
+    /*  and clear int. status */
+    m8xx.piscr = M8xx_PISCR_PIRQ(0) |
+      M8xx_PISCR_PTE | M8xx_PISCR_PS | M8xx_PISCR_PIE; 
+    
+#ifdef EPPCBUG_SMC1
+    simask_copy = m8xx.simask | M8xx_SIMASK_LVM0;
+#endif /* EPPCBUG_SMC1 */
+    m8xx.simask |= M8xx_SIMASK_LVM0;
+  }
+  atexit(Clock_exit);
+}
+
+void
+ReInstall_clock(rtems_isr_entry new_clock_isr)
+{
+  rtems_isr_entry previous_isr;
+  rtems_unsigned32 isrlevel = 0;
+  
+  rtems_interrupt_disable(isrlevel);
+  
+  rtems_interrupt_catch(new_clock_isr, PPC_IRQ_LVL0, &previous_isr);
+  
+  rtems_interrupt_enable(isrlevel);
+}
+
+
+/*
+ * Called via atexit()
+ * Remove the clock interrupt handler by setting handler to NULL
+ */
+void
+Clock_exit(void)
+{
+  if ( BSP_Configuration.ticks_per_timeslice ) {
+    /* disable PIT and PIT interrupts */
+    m8xx.piscr &= ~(M8xx_PISCR_PTE | M8xx_PISCR_PIE); 
+    
+    (void) set_vector(0, PPC_IRQ_LVL0, 1);
+  }
+}
+
+rtems_device_driver Clock_initialize(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void *pargp
+)
+{
+  Install_clock( Clock_isr );
+ 
+  /*
+   * make major/minor avail to others such as shared memory driver
+   */
+ 
+  rtems_clock_major = major;
+  rtems_clock_minor = minor;
+ 
+  return RTEMS_SUCCESSFUL;
+}
+ 
+rtems_device_driver Clock_control(
+  rtems_device_major_number major,
+  rtems_device_minor_number minor,
+  void *pargp
+)
+{
+  rtems_libio_ioctl_args_t *args = pargp;
+  
+  if (args == 0)
+    goto done;
+  
+  /*
+   * This is hokey, but until we get a defined interface
+   * to do this, it will just be this simple...
+   */
+  
+  if (args->command == rtems_build_name('I', 'S', 'R', ' ')) {
+    Clock_isr(PPC_IRQ_LVL0);
+  }
+  else if (args->command == rtems_build_name('N', 'E', 'W', ' ')) {
+    ReInstall_clock(args->buffer);
+  }
+  
+ done:
+  return RTEMS_SUCCESSFUL;
+}
+
Index: c/src/lib/libcpu/powerpc/mpc8xx/console-generic/Makefile.am
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/console-generic/Makefile.am	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
+++ c/src/lib/libcpu/powerpc/mpc8xx/console-generic/Makefile.am	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
@@ -0,0 +1,30 @@
+## 
+## $Id$
+## 
+
+AUTOMAKE_OPTIONS = foreign 1.4
+
+PGM = ${ARCH}/console-generic.rel
+
+## C sources
+C_FILES = console-generic.c
+
+console_generic_rel_OBJECTS = $(C_FILES:%.c=${ARCH}/%.o)
+
+include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
+include $(top_srcdir)/../../../../../automake/lib.am
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+AM_CFLAGS = $(CFLAGS_OS_V)
+
+$(PGM): $(console_generic_rel_OBJECTS)
+	$(make-rel)
+
+all-local: ${ARCH} $(PGM)
+
+EXTRA_DIST = $(C_FILES)
+
+include $(top_srcdir)/../../../../../automake/local.am
Index: c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
+++ c/src/lib/libcpu/powerpc/mpc8xx/console-generic/console-generic.c	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
@@ -0,0 +1,1036 @@
+/*
+ *  General Serial I/O functions.
+ *
+ *  This file contains the functions for performing serial I/O.
+ *  The actual system calls (console_*) should be in the BSP part
+ *  of the source tree. That way different BSPs can use whichever
+ *  SMCs and SCCs they want. Originally, all the stuff was in
+ *  this file, and it caused problems with one BSP using SCC2
+ *  as /dev/console, others using SMC1 for /dev/console, etc.
+ *
+ *  On-chip resources used:
+ *   resource   minor                note
+ *    SMC1       0
+ *    SMC2       1
+ *    SCC1       2                   N/A. Hardwired as ethernet port
+ *    SCC2       3
+ *    SCC3       4
+ *    SCC4       5
+ *    BRG1
+ *    BRG2
+ *    BRG3
+ *    BRG4
+ *  Author: Jay Monkman (jmonkman@frasca.com)
+ *  Copyright (C) 1998 by Frasca International, Inc.
+ *
+ *  Derived from c/src/lib/libbsp/m68k/gen360/console/console.c written by:
+ *    W. Eric Norum
+ *    Saskatchewan Accelerator Laboratory
+ *    University of Saskatchewan
+ *    Saskatoon, Saskatchewan, CANADA
+ *    eric@skatter.usask.ca
+ *
+ *  COPYRIGHT (c) 1989-1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  Modifications by Darlene Stewart <Darlene.Stewart@iit.nrc.ca>
+ *  and Charles-Antoine Gauthier <charles.gauthier@iit.nrc.ca>
+ *  Copyright (c) 1999, National Research Council of Canada
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#include <bsp.h>
+#include <rtems/libio.h>
+#include <mpc8xx.h>
+#include <mpc8xx/console.h>
+#include <stdlib.h>
+#include <unistd.h>
+#include <termios.h>
+
+extern rtems_cpu_table Cpu_table;
+
+#ifdef EPPCBUG_SMC1
+extern unsigned32 simask_copy;
+#endif /* EPPCBUG_SMC1 */
+
+/*
+ * Interrupt-driven input buffer
+ */
+#define RXBUFSIZE       16
+
+/*
+ *  I/O buffers and pointers to buffer descriptors.
+ *  Currently, single buffered input is done. This will work only
+ *  if the Rx interrupts are serviced quickly.
+ *
+ *  TODO: Add a least double buffering for safety.
+ */
+static volatile char rxBuf[NUM_PORTS][RXBUFSIZE];
+static volatile char txBuf[NUM_PORTS];
+
+/* SCC/SMC buffer descriptors */
+static volatile m8xxBufferDescriptor_t *RxBd[NUM_PORTS], *TxBd[NUM_PORTS];
+
+/* Used to track the usage of the baud rate generators */
+static unsigned long brg_spd[4];
+static char  brg_used[4];
+
+/* Used to track termios private data for callbacks */
+struct rtems_termios_tty *ttyp[NUM_PORTS];
+
+/* Used to record previous ISR */
+static rtems_isr_entry old_handler[NUM_PORTS];
+
+/*
+ * Device-specific routines
+ */
+static int m8xx_get_brg_cd(int);
+static unsigned char m8xx_get_brg_clk(int);
+void m8xx_console_reserve_resources(rtems_configuration_table *);
+static int m8xx_smc_set_attributes(int, const struct termios*);
+static int m8xx_scc_set_attributes(int, const struct termios*);
+static rtems_isr m8xx_smc1_interrupt_handler(rtems_vector_number);
+static rtems_isr m8xx_smc2_interrupt_handler(rtems_vector_number);
+static rtems_isr m8xx_scc2_interrupt_handler(rtems_vector_number);
+#if defined(mpc860)
+static rtems_isr m8xx_scc3_interrupt_handler(rtems_vector_number);
+static rtems_isr m8xx_scc4_interrupt_handler(rtems_vector_number);
+#endif
+
+/*
+ * Compute baud-rate-generator configuration register value
+ */
+static int
+m8xx_get_brg_cd (int baud)
+{
+  int divisor;
+  int div16 = 0;
+
+  divisor = ((Cpu_table.clock_speed / 16) + (baud / 2)) / baud;
+  if (divisor > 4096) {
+    div16 = 1;
+    divisor = (divisor + 8) / 16;
+  }
+  return M8xx_BRG_EN | M8xx_BRG_EXTC_BRGCLK |
+    ((divisor - 1) << 1) | div16;
+}
+
+
+/* 
+ *  This function will fail if more that 4 baud rates have been selected
+ *  at any time since the OS started. It needs to be fixed. FIXME
+ */
+static unsigned
+char m8xx_get_brg_clk(int baud)
+{
+  int i;
+
+  /* first try to find a BRG that is already at the right speed */
+  for ( i = 0; i < 4; i++ ) {
+    if ( brg_spd[i] == baud ) {
+      break;
+    }
+  }
+
+  if ( i == 4 ) { /* I guess we didn't find one */
+    for ( i = 0; i < 4; i++ ) {
+      if ( brg_used[i] == 0 ) {
+        break;
+      }
+    }
+  }
+  if (i != 4) {
+    brg_used[i]++;
+    brg_spd[i]=baud;
+    switch (i) {
+    case 0:
+      m8xx.brgc1 = M8xx_BRG_RST;
+      m8xx.brgc1 = m8xx_get_brg_cd(baud);
+      break;
+    case 1:
+      m8xx.brgc2 = M8xx_BRG_RST;
+      m8xx.brgc2 = m8xx_get_brg_cd(baud);
+      break;
+    case 2:
+      m8xx.brgc3 = M8xx_BRG_RST;
+      m8xx.brgc3 = m8xx_get_brg_cd(baud);
+      break;
+    case 3:
+      m8xx.brgc4 = M8xx_BRG_RST;
+      m8xx.brgc4 = m8xx_get_brg_cd(baud);
+      break;
+    }
+    return i;
+  }
+
+  else
+    return 0xff;
+}
+
+
+/*
+ * Hardware-dependent portion of tcsetattr().
+ */
+static int
+m8xx_smc_set_attributes (int minor, const struct termios *t)
+{
+  int baud, brg, csize, ssize, psize;
+  rtems_unsigned16 clen, cstopb, parenb, parodd, cread; 
+
+  /* Baud rate */
+  switch (t->c_cflag & CBAUD) {
+  default:      baud = -1;      break;
+  case B50:     baud = 50;      break;
+  case B75:     baud = 75;      break;
+  case B110:    baud = 110;     break;
+  case B134:    baud = 134;     break;
+  case B150:    baud = 150;     break;
+  case B200:    baud = 200;     break;
+  case B300:    baud = 300;     break;
+  case B600:    baud = 600;     break;
+  case B1200:   baud = 1200;    break;
+  case B1800:   baud = 1800;    break;
+  case B2400:   baud = 2400;    break;
+  case B4800:   baud = 4800;    break;
+  case B9600:   baud = 9600;    break;
+  case B19200:  baud = 19200;   break;
+  case B38400:  baud = 38400;   break;
+  case B57600:  baud = 57600;   break;
+  case B115200: baud = 115200;  break;
+  case B230400: baud = 230400;  break;
+  case B460800: baud = 460800;  break;
+  }
+  if (baud > 0)
+    brg = m8xx_get_brg_clk(baud);     /* 4 BRGs, 6 serial ports - hopefully */
+                                      /*  at least 2 ports will be the same */
+ 
+  /* Number of data bits */
+  switch ( t->c_cflag & CSIZE ) {
+    case CS5:     csize = 5;       break;
+    case CS6:     csize = 6;       break;
+    case CS7:     csize = 7;       break;
+    case CS8:     csize = 8;       break;
+  }
+
+  /* Stop bits */
+  if ( t->c_cflag & CSTOPB ) {
+    cstopb = 0x0400;              /* Two stop bits */
+    ssize  = 2;
+  } else {
+    cstopb = 0x0000;              /* One stop bit */
+    ssize  = 1;
+  }
+
+  /* Parity */
+  if ( t->c_cflag & PARENB ) {
+    parenb = 0x0200;              /* Parity enabled on Tx and Rx */
+    psize  = 1;
+  } else {
+    parenb = 0x0000;              /* No parity on Tx and Rx */
+    psize  = 0;
+  }
+  
+  if ( t->c_cflag & PARODD )
+    parodd = 0x0000;              /* Odd parity */
+  else
+    parodd = 0x0100;
+
+  /* 
+   * Character Length = start + data + parity + stop - 1
+   */ 
+  switch ( 1 + csize + psize + ssize - 1 ) {
+    case 6:     clen = 0x3000;       break;
+    case 7:     clen = 0x3800;       break;
+    case 8:     clen = 0x4000;       break;
+    case 9:     clen = 0x4800;       break;
+    case 10:    clen = 0x5000;       break;
+    case 11:    clen = 0x5800;       break;
+  }
+
+  if ( t->c_cflag & CREAD )
+    cread = 0x0023;		/* UART normal operation, enable Rx and Tx */
+  else
+    cread = 0x0021;		/* UART normal operation, enable Tx */
+    
+  /* Write the SIMODE/SMCMR registers */
+  switch (minor) {
+    case SMC1_MINOR:
+      m8xx.simode = ( (m8xx.simode & 0xffff8fff) | (brg << 12) );
+      m8xx.smc1.smcmr = clen | cstopb | parenb | parodd | cread;
+      break;
+    case SMC2_MINOR:
+      m8xx.simode = ( (m8xx.simode & 0x8fffffff) | (brg << 28) );
+      m8xx.smc2.smcmr = clen | cstopb | parenb | parodd | cread;
+      break;
+  }
+  return 0;
+}
+
+
+static int
+m8xx_scc_set_attributes (int minor, const struct termios *t)
+{
+  int baud, brg;
+  rtems_unsigned16 csize, cstopb, parenb, parodd;
+
+  /* Baud rate */
+  switch (t->c_cflag & CBAUD) {
+  default:      baud = -1;      break;
+  case B50:     baud = 50;      break;
+  case B75:     baud = 75;      break;
+  case B110:    baud = 110;     break;
+  case B134:    baud = 134;     break;
+  case B150:    baud = 150;     break;
+  case B200:    baud = 200;     break;
+  case B300:    baud = 300;     break;
+  case B600:    baud = 600;     break;
+  case B1200:   baud = 1200;    break;
+  case B1800:   baud = 1800;    break;
+  case B2400:   baud = 2400;    break;
+  case B4800:   baud = 4800;    break;
+  case B9600:   baud = 9600;    break;
+  case B19200:  baud = 19200;   break;
+  case B38400:  baud = 38400;   break;
+  case B57600:  baud = 57600;   break;
+  case B115200: baud = 115200;  break;
+  case B230400: baud = 230400;  break;
+  case B460800: baud = 460800;  break;
+  }
+  if (baud > 0)
+    brg = m8xx_get_brg_clk(baud);     /* 4 BRGs, 5 serial ports - hopefully */
+                                      /*  at least 2 ports will be the same */
+                                      /*  Write the SICR register below */
+    
+  /* Number of data bits */
+  switch ( t->c_cflag & CSIZE ) {
+    case CS5:     csize = 0x0000;       break;
+    case CS6:     csize = 0x1000;       break;
+    case CS7:     csize = 0x2000;       break;
+    case CS8:     csize = 0x3000;       break;
+  }
+
+  /* Stop bits */
+  if ( t->c_cflag & CSTOPB )
+    cstopb = 0x4000;              /* Two stop bits */
+  else
+    cstopb = 0x0000;              /* One stop bit */
+    
+  /* Parity */
+  if ( t->c_cflag & PARENB )
+    parenb = 0x0010;              /* Parity enabled on Tx and Rx */
+  else
+    parenb = 0x0000;              /* No parity on Tx and Rx */
+    
+  if ( t->c_cflag & PARODD )
+    parodd = 0x0000;              /* Odd parity */
+  else
+    parodd = 0x000a;
+
+  /* Write the SICR/PSMR Registers */
+  switch (minor) {
+    case SCC2_MINOR:
+      m8xx.sicr = ( (m8xx.sicr & 0xffffc0ff) | (brg << 11) | (brg << 8) );
+      m8xx.scc2.psmr = ( (cstopb | csize | parenb | parodd) | (m8xx.scc2.psmr & 0x8fe0) );
+      break;
+  #if defined(mpc860)
+    case SCC3_MINOR:
+      m8xx.sicr = ( (m8xx.sicr & 0xffc0ffff) | (brg << 19) | (brg << 16) );
+      m8xx.scc3.psmr = ( (cstopb | csize | parenb | parodd) | (m8xx.scc3.psmr & 0x8fe0) );
+      break;
+    case SCC4_MINOR:
+      m8xx.sicr = ( (m8xx.sicr & 0xc0ffffff) | (brg << 27) | (brg << 24) );
+      m8xx.scc4.psmr = ( (cstopb | csize | parenb | parodd) | (m8xx.scc4.psmr & 0x8fe0) );
+      break;
+  #endif
+  }
+  
+  return 0;
+}
+
+
+int 
+m8xx_uart_setAttributes(
+  int minor,
+  const struct termios *t
+)
+{
+  /*
+   * Check that port number is valid
+   */
+  if ( (minor < SMC1_MINOR) || (minor > NUM_PORTS-1) ) 
+    return 0;
+
+  switch (minor) {
+    case SMC1_MINOR:
+    case SMC2_MINOR:
+      return m8xx_smc_set_attributes( minor, t );
+
+    case SCC2_MINOR:
+    case SCC3_MINOR:
+    case SCC4_MINOR:
+      return m8xx_scc_set_attributes( minor, t );
+  }
+  return 0;
+}
+
+
+/*
+ * Interrupt handlers
+ */
+static rtems_isr
+m8xx_scc2_interrupt_handler (rtems_vector_number v)
+{
+  int nb_overflow;
+
+  /*
+   * Buffer received?
+   */
+  if ((m8xx.scc2.sccm & M8xx_SCCE_RX) && (m8xx.scc2.scce & M8xx_SCCE_RX)) {
+    m8xx.scc2.scce = M8xx_SCCE_RX;    /* Clear the event */
+
+
+    /* Check that the buffer is ours */
+    if ((RxBd[SCC2_MINOR]->status & M8xx_BD_EMPTY) == 0) {
+      rtems_invalidate_multiple_data_cache_lines( 
+        RxBd[SCC2_MINOR]->buffer, 
+        RxBd[SCC2_MINOR]->length );
+      nb_overflow = rtems_termios_enqueue_raw_characters(
+        (void *)ttyp[SCC2_MINOR],
+        (char *)RxBd[SCC2_MINOR]->buffer,
+        (int)RxBd[SCC2_MINOR]->length );
+      RxBd[SCC2_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP |
+                                 M8xx_BD_INTERRUPT;
+    }
+  }
+
+  /*
+   * Buffer transmitted?
+   */
+  if (m8xx.scc2.scce & M8xx_SCCE_TX) {
+    m8xx.scc2.scce = M8xx_SCCE_TX;  /* Clear the event */
+
+    /* Check that the buffer is ours */
+    if ((TxBd[SCC2_MINOR]->status & M8xx_BD_READY) == 0)
+      rtems_termios_dequeue_characters (
+        (void *)ttyp[SCC2_MINOR],
+        (int)TxBd[SCC2_MINOR]->length);
+  }
+  m8xx.cisr = 1UL << 29;  /* Clear SCC2 interrupt-in-service bit */
+}
+
+
+#ifdef mpc860
+static rtems_isr
+m8xx_scc3_interrupt_handler (rtems_vector_number v)
+{
+  int nb_overflow;
+
+  /*
+   * Buffer received?
+   */
+  if ((m8xx.scc3.sccm & M8xx_SCCE_RX) && (m8xx.scc3.scce & M8xx_SCCE_RX)) {
+    m8xx.scc3.scce = M8xx_SCCE_RX;  /* Clear the event */
+
+
+    /* Check that the buffer is ours */
+    if ((RxBd[SCC3_MINOR]->status & M8xx_BD_EMPTY) == 0) {
+      rtems_invalidate_multiple_data_cache_lines( 
+        RxBd[SCC3_MINOR]->buffer, 
+        RxBd[SCC3_MINOR]->length );
+      nb_overflow = rtems_termios_enqueue_raw_characters(
+        (void *)ttyp[SCC3_MINOR],
+        (char *)RxBd[SCC3_MINOR]->buffer,
+        (int)RxBd[SCC3_MINOR]->length );
+      RxBd[SCC3_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP |
+                                 M8xx_BD_INTERRUPT;
+    }
+  }
+
+  /*
+   * Buffer transmitted?
+   */
+  if (m8xx.scc3.scce & M8xx_SCCE_TX) {
+    m8xx.scc3.scce = M8xx_SCCE_TX;    /* Clear the event */
+
+    /* Check that the buffer is ours */
+    if ((TxBd[SCC3_MINOR]->status & M8xx_BD_READY) == 0)
+      rtems_termios_dequeue_characters (
+        (void *)ttyp[SCC3_MINOR],
+        (int)TxBd[SCC3_MINOR]->length);
+  }
+  m8xx.cisr = 1UL << 28;  /* Clear SCC3 interrupt-in-service bit */
+}
+
+
+static rtems_isr
+m8xx_scc4_interrupt_handler (rtems_vector_number v)
+{
+  int nb_overflow;
+
+  /*
+   * Buffer received?
+   */
+  if ((m8xx.scc4.sccm & M8xx_SCCE_RX) && (m8xx.scc4.scce & M8xx_SCCE_RX)) {
+    m8xx.scc4.scce = M8xx_SCCE_RX;  /* Clear the event */
+
+
+    /* Check that the buffer is ours */
+    if ((RxBd[SCC4_MINOR]->status & M8xx_BD_EMPTY) == 0) {
+      rtems_invalidate_multiple_data_cache_lines( 
+        RxBd[SCC4_MINOR]->buffer, 
+        RxBd[SCC4_MINOR]->length );
+      nb_overflow = rtems_termios_enqueue_raw_characters(
+        (void *)ttyp[SCC4_MINOR],
+        (char *)RxBd[SCC4_MINOR]->buffer,
+        (int)RxBd[SCC4_MINOR]->length );
+      RxBd[SCC4_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP |
+                                 M8xx_BD_INTERRUPT;
+    }
+  }
+
+  /*
+   * Buffer transmitted?
+   */
+  if (m8xx.scc4.scce & M8xx_SCCE_TX) {
+    m8xx.scc4.scce = M8xx_SCCE_TX;    /* Clear the event */
+
+    /* Check that the buffer is ours */
+    if ((TxBd[SCC4_MINOR]->status & M8xx_BD_READY) == 0)
+      rtems_termios_dequeue_characters (
+        (void *)ttyp[SCC4_MINOR],
+        (int)TxBd[SCC4_MINOR]->length);
+  }
+  m8xx.cisr = 1UL << 27;  /* Clear SCC4 interrupt-in-service bit */
+}
+#endif
+
+static rtems_isr
+m8xx_smc1_interrupt_handler (rtems_vector_number v)
+{
+  int nb_overflow;
+
+  /*
+   * Buffer received?
+   */
+  if (m8xx.smc1.smce & M8xx_SMCE_RX) {
+    m8xx.smc1.smce = M8xx_SMCE_RX;  /* Clear the event */
+
+
+    /* Check that the buffer is ours */
+    if ((RxBd[SMC1_MINOR]->status & M8xx_BD_EMPTY) == 0) {
+      rtems_invalidate_multiple_data_cache_lines( 
+        RxBd[SMC1_MINOR]->buffer, 
+        RxBd[SMC1_MINOR]->length );
+      nb_overflow = rtems_termios_enqueue_raw_characters(
+        (void *)ttyp[SMC1_MINOR],
+        (char *)RxBd[SMC1_MINOR]->buffer,
+        (int)RxBd[SMC1_MINOR]->length );
+      RxBd[SMC1_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP |
+                                 M8xx_BD_INTERRUPT;
+    }
+  }
+
+  /*
+   * Buffer transmitted?
+   */
+  if (m8xx.smc1.smce & M8xx_SMCE_TX) {
+    m8xx.smc1.smce = M8xx_SMCE_TX;    /* Clear the event */
+
+    /* Check that the buffer is ours */
+    if ((TxBd[SMC1_MINOR]->status & M8xx_BD_READY) == 0)
+      rtems_termios_dequeue_characters (
+        (void *)ttyp[SMC1_MINOR],
+        (int)TxBd[SMC1_MINOR]->length);
+  }
+  m8xx.cisr = 1UL << 4;  /* Clear SMC1 interrupt-in-service bit */
+}
+
+
+static rtems_isr
+m8xx_smc2_interrupt_handler (rtems_vector_number v)
+{
+  int nb_overflow;
+
+  /*
+   * Buffer received?
+   */
+  if (m8xx.smc2.smce & M8xx_SMCE_RX) {
+    m8xx.smc2.smce = M8xx_SMCE_RX;  /* Clear the event */
+
+
+    /* Check that the buffer is ours */
+    if ((RxBd[SMC2_MINOR]->status & M8xx_BD_EMPTY) == 0) {
+      rtems_invalidate_multiple_data_cache_lines( 
+        RxBd[SMC2_MINOR]->buffer, 
+        RxBd[SMC2_MINOR]->length );
+      nb_overflow = rtems_termios_enqueue_raw_characters(
+        (void *)ttyp[SMC2_MINOR],
+        (char *)RxBd[SMC2_MINOR]->buffer,
+        (int)RxBd[SMC2_MINOR]->length );
+      RxBd[SMC2_MINOR]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP |
+                                 M8xx_BD_INTERRUPT;
+    }
+  }
+
+  /*
+   * Buffer transmitted?
+   */
+  if (m8xx.smc2.smce & M8xx_SMCE_TX) {
+    m8xx.smc2.smce = M8xx_SMCE_TX;    /* Clear the event */
+
+    /* Check that the buffer is ours */
+    if ((TxBd[SMC2_MINOR]->status & M8xx_BD_READY) == 0)
+      rtems_termios_dequeue_characters (
+        (void *)ttyp[SMC2_MINOR],
+        (int)TxBd[SMC2_MINOR]->length);
+  }
+  m8xx.cisr = 1UL << 3;  /* Clear SMC2 interrupt-in-service bit */
+}
+
+
+void
+m8xx_uart_scc_initialize (int minor)
+{
+  unsigned char brg;
+  volatile m8xxSCCparms_t *sccparms;
+  volatile m8xxSCCRegisters_t *sccregs;
+
+  /*
+   * Check that minor number is valid
+   */
+  if ( (minor < SCC2_MINOR) || (minor > NUM_PORTS-1) ) 
+    return;
+
+  /* Get the sicr clock source bit values for 9600 bps */
+  brg = m8xx_get_brg_clk(9600);
+
+  /*
+   * Allocate buffer descriptors
+   */
+  RxBd[minor] = m8xx_bd_allocate(1);
+  TxBd[minor] = m8xx_bd_allocate(1);
+
+  /*
+   *  Get the address of the parameter RAM for the specified port,
+   *  configure I/O port A,C & D and put SMC in NMSI mode, connect
+   *  the SCC to the appropriate BRG.
+   *
+   *  SCC2 TxD is shared with port A bit 12
+   *  SCC2 RxD is shared with port A bit 13
+   *  SCC1 TxD is shared with port A bit 14
+   *  SCC1 RxD is shared with port A bit 15
+   *  SCC4 DCD is shared with port C bit 4
+   *  SCC4 CTS is shared with port C bit 5
+   *  SCC3 DCD is shared with port C bit 6
+   *  SCC3 CTS is shared with port C bit 7
+   *  SCC2 DCD is shared with port C bit 8
+   *  SCC2 CTS is shared with port C bit 9
+   *  SCC1 DCD is shared with port C bit 10
+   *  SCC1 CTS is shared with port C bit 11
+   *  SCC2 RTS is shared with port C bit 14
+   *  SCC1 RTS is shared with port C bit 15
+   *  SCC4 RTS is shared with port D bit 6
+   *  SCC3 RTS is shared with port D bit 7
+   *  SCC4 TxD is shared with port D bit 8
+   *  SCC4 RxD is shared with port D bit 9
+   *  SCC3 TxD is shared with port D bit 10
+   *  SCC3 RxD is shared with port D bit 11
+   */
+  switch (minor) {
+    case SCC2_MINOR:
+      sccparms = &m8xx.scc2p;
+      sccregs = &m8xx.scc2;
+      
+      m8xx.papar |=  0x000C;        /* PA12 & PA13 are dedicated peripheral pins */
+      m8xx.padir &= ~0x000C;        /* PA13 & PA12 must not drive the UART lines */
+      m8xx.paodr &= ~0x000C;        /* PA12 & PA13 are not open drain */
+      m8xx.pcpar |=  0x0002;        /* PC14 is SCC2 RTS */
+      m8xx.pcpar &= ~0x00C0;        /* PC8 & PC9 are SCC2 DCD and CTS */
+      m8xx.pcdir &= ~0x00C2;        /* PC8, PC9 & PC14 must not drive the UART lines */
+      m8xx.pcso  |=  0x00C0;        /* Enable DCD and CTS inputs */
+      
+      m8xx.sicr &= 0xFFFF00FF;      /* Clear TCS2 & RCS2, GR2=no grant, SC2=NMSI mode */
+      m8xx.sicr |= (brg<<11) | (brg<<8); /* TCS2 = RCS2 = brg */
+      break;
+
+#ifdef mpc860
+    case SCC3_MINOR:
+      sccparms = &m8xx.scc3p;
+      sccregs = &m8xx.scc3;
+      
+      m8xx.pcpar &= ~0x0300;        /* PC6 & PC7 are SCC3 DCD and CTS */
+      m8xx.pcdir &= ~0x0300;        /* PC6 & PC7 must not drive the UART lines */
+      m8xx.pcso  |=  0x0300;        /* Enable DCD and CTS inputs */
+      m8xx.pdpar |=  0x0130;        /* PD7, PD10 & PD11 are dedicated peripheral pins */
+      
+      m8xx.sicr &= 0xFF00FFFF;      /* Clear TCS3 & RCS3, GR3=no grant, SC3=NMSI mode */
+      m8xx.sicr |= (brg<<19) | (brg<<16); /* TCS3 = RCS3 = brg */
+      break;
+
+    case SCC4_MINOR:
+      sccparms = &m8xx.scc4p;
+      sccregs = &m8xx.scc4;
+      
+      m8xx.pcpar &= ~0x0C00;        /* PC4 & PC5 are SCC4 DCD and CTS */
+      m8xx.pcdir &= ~0x0C00;        /* PC4 & PC5 must not drive the UART lines */
+      m8xx.pcso  |=  0x0C00;        /* Enable DCD and CTS inputs */
+      m8xx.pdpar |=  0x02C0;        /* PD6, PD8 & PD9 are dedicated peripheral pins */
+       
+      m8xx.sicr &= 0x00FFFFFF;      /* Clear TCS4 & RCS4, GR4=no grant, SC4=NMSI mode */
+      m8xx.sicr |= (brg<<27) | (brg<<24); /* TCS4 = RCS4 = brg */
+      break;
+#endif
+  }
+
+  /*
+   *  Set up SDMA
+   */
+  m8xx.sdcr = 0x01;                 /* as per section 16.10.2.1 MPC821UM/AD */
+
+  /*
+   *  Set up the SCC parameter RAM.
+   */
+  sccparms->rbase = (char *)RxBd[minor] - (char *)&m8xx;
+  sccparms->tbase = (char *)TxBd[minor] - (char *)&m8xx;
+
+  sccparms->rfcr = M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0);
+  sccparms->tfcr = M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0);
+#ifdef UARTS_USE_INTERRUPTS
+  sccparms->mrblr = RXBUFSIZE;      /* Maximum Rx buffer size */
+#else
+  sccparms->mrblr = 1;              /* Maximum Rx buffer size */
+#endif
+
+  sccparms->un.uart.max_idl = 10;   /* Set nb of idle chars to close buffer */
+  sccparms->un.uart.brkcr = 0;      /* Set nb of breaks to send for STOP Tx */
+
+  sccparms->un.uart.parec = 0;      /* Clear parity error counter */
+  sccparms->un.uart.frmec = 0;      /* Clear framing error counter */
+  sccparms->un.uart.nosec = 0;      /* Clear noise counter */
+  sccparms->un.uart.brkec = 0;      /* Clear break counter */
+
+  sccparms->un.uart.uaddr[0] = 0;   /* Not in multidrop mode, so clear */
+  sccparms->un.uart.uaddr[1] = 0;   /* Not in multidrop mode, so clear */
+  sccparms->un.uart.toseq  = 0;     /* Tx Out-Of-SEQuence--no XON/XOFF now */
+
+  sccparms->un.uart.character[0] = 0x8000; /* Entry is invalid */
+  sccparms->un.uart.character[1] = 0x8000; /* Entry is invalid */
+  sccparms->un.uart.character[2] = 0x8000; /* Entry is invalid */
+  sccparms->un.uart.character[3] = 0x8000; /* Entry is invalid */
+  sccparms->un.uart.character[4] = 0x8000; /* Entry is invalid */
+  sccparms->un.uart.character[5] = 0x8000; /* Entry is invalid */
+  sccparms->un.uart.character[6] = 0x8000; /* Entry is invalid */
+  sccparms->un.uart.character[7] = 0x8000; /* Entry is invalid */
+
+
+  sccparms->un.uart.rccm = 0xc0ff;  /* No masking */
+
+  /*
+   * Set up the Receive Buffer Descriptor
+   */
+  RxBd[minor]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP | M8xx_BD_INTERRUPT;
+  RxBd[minor]->length = 0;
+  RxBd[minor]->buffer = rxBuf[minor];
+
+  /*
+   * Setup the Transmit Buffer Descriptor
+   */
+  TxBd[minor]->status = M8xx_BD_WRAP;
+
+ /*
+   * Set up SCCx general and protocol-specific mode registers
+   */
+  sccregs->gsmr_h = 0x00000020;     /* RFW=low latency operation */
+  sccregs->gsmr_l = 0x00028004;     /* TDCR=RDCR=16x clock mode, MODE=uart*/
+  sccregs->scce = ~0;               /* Clear any pending event */
+  sccregs->sccm = 0;                /* Mask all interrupt/event sources */
+  sccregs->psmr = 0x3000;           /* Normal operation & mode, 1 stop bit,
+                                       8 data bits, no parity */
+  sccregs->dsr = 0x7E7E;            /* No fractional stop bits */
+  sccregs->gsmr_l = 0x00028034;     /* ENT=enable Tx, ENR=enable Rx */
+
+  /*
+   *  Initialize the Rx and Tx with the new parameters.
+   */
+  switch (minor) {
+    case SCC2_MINOR:
+      m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SCC2);
+      break;
+
+#ifdef mpc860
+    case SCC3_MINOR:
+      m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SCC3);
+      break;
+    case SCC4_MINOR:
+      m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SCC4);
+      break;
+#endif
+  }
+#ifdef UARTS_USE_INTERRUPTS
+  switch (minor) {
+    case SCC2_MINOR:
+      rtems_interrupt_catch (m8xx_scc2_interrupt_handler,
+                             PPC_IRQ_CPM_SCC2,
+                             &old_handler[minor]);
+
+      sccregs->sccm = 3;            /* Enable SCC2 Rx & Tx interrupts */
+      m8xx.cimr |= 1UL <<  29;      /* Enable SCC2 interrupts */
+      break;
+
+#ifdef mpc860
+    case SCC3_MINOR:
+      rtems_interrupt_catch (m8xx_scc3_interrupt_handler,
+                             PPC_IRQ_CPM_SCC3,
+                             &old_handler[minor]);
+
+      sccregs->sccm = 3;            /* Enable SCC2 Rx & Tx interrupts */
+      m8xx.cimr |= 1UL <<  28;      /* Enable SCC2 interrupts */
+      break;
+      
+    case SCC4_MINOR:
+      rtems_interrupt_catch (m8xx_scc4_interrupt_handler,
+                             PPC_IRQ_CPM_SCC4,
+                             &old_handler[minor]);
+
+      sccregs->sccm = 3;            /* Enable SCC2 Rx & Tx interrupts */
+      m8xx.cimr |= 1UL <<  27;      /* Enable SCC2 interrupts */
+      break;
+#endif /* mpc860 */
+  }
+#endif /* UARTS_USE_INTERRUPTS */
+}
+
+
+void
+m8xx_uart_smc_initialize (int minor)
+{
+  unsigned char brg;
+  volatile m8xxSMCparms_t *smcparms;
+  volatile m8xxSMCRegisters_t *smcregs;
+
+  /*
+   * Check that minor number is valid
+   */
+  if ( (minor < SMC1_MINOR) || (minor > SMC2_MINOR) ) 
+    return;
+
+  /* Get the simode clock source bit values for 9600 bps */
+  brg = m8xx_get_brg_clk(9600);
+
+  /*
+   * Allocate buffer descriptors
+   */
+  RxBd[minor] = m8xx_bd_allocate (1);
+  TxBd[minor] = m8xx_bd_allocate (1);
+
+  /*
+   *  Get the address of the parameter RAM for the specified port,
+   *  configure I/O port B and put SMC in NMSI mode, connect the
+   *  SMC to the appropriate BRG.
+   *
+   *  SMC2 RxD is shared with port B bit 20
+   *  SMC2 TxD is shared with port B bit 21
+   *  SMC1 RxD is shared with port B bit 24
+   *  SMC1 TxD is shared with port B bit 25
+   */
+  switch (minor) {
+    case SMC1_MINOR:
+      smcparms = &m8xx.smc1p;
+      smcregs = &m8xx.smc1;
+      
+      m8xx.pbpar |=  0x000000C0;    /* PB24 & PB25 are dedicated peripheral pins */
+      m8xx.pbdir &= ~0x000000C0;    /* PB24 & PB25 must not drive UART lines */
+      m8xx.pbodr &= ~0x000000C0;    /* PB24 & PB25 are not open drain */
+
+      m8xx.simode &= 0xFFFF0FFF;    /* Clear SMC1CS & SMC1 for NMSI mode */
+      m8xx.simode |= brg << 12;     /* SMC1CS = brg */
+      break;
+
+    case SMC2_MINOR:
+      smcparms = &m8xx.smc2p;
+      smcregs = &m8xx.smc2;
+      
+      m8xx.pbpar |=  0x00000C00;    /* PB20 & PB21 are dedicated peripheral pins */
+      m8xx.pbdir &= ~0x00000C00;    /* PB20 & PB21 must not drive the UART lines */
+      m8xx.pbodr &= ~0x00000C00;    /* PB20 & PB21 are not open drain */
+      
+      m8xx.simode &= 0x0FFFFFFF;    /* Clear SMC2CS & SMC2 for NMSI mode */
+      m8xx.simode |= brg << 28;     /* SMC2CS = brg */
+      break;
+  }
+  
+  /*
+   * Set up SMC1 parameter RAM common to all protocols
+   */
+  smcparms->rbase = (char *)RxBd[minor] - (char *)&m8xx;
+  smcparms->tbase = (char *)TxBd[minor] - (char *)&m8xx;
+  smcparms->rfcr = M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0);
+  smcparms->tfcr = M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0);
+#ifdef UARTS_USE_INTERRUPTS  
+  smcparms->mrblr = RXBUFSIZE;      /* Maximum Rx buffer size */
+#else
+  smcparms->mrblr = 1;              /* Maximum Rx buffer size */
+#endif
+
+  /*
+   * Set up SMC1 parameter RAM UART-specific parameters
+   */
+  smcparms->un.uart.max_idl = 10;   /* Set nb of idle chars to close buffer */
+  smcparms->un.uart.brkcr = 0;      /* Set nb of breaks to send for STOP Tx */
+  smcparms->un.uart.brkec = 0;      /* Clear break counter */
+
+  /*
+   * Set up the Receive Buffer Descriptor
+   */
+  RxBd[minor]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP | M8xx_BD_INTERRUPT;
+  RxBd[minor]->length = 0;
+  RxBd[minor]->buffer = rxBuf[minor];
+
+  /*
+   * Setup the Transmit Buffer Descriptor
+   */
+  TxBd[minor]->status = M8xx_BD_WRAP;
+
+  /*
+   * Set up SMCx general and protocol-specific mode registers
+   */
+  smcregs->smce = ~0;               /* Clear any pending events */
+  smcregs->smcm = 0;                /* Enable SMC Rx & Tx interrupts */
+  smcregs->smcmr = M8xx_SMCMR_CLEN(9) | M8xx_SMCMR_SM_UART;
+
+  /*
+   * Send "Init parameters" command
+   */
+  switch (minor) {
+    case SMC1_MINOR:
+      m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SMC1);
+      break;
+
+    case SMC2_MINOR:
+      m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SMC2);
+      break;
+  }
+  
+  /*
+   * Enable receiver and transmitter
+   */
+  smcregs->smcmr |= M8xx_SMCMR_TEN | M8xx_SMCMR_REN;
+#ifdef UARTS_USE_INTERRUPTS
+  switch (minor) {
+    case SMC1_MINOR:
+      rtems_interrupt_catch (m8xx_smc1_interrupt_handler,
+                                  PPC_IRQ_CPM_SMC1,
+                                  &old_handler[minor]);
+
+      smcregs->smcm = 3;            /* Enable SMC1 Rx & Tx interrupts */
+      m8xx.cimr |= 1UL <<  4;       /* Enable SMC1 interrupts */
+      break;
+      
+    case SMC2_MINOR:
+      rtems_interrupt_catch (m8xx_smc2_interrupt_handler,
+                                  PPC_IRQ_CPM_SMC2,
+                                  &old_handler[minor]);
+
+      smcregs->smcm = 3;            /* Enable SMC2 Rx & Tx interrupts */
+      m8xx.cimr |= 1UL <<  3;       /* Enable SMC2 interrupts */
+      break;
+  }
+#endif
+}
+
+void
+m8xx_uart_initialize(void)
+{
+  int i;
+  
+  for (i=0; i < 4; i++) {
+    brg_spd[i] = 0;
+    brg_used[i] = 0;
+  }
+}
+
+
+void 
+m8xx_uart_interrupts_initialize(void)
+{
+#ifdef mpc860
+  m8xx.cicr = 0x00E43F80;           /* SCaP=SCC1, SCbP=SCC2, SCcP=SCC3,
+                                       SCdP=SCC4, IRL=1, HP=PC15, IEN=1 */
+#else
+  m8xx.cicr = 0x00043F80;           /* SCaP=SCC1, SCbP=SCC2, IRL=1, HP=PC15, IEN=1 */
+#endif
+#ifdef EPPCBUG_SMC1
+  simask_copy = m8xx.simask | M8xx_SIMASK_LVM1;
+#endif /* EPPCBUG_SMC1 */
+  m8xx.simask |= M8xx_SIMASK_LVM1; /* Enable level interrupts */
+}
+
+
+int
+m8xx_uart_pollRead(
+  int minor
+)
+{
+  unsigned char c;
+
+  if (RxBd[minor]->status & M8xx_BD_EMPTY) {
+    return -1;
+  }
+  _CPU_Data_Cache_Block_Invalidate( RxBd[minor]->buffer );
+  c = ((char *)RxBd[minor]->buffer)[0];
+  RxBd[minor]->status = M8xx_BD_EMPTY | M8xx_BD_WRAP;
+  return c;
+}
+
+
+/*
+ *  TODO: Get a free buffer and set it up.
+ */
+int 
+m8xx_uart_write(
+  int minor,
+  const char *buf,
+  int len
+)
+{
+  rtems_flush_multiple_data_cache_lines( buf, len );
+  TxBd[minor]->buffer = (char *) buf;
+  TxBd[minor]->length = len;
+  TxBd[minor]->status = M8xx_BD_READY | M8xx_BD_WRAP | M8xx_BD_INTERRUPT;
+  return 0;
+}
+  
+
+int
+m8xx_uart_pollWrite(
+  int minor,
+  const char *buf,
+  int len
+)
+{
+  while (len--) {
+    while (TxBd[minor]->status & M8xx_BD_READY)
+      continue;
+    txBuf[minor] = *buf++;
+    _CPU_Data_Cache_Block_Flush( &txBuf[minor] );
+    TxBd[minor]->buffer = &txBuf[minor];
+    TxBd[minor]->length = 1;
+    TxBd[minor]->status = M8xx_BD_READY | M8xx_BD_WRAP;
+  }
+  return 0;
+}
+
+void
+m8xx_uart_reserve_resources(
+  rtems_configuration_table *configuration
+)
+{
+  rtems_termios_reserve_resources (configuration, NUM_PORTS);
+}
Index: c/src/lib/libcpu/powerpc/mpc8xx/cpm/Makefile.am
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/cpm/Makefile.am	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
+++ c/src/lib/libcpu/powerpc/mpc8xx/cpm/Makefile.am	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
@@ -0,0 +1,38 @@
+## 
+## $Id$
+## 
+
+AUTOMAKE_OPTIONS = foreign 1.4
+
+PGM = ${ARCH}/cp.rel
+
+## C sources
+C_FILES = cp.c dpram.c
+
+clock_rel_OBJECTS = $(C_FILES:%.c=${ARCH}/%.o)
+
+include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
+include $(top_srcdir)/../../../../../automake/lib.am
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+AM_CFLAGS = $(CFLAGS_OS_V)
+
+$(PGM): $(clock_rel_OBJECTS)
+	$(make-rel)
+
+all-local: ${ARCH} $(PGM)
+
+EXTRA_DIST = $(C_FILES)
+
+include $(top_srcdir)/../../../../../automake/local.am
+
+
+
+
+
+
+
+
Index: c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
+++ c/src/lib/libcpu/powerpc/mpc8xx/cpm/cp.c	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
@@ -0,0 +1,34 @@
+/*
+ * cp.c
+ *
+ * MPC8xx CPM RISC Communication Processor routines.
+ * 
+ * Based on code (alloc860.c in eth_comm port) by
+ * Jay Monkman (jmonkman@frasca.com),
+ * which, in turn, is based on code by
+ * W. Eric Norum (eric@skatter.usask.ca).
+ *
+ * Modifications by Darlene Stewart (Darlene.Stewart@iit.nrc.ca):
+ * Copyright (c) 1999, National Research Council of Canada
+ */
+
+#include <bsp.h>
+#include <rtems/rtems/intr.h>
+#include <rtems/error.h>
+
+/*
+ * Send a command to the CPM RISC processer
+ */
+void m8xx_cp_execute_cmd( unsigned16 command )
+{
+  rtems_unsigned16 lvl;
+  
+  rtems_interrupt_disable(lvl);
+  while (m8xx.cpcr & M8xx_CR_FLG) {
+    continue;
+  }
+
+  m8xx.cpcr = command | M8xx_CR_FLG;
+  rtems_interrupt_enable (lvl);
+}
+
Index: c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
+++ c/src/lib/libcpu/powerpc/mpc8xx/cpm/dpram.c	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
@@ -0,0 +1,89 @@
+/*
+ * dpram.c
+ *
+ * MPC8xx dual-port RAM allocation routines
+ * 
+ * Based on code (alloc860.c in eth_comm port) by
+ * Jay Monkman (jmonkman@frasca.com),
+ * which, in turn, is based on code by
+ * W. Eric Norum (eric@skatter.usask.ca).
+ *
+ *
+ * Modifications :
+ * Copyright (c) 1999, National Research Council of Canada
+ */
+
+#include <bsp.h>
+#include <rtems/rtems/intr.h>
+#include <rtems/error.h>
+
+/*
+ * Allocation order:
+ *      - Dual-Port RAM section 0
+ *      - Dual-Port RAM section 1
+ *      - Dual-Port RAM section 2
+ *      - Dual-Port RAM section 3
+ *      - Dual-Port RAM section 4
+ */
+static struct {
+  unsigned8     *base;
+  unsigned int  size;
+  unsigned int  used;
+} dpram_regions[] = {
+  { (char *)&m8xx.dpram0[0],    sizeof m8xx.dpram0,     0 },
+  { (char *)&m8xx.dpram1[0],    sizeof m8xx.dpram1,     0 },
+  { (char *)&m8xx.dpram2[0],    sizeof m8xx.dpram2,     0 },
+  { (char *)&m8xx.dpram3[0],    sizeof m8xx.dpram3,     0 },
+  { (char *)&m8xx.dpram4[0],    sizeof m8xx.dpram4,     0 },
+};
+
+#define	NUM_DPRAM_REGIONS	(sizeof(dpram_regions) / sizeof(dpram_regions[0]))
+
+void *
+m8xx_dpram_allocate( unsigned int byte_count )
+{
+  unsigned int i;
+  ISR_Level level;
+  void *blockp = NULL;
+  
+  byte_count = (byte_count + 3) & ~0x3;
+  
+  /*
+   * Running with interrupts disabled is usually considered bad
+   * form, but this routine is probably being run as part of an
+   * initialization sequence so the effect shouldn't be too severe.
+   */
+  _ISR_Disable (level);
+  
+  for ( i = 0; i < NUM_DPRAM_REGIONS; i++ ) {
+    /*
+     * Verify that the region is available for use.
+     * This test is necessary because if extra microcode modules
+     * are installed, some regions are locked and unavailable.
+     * See MPC860 User's Manual Pages 19-9 to 19-11.
+     */
+    if (dpram_regions[i].used == 0) {
+      volatile unsigned char *cp = dpram_regions[i].base;
+      *cp = 0xAA;
+      if (*cp != 0xAA)
+        dpram_regions[i].used = dpram_regions[i].size;
+      else {
+        *cp = 0x55;
+        if (*cp != 0x55)
+          dpram_regions[i].used = dpram_regions[i].size;
+      }
+      *cp = 0x0;
+    }
+    if (dpram_regions[i].size - dpram_regions[i].used >= byte_count) {
+      blockp = dpram_regions[i].base + dpram_regions[i].used;
+      dpram_regions[i].used += byte_count;
+      break;
+    }
+  }
+  
+  _ISR_Enable(level);
+  
+  if (blockp == NULL)
+    rtems_panic("Can't allocate %d bytes of dual-port RAM.\n", byte_count);
+  return blockp;
+}
Index: c/src/lib/libcpu/powerpc/mpc8xx/include/Makefile.am
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/include/Makefile.am	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
+++ c/src/lib/libcpu/powerpc/mpc8xx/include/Makefile.am	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
@@ -0,0 +1,28 @@
+## 
+## $Id$
+## 
+
+AUTOMAKE_OPTIONS = foreign 1.4
+
+H_FILES = mpc8xx.h
+MPC8XX_H_FILES = console.h cpm.h mmu.h
+
+noinst_HEADERS = $(H_FILES) $(MPC8XX_H_FILES)
+
+PREINSTALL_FILES = \
+$(PROJECT_INCLUDE)/mpc8xx \
+$(H_FILES:%.h=$(PROJECT_INCLUDE)/%.h) \
+$(MPC8XX_H_FILES:%.h=$(PROJECT_INCLUDE)/mpc8xx/%.h)
+
+$(PROJECT_INCLUDE)/mpc8xx:
+	$(mkinstalldirs) $@
+
+$(PROJECT_INCLUDE)/%.h: %.h
+	$(INSTALL_DATA) $< $@
+
+$(PROJECT_INCLUDE)/mpc8xx/%.h: %.h
+	$(INSTALL_DATA) $< $@
+
+all-local: $(PREINSTALL_FILES) 
+
+include $(top_srcdir)/../../../../../automake/local.am
Index: c/src/lib/libcpu/powerpc/mpc8xx/include/console.h
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/include/console.h	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
+++ c/src/lib/libcpu/powerpc/mpc8xx/include/console.h	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
@@ -0,0 +1,37 @@
+/*
+ *  $Id$
+ */
+
+#ifndef _M8xx_CONSOLE_H_
+#define _M8xx_CONSOLE_H_
+
+#include <rtems/libio.h>
+
+void m8xx_uart_reserve_resources(rtems_configuration_table *configuration);
+void m8xx_uart_initialize(void);
+void m8xx_uart_interrupts_initialize(void);
+void m8xx_uart_scc_initialize (int minor);
+void m8xx_uart_smc_initialize (int minor);
+
+/* Termios callbacks */
+int m8xx_uart_pollRead(int minor);
+int m8xx_uart_pollWrite(int minor, const char* buf, int len);
+int m8xx_uart_write(int minor, const char *buf, int len);
+int m8xx_uart_setAttributes(int, const struct termios* t);
+
+
+#ifdef mpc860
+#define NUM_PORTS 6                /* number of serial ports for mpc860 */
+#else
+#define NUM_PORTS 4                /* number of serial ports for mpc821 */
+#endif
+
+#define SMC1_MINOR    0
+#define SMC2_MINOR    1
+#define SCC1_MINOR    2
+#define SCC2_MINOR    3
+#define SCC3_MINOR    4
+#define SCC4_MINOR    5
+
+
+#endif
Index: c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
+++ c/src/lib/libcpu/powerpc/mpc8xx/include/cpm.h	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
@@ -0,0 +1,38 @@
+/* 
+ * cpm.h
+ * 
+ * This include file contains definitions pertaining 
+ * to the Communications Processor Module (CPM) on the MPC8xx.
+ *
+ * Copyright (c) 1999, National Research Council of Canada
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.OARcorp.com/rtems/license.html.
+ */
+
+#ifndef __M8xx_CPM_h
+#define __M8xx_CPM_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <bsp.h>
+
+/* Functions */
+
+void m8xx_cp_execute_cmd( unsigned16 command );
+void *m8xx_dpram_allocate( unsigned int byte_count );
+
+#define m8xx_bd_allocate(count)		\
+		m8xx_dpram_allocate( (count) * sizeof(m8xxBufferDescriptor_t) )
+#define m8xx_RISC_timer_table_allocate(count)	\
+		m8xx_dpram_allocate( (count) * 4 )
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/* end of include file */
Index: c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
+++ c/src/lib/libcpu/powerpc/mpc8xx/include/mmu.h	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
@@ -0,0 +1,49 @@
+/* 
+ * mmu.h
+ * 
+ * This include file contains definitions pertaining 
+ * to the MMU on the MPC8xx.
+ *
+ * Copyright (c) 1999, National Research Council of Canada
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.OARcorp.com/rtems/license.html.
+ */
+
+#ifndef __M8xx_MMU_h
+#define __M8xx_MMU_h
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <bsp.h>
+
+/*
+ * The MMU_TLB_table is used to statically initialize the Table Lookaside
+ * Buffers in the MMU of an MPC8xx.
+ */
+typedef struct {
+  unsigned32	mmu_epn;	/* Effective Page Number */
+  unsigned32	mmu_twc;	/* Tablewalk Control Register */
+  unsigned32	mmu_rpn;	/* Real Page Number */
+} MMU_TLB_table_t;
+
+/*
+ * The MMU_TLB_table and its size, MMU_N_TLB_Table_Entries, must be 
+ * supplied by the BSP.
+ */
+extern MMU_TLB_table_t MMU_TLB_table[];	/* MMU TLB table supplied by BSP */
+extern int MMU_N_TLB_Table_Entries;	/* Number of entries in MMU TLB table */
+
+/* Functions */
+
+void mmu_init( void );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+/* end of include file */
Index: c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
+++ c/src/lib/libcpu/powerpc/mpc8xx/include/mpc8xx.h	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
@@ -0,0 +1,1399 @@
+/*
+**************************************************************************
+**************************************************************************
+**                                                                      **
+**       MOTOROLA MPC860/MPC821 PORTABLE SYSTEMS MICROPROCESSOR         **
+**                                                                      **
+**                        HARDWARE DECLARATIONS                         **
+**                                                                      **
+**                                                                      **
+**  Submitted By:                                                       **
+**                                                                      **
+**      W. Eric Norum                                                   **
+**      Saskatchewan Accelerator Laboratory                             **
+**      University of Saskatchewan                                      **
+**      107 North Road                                                  **
+**      Saskatoon, Saskatchewan, CANADA                                 **
+**      S7N 5C6                                                         **
+**                                                                      **
+**      eric@skatter.usask.ca                                           **
+**                                                                      **
+**  Modified for use with the MPC860 (original code was for MC68360)    **
+**  by                                                                  **
+**      Jay Monkman                                                     **
+**      Frasca International, Inc.                                      **
+**      906 E. Airport Rd.                                              **
+**      Urbana, IL, 61801                                               **
+**                                                                      **
+**      jmonkman@frasca.com                                             **
+**                                                                      **
+**  Modified further for use with the MPC821 by:                        **
+**      Andrew Bray <andy@chaos.org.uk>                                 **
+**                                                                      **
+**  With some corrections/additions by:                                 **
+**      Darlene A. Stewart and                                          **
+**      Charles-Antoine Gauthier                                        **
+**      Institute for Information Technology                            **
+**      National Research Council of Canada                             **
+**      Ottawa, ON  K1A 0R6                                             **
+**                                                                      **
+**      Darlene.Stewart@iit.nrc.ca                                      **
+**      charles.gauthier@iit.nrc.ca                                     **
+**                                                                      **
+**      Corrections/additions:                                          **
+**        Copyright (c) 1999, National Research Council of Canada       **
+**************************************************************************
+**************************************************************************
+*/
+
+#ifndef __MPC8xx_h
+#define __MPC8xx_h
+
+#ifndef ASM
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Macros for accessing Special Purpose Registers (SPRs)
+ */
+#define _mtspr(_spr,_reg)   __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) )
+#define _mfspr(_reg,_spr)   __asm__ volatile ( "mfspr %0, %1\n" : "=r" ((_reg)) : "i" ((_spr)) )
+
+#define _isync   __asm__ volatile ("isync\n"::)
+
+/*
+ * Core Registers (SPRs)
+ */
+#define M8xx_DEC        22      /* Decrementer Register */
+#define M8xx_DER        149     /* Debug Enable Register */
+#define M8xx_ICTRL      158     /* Instruction Support Control Register */
+#define M8xx_TBL_WR     284     /* Timebase Lower Write Register */
+#define M8xx_TBU_WR     285     /* Timebase Upper Write Register */
+#define M8xx_IMMR       638     /* Internal Memory Map Register */
+
+/*
+ * Cache Control Registers (SPRs)
+ */
+#define M8xx_IC_CST     560     /* Instruction Cache Control and Status Register */
+#define M8xx_DC_CST     568     /* Data Cache Control and Status Register */
+#define M8xx_IC_ADR     561     /* Instruction Cache Address Register */
+#define M8xx_DC_ADR     569     /* Data Cache Address Register */
+#define M8xx_IC_DAT     562     /* Instruction Cache Data Port Register */
+#define M8xx_DC_DAT     570     /* Data Cache Data Port Register */
+
+/*
+ * MMU Registers (SPRs)
+ */
+/* Control Registers */
+#define M8xx_MI_CTR     784     /* IMMU Control Register */
+#define M8xx_MD_CTR     792     /* DMMU Control Register */
+/* TLB Source Registers */
+#define M8xx_MI_EPN     787     /* IMMU Effective Page Number Register (EPN) */
+#define M8xx_MD_EPN     795     /* DMMU Effective Page Number Register (EPN) */
+#define M8xx_MI_TWC     789     /* IMMU Tablewalk Control Register (TWC) */
+#define M8xx_MD_TWC     797     /* DMMU Tablewalk Control Register (TWC) */
+#define M8xx_MI_RPN     790     /* IMMU Real (physical) Page Number Register (RPN) */
+#define M8xx_MD_RPN     798     /* DMMU Real (physical) Page Number Register (RPN) */
+/* Tablewalk Assist Registers */
+#define M8xx_M_TWB      796     /* MMU Tablewalk Base Register (TWB) */
+/* Protection Registers */
+#define M8xx_M_CASID    793     /* MMU Current Address Space ID Register */
+#define M8xx_MI_AP      786     /* IMMU Access Protection Register */
+#define M8xx_MD_AP      794     /* DMMU Access Protection Register */
+/* Scratch Register */
+#define M8xx_M_TW       799     /* MMU Tablewalk Special Register */
+/* Debug Registers */
+#define M8xx_MI_CAM     816     /* IMMU CAM Entry Read Register */
+#define M8xx_MI_RAM0    817     /* IMMU RAM Entry Read Register 0 */
+#define M8xx_MI_RAM1    818     /* IMMU RAM Entry Read Register 1 */
+#define M8xx_MD_CAM     824     /* DMMU CAM Entry Read Register */
+#define M8xx_MD_RAM0    825     /* DMMU RAM Entry Read Register 0 */
+#define M8xx_MD_RAM1    826     /* DMMU RAM Entry Read Register 1 */
+
+#define M8xx_MI_CTR_GPM       (1<<31)
+#define M8xx_MI_CTR_PPM       (1<<30)
+#define M8xx_MI_CTR_CIDEF     (1<<29)
+#define M8xx_MI_CTR_RSV4I     (1<<27)
+#define M8xx_MI_CTR_PPCS      (1<<25)
+#define M8xx_MI_CTR_ITLB_INDX(x) ((x)<<8)   /* ITLB index */
+
+#define M8xx_MD_CTR_GPM       (1<<31)
+#define M8xx_MD_CTR_PPM       (1<<30)
+#define M8xx_MD_CTR_CIDEF     (1<<29)
+#define M8xx_MD_CTR_WTDEF     (1<<28)
+#define M8xx_MD_CTR_RSV4D     (1<<27)
+#define M8xx_MD_CTR_TWAM      (1<<26)
+#define M8xx_MD_CTR_PPCS      (1<<25)
+#define M8xx_MD_CTR_DTLB_INDX(x) ((x)<<8)   /* DTLB index */
+
+#define M8xx_MI_EPN_VALID     (1<<9)
+
+#define M8xx_MD_EPN_VALID     (1<<9)
+
+#define M8xx_MI_TWC_G         (1<<4)
+#define M8xx_MI_TWC_PSS       (0<<2)
+#define M8xx_MI_TWC_PS512     (1<<2)
+#define M8xx_MI_TWC_PS8       (3<<2)
+#define M8xx_MI_TWC_VALID     (1)
+
+#define M8xx_MD_TWC_G         (1<<4)
+#define M8xx_MD_TWC_PSS       (0<<2)
+#define M8xx_MD_TWC_PS512     (1<<2)
+#define M8xx_MD_TWC_PS8       (3<<2)
+#define M8xx_MD_TWC_WT        (1<<1)
+#define M8xx_MD_TWC_VALID     (1)
+
+#define M8xx_MI_RPN_F         (0xf<<4)
+#define M8xx_MI_RPN_16K       (1<<3)
+#define M8xx_MI_RPN_SHARED    (1<<2)
+#define M8xx_MI_RPN_CI        (1<<1)
+#define M8xx_MI_RPN_VALID     (1)
+
+#define M8xx_MD_RPN_CHANGE    (1<<8)
+#define M8xx_MD_RPN_F         (0xf<<4)
+#define M8xx_MD_RPN_16K       (1<<3)
+#define M8xx_MD_RPN_SHARED    (1<<2)
+#define M8xx_MD_RPN_CI        (1<<1)
+#define M8xx_MD_RPN_VALID     (1)
+
+#define M8xx_MI_AP_Kp         (1)
+
+#define M8xx_MD_AP_Kp         (1)
+
+#define M8xx_CACHE_CMD_SFWT          (0x1<<24)
+#define M8xx_CACHE_CMD_ENABLE        (0x2<<24)
+#define M8xx_CACHE_CMD_CFWT          (0x3<<24)
+#define M8xx_CACHE_CMD_DISABLE       (0x4<<24)
+#define M8xx_CACHE_CMD_STLES         (0x5<<24)
+#define M8xx_CACHE_CMD_LLCB          (0x6<<24)
+#define M8xx_CACHE_CMD_CLES          (0x7<<24)
+#define M8xx_CACHE_CMD_UNLOCK        (0x8<<24)
+#define M8xx_CACHE_CMD_UNLOCKALL     (0xa<<24)
+#define M8xx_CACHE_CMD_INVALIDATE    (0xc<<24)
+#define M8xx_CACHE_CMD_FLUSH         (0xe<<24)
+
+/*
+*************************************************************************
+*                         REGISTER SUBBLOCKS                            *
+*************************************************************************
+*/
+
+/*
+ * Memory controller registers
+ */
+typedef struct m8xxMEMCRegisters_ {
+  rtems_unsigned32        _br;
+  rtems_unsigned32        _or;    /* Used to be called 'or'; reserved ANSI C++ keyword */
+} m8xxMEMCRegisters_t;
+
+/*
+ * Serial Communications Controller registers
+ */
+typedef struct m8xxSCCRegisters_ {
+  rtems_unsigned32        gsmr_l;
+  rtems_unsigned32        gsmr_h;
+  rtems_unsigned16        psmr;
+  rtems_unsigned16        _pad0;
+  rtems_unsigned16        todr;
+  rtems_unsigned16        dsr;
+  rtems_unsigned16        scce;
+  rtems_unsigned16        _pad1;
+  rtems_unsigned16        sccm;
+  rtems_unsigned8         _pad2;
+  rtems_unsigned8         sccs;
+  rtems_unsigned32        _pad3[2];
+} m8xxSCCRegisters_t;
+
+/*
+ * Serial Management Controller registers
+ */
+typedef struct m8xxSMCRegisters_ {
+  rtems_unsigned16        _pad0;
+  rtems_unsigned16        smcmr;
+  rtems_unsigned16        _pad1;
+  rtems_unsigned8         smce;
+  rtems_unsigned8         _pad2;
+  rtems_unsigned16        _pad3;
+  rtems_unsigned8         smcm;
+  rtems_unsigned8         _pad4;
+  rtems_unsigned32        _pad5;
+} m8xxSMCRegisters_t;
+
+/*
+ * Fast Ethernet Controller registers (Only on MPC8xxT)
+ */
+typedef struct m8xxFECRegisters_ {
+  rtems_unsigned32    addr_low;
+  rtems_unsigned32    addr_high;
+  rtems_unsigned32    hash_table_high;
+  rtems_unsigned32    hash_table_low;
+  rtems_unsigned32    r_des_start;
+  rtems_unsigned32    x_des_start;
+  rtems_unsigned32    r_buf_size;
+  rtems_unsigned32    _pad0[9];
+  rtems_unsigned32    ecntrl;
+  rtems_unsigned32    ievent;
+  rtems_unsigned32    imask;
+  rtems_unsigned32    ivec;
+  rtems_unsigned32    r_des_active;
+  rtems_unsigned32    x_des_active;
+  rtems_unsigned32    _pad1[10];
+  rtems_unsigned32    mii_data;
+  rtems_unsigned32    mii_speed;
+  rtems_unsigned32    _pad2[17];
+  rtems_unsigned32    r_bound;
+  rtems_unsigned32    r_fstart;
+  rtems_unsigned32    _pad3[6];
+  rtems_unsigned32    x_fstart;
+  rtems_unsigned32    _pad4[17];
+  rtems_unsigned32    fun_code;
+  rtems_unsigned32    _pad5[3];
+  rtems_unsigned32    r_cntrl;
+  rtems_unsigned32    r_hash;
+  rtems_unsigned32    _pad6[14];
+  rtems_unsigned32    x_cntrl;
+  rtems_unsigned32    _pad7[30];
+
+} m8xxFECRegisters_t;
+
+#define M8xx_FEC_IEVENT_HBERR  (1 << 31)
+#define M8xx_FEC_IEVENT_BABR   (1 << 30)
+#define M8xx_FEC_IEVENT_BABT   (1 << 29)
+#define M8xx_FEC_IEVENT_GRA    (1 << 28)
+#define M8xx_FEC_IEVENT_TFINT  (1 << 27)
+#define M8xx_FEC_IEVENT_TXB    (1 << 26)
+#define M8xx_FEC_IEVENT_RFINT  (1 << 25)
+#define M8xx_FEC_IEVENT_RXB    (1 << 24)
+#define M8xx_FEC_IEVENT_MII    (1 << 23)
+#define M8xx_FEC_IEVENT_EBERR  (1 << 22)
+#define M8xx_FEC_IMASK_HBEEN   (1 << 31)
+#define M8xx_FEC_IMASK_BREEN   (1 << 30)
+#define M8xx_FEC_IMASK_BTEN    (1 << 29)
+#define M8xx_FEC_IMASK_GRAEN   (1 << 28)
+#define M8xx_FEC_IMASK_TFIEN   (1 << 27)
+#define M8xx_FEC_IMASK_TBIEN   (1 << 26)
+#define M8xx_FEC_IMASK_RFIEN   (1 << 25)
+#define M8xx_FEC_IMASK_RBIEN   (1 << 24)
+#define M8xx_FEC_IMASK_MIIEN   (1 << 23)
+#define M8xx_FEC_IMASK_EBERREN (1 << 22)
+
+/*
+*************************************************************************
+*                         Miscellaneous Parameters                      *
+*************************************************************************
+*/
+typedef struct m8xxMiscParms_ {
+  rtems_unsigned16        rev_num;
+  rtems_unsigned16        _res1;
+  rtems_unsigned32        _res2;
+  rtems_unsigned32        _res3;
+} m8xxMiscParms_t;
+
+/*
+*************************************************************************
+*                              RISC Timers                              *
+*************************************************************************
+*/
+typedef struct m8xxTimerParms_ {
+  rtems_unsigned16        tm_base;
+  rtems_unsigned16        _tm_ptr;
+  rtems_unsigned16        _r_tmr;
+  rtems_unsigned16        _r_tmv;
+  rtems_unsigned32        tm_cmd;
+  rtems_unsigned32        tm_cnt;
+} m8xxTimerParms_t;
+
+/*
+ * RISC Controller Configuration Register (RCCR)
+ * All other bits in this register are reserved.
+ */
+#define M8xx_RCCR_TIME          (1<<15)    /* Enable timer */
+#define M8xx_RCCR_TIMEP(x)      ((x)<<8)   /* Timer period */
+#define M8xx_RCCR_DR1M          (1<<7)     /* IDMA Rqst 1 Mode */
+#define M8xx_RCCR_DR0M          (1<<6)     /* IDMA Rqst 0 Mode */
+#define M8xx_RCCR_DRQP(x)       ((x)<<4)   /* IDMA Rqst Priority */
+#define M8xx_RCCR_EIE           (1<<3)     /* External Interrupt Enable */
+#define M8xx_RCCR_SCD           (1<<2)     /* Scheduler Configuration */
+#define M8xx_RCCR_ERAM(x)       (x)        /* Enable RAM Microcode */
+
+/*
+ * Command register
+ * Set up this register before issuing a M8xx_CR_OP_SET_TIMER command.
+ */
+#define M8xx_TM_CMD_V           (1<<31)         /* Set to enable timer */
+#define M8xx_TM_CMD_R           (1<<30)         /* Set for automatic restart */
+#define M8xx_TM_CMD_PWM         (1<<29)         /* Set for PWM operation */
+#define M8xx_TM_CMD_TIMER(x)    ((x)<<16)       /* Select timer */
+#define M8xx_TM_CMD_PERIOD(x)   (x)             /* Timer period (16 bits) */
+
+/*
+*************************************************************************
+*                               DMA Controllers                         *
+*************************************************************************
+*/
+typedef struct m8xxIDMAparms_ {
+  rtems_unsigned16        ibase;
+  rtems_unsigned16        dcmr;
+  rtems_unsigned32        _sapr;
+  rtems_unsigned32        _dapr;
+  rtems_unsigned16        ibptr;
+  rtems_unsigned16        _write_sp;
+  rtems_unsigned32        _s_byte_c;
+  rtems_unsigned32        _d_byte_c;
+  rtems_unsigned32        _s_state;
+  rtems_unsigned32        _itemp[4];
+  rtems_unsigned32        _sr_mem;
+  rtems_unsigned16        _read_sp;
+  rtems_unsigned16        _res0;
+  rtems_unsigned16        _res1;
+  rtems_unsigned16        _res2;
+  rtems_unsigned32        _d_state;
+} m8xxIDMAparms_t;
+
+
+/*
+*************************************************************************
+*                               DSP                                     *
+*************************************************************************
+*/
+typedef struct m8xxDSPparms_ {
+  rtems_unsigned32        fdbase;
+  rtems_unsigned32        _fd_ptr;
+  rtems_unsigned32        _dstate;
+  rtems_unsigned32        _pad0;
+  rtems_unsigned16        _dstatus;
+  rtems_unsigned16        _i;
+  rtems_unsigned16        _tap;
+  rtems_unsigned16        _cbase;
+  rtems_unsigned16        _pad1;
+  rtems_unsigned16        _xptr;
+  rtems_unsigned16        _pad2;
+  rtems_unsigned16        _yptr;
+  rtems_unsigned16        _m;
+  rtems_unsigned16        _pad3;
+  rtems_unsigned16        _n;
+  rtems_unsigned16        _pad4;
+  rtems_unsigned16        _k;
+  rtems_unsigned16        _pad5;
+} m8xxDSPparms_t;
+
+/*
+*************************************************************************
+*                   Serial Communication Controllers                    *
+*************************************************************************
+*/
+typedef struct m8xxSCCparms_ {
+  rtems_unsigned16        rbase;
+  rtems_unsigned16        tbase;
+  rtems_unsigned8         rfcr;
+  rtems_unsigned8         tfcr;
+  rtems_unsigned16        mrblr;
+  rtems_unsigned32        _rstate;
+  rtems_unsigned32        _pad0;
+  rtems_unsigned16        _rbptr;
+  rtems_unsigned16        _pad1;
+  rtems_unsigned32        _pad2;
+  rtems_unsigned32        _tstate;
+  rtems_unsigned32        _pad3;
+  rtems_unsigned16        _tbptr;
+  rtems_unsigned16        _pad4;
+  rtems_unsigned32        _pad5;
+  rtems_unsigned32        _rcrc;
+  rtems_unsigned32        _tcrc;
+  union {
+    struct {
+      rtems_unsigned32        _res0;
+      rtems_unsigned32        _res1;
+      rtems_unsigned16        max_idl;
+      rtems_unsigned16        _idlc;
+      rtems_unsigned16        brkcr;
+      rtems_unsigned16        parec;
+      rtems_unsigned16        frmec;
+      rtems_unsigned16        nosec;
+      rtems_unsigned16        brkec;
+      rtems_unsigned16        brkln;
+      rtems_unsigned16        uaddr[2];
+      rtems_unsigned16        _rtemp;
+      rtems_unsigned16        toseq;
+      rtems_unsigned16        character[8];
+      rtems_unsigned16        rccm;
+      rtems_unsigned16        rccr;
+      rtems_unsigned16        rlbc;
+    } uart;
+  } un;
+} m8xxSCCparms_t;
+
+typedef struct m8xxSCCENparms_ {
+  rtems_unsigned16        rbase;
+  rtems_unsigned16        tbase;
+  rtems_unsigned8         rfcr;
+  rtems_unsigned8         tfcr;
+  rtems_unsigned16        mrblr;
+  rtems_unsigned32        _rstate;
+  rtems_unsigned32        _pad0;
+  rtems_unsigned16        _rbptr;
+  rtems_unsigned16        _pad1;
+  rtems_unsigned32        _pad2;
+  rtems_unsigned32        _tstate;
+  rtems_unsigned32        _pad3;
+  rtems_unsigned16        _tbptr;
+  rtems_unsigned16        _pad4;
+  rtems_unsigned32        _pad5;
+  rtems_unsigned32        _rcrc;
+  rtems_unsigned32        _tcrc;
+  union {
+    struct {
+      rtems_unsigned32        _res0;
+      rtems_unsigned32        _res1;
+      rtems_unsigned16        max_idl;
+      rtems_unsigned16        _idlc;
+      rtems_unsigned16        brkcr;
+      rtems_unsigned16        parec;
+      rtems_unsigned16        frmec;
+      rtems_unsigned16        nosec;
+      rtems_unsigned16        brkec;
+      rtems_unsigned16        brkln;
+      rtems_unsigned16        uaddr[2];
+      rtems_unsigned16        _rtemp;
+      rtems_unsigned16        toseq;
+      rtems_unsigned16        character[8];
+      rtems_unsigned16        rccm;
+      rtems_unsigned16        rccr;
+      rtems_unsigned16        rlbc;
+    } uart;
+    struct {
+      rtems_unsigned32        c_pres;
+      rtems_unsigned32        c_mask;
+      rtems_unsigned32        crcec;
+      rtems_unsigned32        alec;
+      rtems_unsigned32        disfc;
+      rtems_unsigned16        pads;
+      rtems_unsigned16        ret_lim;
+      rtems_unsigned16        _ret_cnt;
+      rtems_unsigned16        mflr;
+      rtems_unsigned16        minflr;
+      rtems_unsigned16        maxd1;
+      rtems_unsigned16        maxd2;
+      rtems_unsigned16        _maxd;
+      rtems_unsigned16        dma_cnt;
+      rtems_unsigned16        _max_b;
+      rtems_unsigned16        gaddr1;
+      rtems_unsigned16        gaddr2;
+      rtems_unsigned16        gaddr3;
+      rtems_unsigned16        gaddr4;
+      rtems_unsigned32        _tbuf0data0;
+      rtems_unsigned32        _tbuf0data1;
+      rtems_unsigned32        _tbuf0rba0;
+      rtems_unsigned32        _tbuf0crc;
+      rtems_unsigned16        _tbuf0bcnt;
+      rtems_unsigned16        paddr_h;
+      rtems_unsigned16        paddr_m;
+      rtems_unsigned16        paddr_l;
+      rtems_unsigned16        p_per;
+      rtems_unsigned16        _rfbd_ptr;
+      rtems_unsigned16        _tfbd_ptr;
+      rtems_unsigned16        _tlbd_ptr;
+      rtems_unsigned32        _tbuf1data0;
+      rtems_unsigned32        _tbuf1data1;
+      rtems_unsigned32        _tbuf1rba0;
+      rtems_unsigned32        _tbuf1crc;
+      rtems_unsigned16        _tbuf1bcnt;
+      rtems_unsigned16        _tx_len;
+      rtems_unsigned16        iaddr1;
+      rtems_unsigned16        iaddr2;
+      rtems_unsigned16        iaddr3;
+      rtems_unsigned16        iaddr4;
+      rtems_unsigned16        _boff_cnt;
+      rtems_unsigned16        taddr_l;
+      rtems_unsigned16        taddr_m;
+      rtems_unsigned16        taddr_h;
+    } ethernet;
+  } un;
+} m8xxSCCENparms_t;
+
+/*
+ * Receive and transmit function code register bits
+ * These apply to the function code registers of all devices, not just SCC.
+ */
+#define M8xx_RFCR_BO(x)         ((x)<<3)
+#define M8xx_RFCR_MOT           (2<<3)
+#define M8xx_RFCR_DMA_SPACE(x)  (x)
+#define M8xx_TFCR_BO(x)         ((x)<<3)
+#define M8xx_TFCR_MOT           (2<<3)
+#define M8xx_TFCR_DMA_SPACE(x)  (x)
+
+/*
+ * Event and mask registers (SCCE, SCCM)
+ */
+#define M8xx_SCCE_BRKE  (1<<6)
+#define M8xx_SCCE_BRK   (1<<4)
+#define M8xx_SCCE_BSY   (1<<2)
+#define M8xx_SCCE_TX    (1<<1)
+#define M8xx_SCCE_RX    (1<<0)
+
+/*
+*************************************************************************
+*                     Serial Management Controllers                     *
+*************************************************************************
+*/
+typedef struct m8xxSMCparms_ {
+  rtems_unsigned16        rbase;
+  rtems_unsigned16        tbase;
+  rtems_unsigned8         rfcr;
+  rtems_unsigned8         tfcr;
+  rtems_unsigned16        mrblr;
+  rtems_unsigned32        _rstate;
+  rtems_unsigned32        _pad0;
+  rtems_unsigned16        _rbptr;
+  rtems_unsigned16        _pad1;
+  rtems_unsigned32        _pad2;
+  rtems_unsigned32        _tstate;
+  rtems_unsigned32        _pad3;
+  rtems_unsigned16        _tbptr;
+  rtems_unsigned16        _pad4;
+  rtems_unsigned32        _pad5;
+  union {
+    struct {
+      rtems_unsigned16        max_idl;
+      rtems_unsigned16        _idlc;
+      rtems_unsigned16        brkln;
+      rtems_unsigned16        brkec;
+      rtems_unsigned16        brkcr;
+      rtems_unsigned16        _r_mask;
+    } uart;
+    struct {
+      rtems_unsigned16        _pad0[5];
+    } transparent;
+  } un;
+} m8xxSMCparms_t;
+
+/*
+ * Mode register
+ */
+#define M8xx_SMCMR_CLEN(x)              ((x)<<11)    /* Character length */
+#define M8xx_SMCMR_2STOP                (1<<10)      /* 2 stop bits */
+#define M8xx_SMCMR_PARITY               (1<<9)       /* Enable parity */
+#define M8xx_SMCMR_EVEN                 (1<<8)       /* Even parity */
+#define M8xx_SMCMR_SM_GCI               (0<<4)       /* GCI Mode */
+#define M8xx_SMCMR_SM_UART              (2<<4)       /* UART Mode */
+#define M8xx_SMCMR_SM_TRANSPARENT       (3<<4)       /* Transparent Mode */
+#define M8xx_SMCMR_DM_LOOPBACK          (1<<2)       /* Local loopback mode */
+#define M8xx_SMCMR_DM_ECHO              (2<<2)       /* Echo mode */
+#define M8xx_SMCMR_TEN                  (1<<1)       /* Enable transmitter */
+#define M8xx_SMCMR_REN                  (1<<0)       /* Enable receiver */
+
+/*
+ * Event and mask registers (SMCE, SMCM)
+ */
+#define M8xx_SMCE_BRKE  (1<<6)
+#define M8xx_SMCE_BRK   (1<<4)
+#define M8xx_SMCE_BSY   (1<<2)
+#define M8xx_SMCE_TX    (1<<1)
+#define M8xx_SMCE_RX    (1<<0)
+
+/*
+*************************************************************************
+*                      Serial Peripheral Interface                      *
+*************************************************************************
+*/
+typedef struct m8xxSPIparms_ {
+  rtems_unsigned16        rbase;
+  rtems_unsigned16        tbase;
+  rtems_unsigned8         rfcr;
+  rtems_unsigned8         tfcr;
+  rtems_unsigned16        mrblr;
+  rtems_unsigned32        _rstate;
+  rtems_unsigned32        _pad0;
+  rtems_unsigned16        _rbptr;
+  rtems_unsigned16        _pad1;
+  rtems_unsigned32        _pad2;
+  rtems_unsigned32        _tstate;
+  rtems_unsigned32        _pad3;
+  rtems_unsigned16        _tbptr;
+  rtems_unsigned16        _pad4;
+  rtems_unsigned32        _pad5;
+} m8xxSPIparms_t;
+
+/*
+ * Mode register (SPMODE)
+ */
+#define M8xx_SPMODE_LOOP                (1<<14) /* Local loopback mode */
+#define M8xx_SPMODE_CI                  (1<<13) /* Clock invert */
+#define M8xx_SPMODE_CP                  (1<<12) /* Clock phase */
+#define M8xx_SPMODE_DIV16               (1<<11) /* Divide BRGCLK by 16 */
+#define M8xx_SPMODE_REV                 (1<<10) /* Reverse data */
+#define M8xx_SPMODE_MASTER              (1<<9)  /* SPI is master */
+#define M8xx_SPMODE_EN                  (1<<8)  /* Enable SPI */
+#define M8xx_SPMODE_CLEN(x)             ((x)<<4)        /* Character length */
+#define M8xx_SPMODE_PM(x)               (x)     /* Prescaler modulus */
+
+/*
+ * Mode register (SPCOM)
+ */
+#define M8xx_SPCOM_STR                  (1<<7)  /* Start transmit */
+
+/*
+ * Event and mask registers (SPIE, SPIM)
+ */
+#define M8xx_SPIE_MME   (1<<5)          /* Multi-master error */
+#define M8xx_SPIE_TXE   (1<<4)          /* Tx error */
+#define M8xx_SPIE_BSY   (1<<2)          /* Busy condition*/
+#define M8xx_SPIE_TXB   (1<<1)          /* Tx buffer */
+#define M8xx_SPIE_RXB   (1<<0)          /* Rx buffer */
+
+/*
+*************************************************************************
+*                 SDMA (SCC, SMC, SPI) Buffer Descriptors               *
+*************************************************************************
+*/
+typedef struct m8xxBufferDescriptor_ {
+  rtems_unsigned16        status;
+  rtems_unsigned16        length;
+  volatile void           *buffer;
+} m8xxBufferDescriptor_t;
+
+/*
+ * Bits in receive buffer descriptor status word
+ */
+#define M8xx_BD_EMPTY           (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
+#define M8xx_BD_WRAP            (1<<13) /* Ethernet, SCC UART, SMC UART, SPI */
+#define M8xx_BD_INTERRUPT       (1<<12) /* Ethernet, SCC UART, SMC UART, SPI */
+#define M8xx_BD_LAST            (1<<11) /* Ethernet, SPI */
+#define M8xx_BD_CONTROL_CHAR    (1<<11) /* SCC UART */
+#define M8xx_BD_FIRST_IN_FRAME  (1<<10) /* Ethernet */
+#define M8xx_BD_ADDRESS         (1<<10) /* SCC UART */
+#define M8xx_BD_CONTINUOUS      (1<<9)  /* SCC UART, SMC UART, SPI */
+#define M8xx_BD_MISS            (1<<8)  /* Ethernet */
+#define M8xx_BD_IDLE            (1<<8)  /* SCC UART, SMC UART */
+#define M8xx_BD_ADDRSS_MATCH    (1<<7)  /* SCC UART */
+#define M8xx_BD_LONG            (1<<5)  /* Ethernet */
+#define M8xx_BD_BREAK           (1<<5)  /* SCC UART, SMC UART */
+#define M8xx_BD_NONALIGNED      (1<<4)  /* Ethernet */
+#define M8xx_BD_FRAMING_ERROR   (1<<4)  /* SCC UART, SMC UART */
+#define M8xx_BD_SHORT           (1<<3)  /* Ethernet */
+#define M8xx_BD_PARITY_ERROR    (1<<3)  /* SCC UART, SMC UART */
+#define M8xx_BD_CRC_ERROR       (1<<2)  /* Ethernet */
+#define M8xx_BD_OVERRUN         (1<<1)  /* Ethernet, SCC UART, SMC UART, SPI */
+#define M8xx_BD_COLLISION       (1<<0)  /* Ethernet */
+#define M8xx_BD_CARRIER_LOST    (1<<0)  /* SCC UART, SMC UART */
+#define M8xx_BD_MASTER_ERROR    (1<<0)  /* SPI */
+
+/*
+ * Bits in transmit buffer descriptor status word
+ * Many bits have the same meaning as those in receiver buffer descriptors.
+ */
+#define M8xx_BD_READY           (1<<15) /* Ethernet, SCC UART, SMC UART, SPI */
+#define M8xx_BD_PAD             (1<<14) /* Ethernet */
+#define M8xx_BD_CTS_REPORT      (1<<11) /* SCC UART */
+#define M8xx_BD_TX_CRC          (1<<10) /* Ethernet */
+#define M8xx_BD_DEFER           (1<<9)  /* Ethernet */
+#define M8xx_BD_HEARTBEAT       (1<<8)  /* Ethernet */
+#define M8xx_BD_PREAMBLE        (1<<8)  /* SCC UART, SMC UART */
+#define M8xx_BD_LATE_COLLISION  (1<<7)  /* Ethernet */
+#define M8xx_BD_NO_STOP_BIT     (1<<7)  /* SCC UART */
+#define M8xx_BD_RETRY_LIMIT     (1<<6)  /* Ethernet */
+#define M8xx_BD_RETRY_COUNT(x)  (((x)&0x3C)>>2) /* Ethernet */
+#define M8xx_BD_UNDERRUN        (1<<1)  /* Ethernet, SPI */
+#define M8xx_BD_CARRIER_LOST    (1<<0)  /* Ethernet */
+#define M8xx_BD_CTS_LOST        (1<<0)  /* SCC UART */
+
+/*
+*************************************************************************
+*                           IDMA Buffer Descriptors                     *
+*************************************************************************
+*/
+typedef struct m8xxIDMABufferDescriptor_ {
+  rtems_unsigned16        status;
+  rtems_unsigned8         dfcr;       
+  rtems_unsigned8         sfcr;       
+  rtems_unsigned32        length;
+  void                    *source;
+  void                    *destination;
+} m8xxIDMABufferDescriptor_t;
+
+/*
+*************************************************************************
+*       RISC Communication Processor Module Command Register (CR)       *
+*************************************************************************
+*/
+#define M8xx_CR_RST             (1<<15) /* Reset communication processor */
+#define M8xx_CR_OP_INIT_RX_TX   (0<<8)  /* SCC, SMC UART, SMC GCI, SPI */
+#define M8xx_CR_OP_INIT_RX      (1<<8)  /* SCC, SMC UART, SPI */
+#define M8xx_CR_OP_INIT_TX      (2<<8)  /* SCC, SMC UART, SPI */
+#define M8xx_CR_OP_INIT_HUNT    (3<<8)  /* SCC, SMC UART */
+#define M8xx_CR_OP_STOP_TX      (4<<8)  /* SCC, SMC UART */
+#define M8xx_CR_OP_GR_STOP_TX   (5<<8)  /* SCC */
+#define M8xx_CR_OP_INIT_IDMA    (5<<8)  /* IDMA */
+#define M8xx_CR_OP_RESTART_TX   (6<<8)  /* SCC, SMC UART */
+#define M8xx_CR_OP_CLOSE_RX_BD  (7<<8)  /* SCC, SMC UART, SPI */
+#define M8xx_CR_OP_SET_GRP_ADDR (8<<8)  /* SCC */
+#define M8xx_CR_OP_SET_TIMER    (8<<8)  /* Timer */
+#define M8xx_CR_OP_GCI_TIMEOUT  (9<<8)  /* SMC GCI */
+#define M8xx_CR_OP_RESERT_BCS   (10<<8) /* SCC */
+#define M8xx_CR_OP_GCI_ABORT    (10<<8) /* SMC GCI */
+#define M8xx_CR_OP_STOP_IDMA    (11<<8) /* IDMA */
+#define M8xx_CR_OP_START_DSP    (12<<8) /* DSP */
+#define M8xx_CR_OP_INIT_DSP     (13<<8) /* DSP */
+
+#define M8xx_CR_CHAN_SCC1       (0<<4)  /* Channel selection */
+#define M8xx_CR_CHAN_I2C        (1<<4)
+#define M8xx_CR_CHAN_IDMA1      (1<<4)
+#define M8xx_CR_CHAN_SCC2       (4<<4)
+#define M8xx_CR_CHAN_SPI        (5<<4)
+#define M8xx_CR_CHAN_IDMA2      (5<<4)
+#define M8xx_CR_CHAN_TIMER      (5<<4)
+#define M8xx_CR_CHAN_SCC3       (8<<4)
+#define M8xx_CR_CHAN_SMC1       (9<<4)
+#define M8xx_CR_CHAN_DSP1       (9<<4)
+#define M8xx_CR_CHAN_SCC4       (12<<4)
+#define M8xx_CR_CHAN_SMC2       (13<<4)
+#define M8xx_CR_CHAN_DSP2       (13<<4)
+#define M8xx_CR_FLG             (1<<0)  /* Command flag */
+
+/*
+*************************************************************************
+*                 System Protection Control Register (SYPCR)            *
+*************************************************************************
+*/
+#define M8xx_SYPCR_SWTC(x)      ((x)<<16)   /* Software watchdog timer count */
+#define M8xx_SYPCR_BMT(x)       ((x)<<8)    /* Bus monitor timing */
+#define M8xx_SYPCR_BME          (1<<7)      /* Bus monitor enable */
+#define M8xx_SYPCR_SWF          (1<<3)      /* Software watchdog freeze */
+#define M8xx_SYPCR_SWE          (1<<2)      /* Software watchdog enable */
+#define M8xx_SYPCR_SWRI         (1<<1)      /* Watchdog reset/interrupt sel. */
+#define M8xx_SYPCR_SWP          (1<<0)      /* Software watchdog prescale */
+
+/*
+*************************************************************************
+*                        Memory Control Registers                       *
+*************************************************************************
+*/
+#define M8xx_UPM_AMX_8col       (0<<20) /* 8 column DRAM */
+#define M8xx_UPM_AMX_9col       (1<<20) /* 9 column DRAM */
+#define M8xx_UPM_AMX_10col      (2<<20) /* 10 column DRAM */
+#define M8xx_UPM_AMX_11col      (3<<20) /* 11 column DRAM */
+#define M8xx_UPM_AMX_12col      (4<<20) /* 12 column DRAM */
+#define M8xx_UPM_AMX_13col      (5<<20) /* 13 column DRAM */
+#define M8xx_MSR_PER(x)         (0x100<<(7-x)) /* Perity error bank (x) */
+#define M8xx_MSR_WPER           (1<<7)  /* Write protection error */
+#define M8xx_MPTPR_PTP(x)       ((x)<<8) /* Periodic timer prescaler */
+#define M8xx_BR_BA(x)           ((x)&0xffff8000) /* Base address */
+#define M8xx_BR_AT(x)           ((x)<<12) /* Address type */
+#define M8xx_BR_PS8             (1<<10)  /* 8 bit port */
+#define M8xx_BR_PS16            (2<<10)  /* 16 bit port */
+#define M8xx_BR_PS32            (0<<10)  /* 32 bit port */
+#define M8xx_BR_PARE            (1<<9)   /* Parity checking enable */
+#define M8xx_BR_WP              (1<<8)   /* Write protect */
+#define M8xx_BR_MS_GPCM         (0<<6)   /* GPCM */
+#define M8xx_BR_MS_UPMA         (2<<6)   /* UPM A */
+#define M8xx_BR_MS_UPMB         (3<<6)   /* UPM B */
+#define M8xx_MEMC_BR_V          (1<<0)  /* Base/Option register are valid */
+
+#define M8xx_MEMC_OR_32K        0xffff8000      /* Address range */
+#define M8xx_MEMC_OR_64K        0xffff0000
+#define M8xx_MEMC_OR_128K       0xfffe0000
+#define M8xx_MEMC_OR_256K       0xfffc0000
+#define M8xx_MEMC_OR_512K       0xfff80000
+#define M8xx_MEMC_OR_1M         0xfff00000
+#define M8xx_MEMC_OR_2M         0xffe00000
+#define M8xx_MEMC_OR_4M         0xffc00000
+#define M8xx_MEMC_OR_8M         0xff800000
+#define M8xx_MEMC_OR_16M        0xff000000
+#define M8xx_MEMC_OR_32M        0xfe000000
+#define M8xx_MEMC_OR_64M        0xfc000000
+#define M8xx_MEMC_OR_128        0xf8000000
+#define M8xx_MEMC_OR_256M       0xf0000000
+#define M8xx_MEMC_OR_512M       0xe0000000
+#define M8xx_MEMC_OR_1G         0xc0000000
+#define M8xx_MEMC_OR_2G         0x80000000
+#define M8xx_MEMC_OR_4G         0x00000000
+#define M8xx_MEMC_OR_ATM(x)     ((x)<<12)   /* Address type mask */
+#define M8xx_MEMC_OR_CSNT       (1<<11)     /* Chip select is negated early */
+#define M8xx_MEMC_OR_SAM        (1<<11)     /* Address lines are multiplexed */
+#define M8xx_MEMC_OR_ACS_NORM   (0<<9)      /* *CS asserted with addr lines */
+#define M8xx_MEMC_OR_ACS_QRTR   (2<<9)      /* *CS asserted 1/4 after addr */
+#define M8xx_MEMC_OR_ACS_HALF   (3<<9)      /* *CS asserted 1/2 after addr */
+#define M8xx_MEMC_OR_BI         (1<<8)      /* Burst inhibit */
+#define M8xx_MEMC_OR_SCY(x)     ((x)<<4)    /* Cycle length in clocks */
+#define M8xx_MEMC_OR_SETA       (1<<3)      /* *TA generated externally */
+#define M8xx_MEMC_OR_TRLX       (1<<2)      /* Relaxed timing in GPCM */
+#define M8xx_MEMC_OR_EHTR       (1<<1)      /* Extended hold time on reads */
+
+/*
+*************************************************************************
+*                         UPM Registers (MxMR)                          *
+*************************************************************************
+*/
+#define M8xx_MEMC_MMR_PTP(x)   ((x)<<24)    /* Periodic timer period */
+#define M8xx_MEMC_MMR_PTE      (1<<23)      /* Periodic timer enable */
+#define M8xx_MEMC_MMR_DSP(x)   ((x)<<17)    /* Disable timer period */
+#define M8xx_MEMC_MMR_G0CL(x)  ((x)<<13)    /* General line 0 control */
+#define M8xx_MEMC_MMR_UPWAIT   (1<<12)      /* GPL_x4 is UPWAITx */
+#define M8xx_MEMC_MMR_RLF(x)   ((x)<<8)     /* Read loop field */
+#define M8xx_MEMC_MMR_WLF(x)   ((x)<<4)     /* Write loop field */
+#define M8xx_MEMC_MMR_TLF(x)   ((x)<<0)     /* Timer loop field */
+/*
+*************************************************************************
+*                         Memory Command Register (MCR)                 *
+*************************************************************************
+*/
+#define M8xx_MEMC_MCR_WRITE     (0<<30)     /* WRITE command */
+#define M8xx_MEMC_MCR_READ      (1<<30)     /* READ command */
+#define M8xx_MEMC_MCR_RUN       (2<<30)     /* RUN command */
+#define M8xx_MEMC_MCR_UPMA      (0<<23)     /* Cmd is for UPMA */
+#define M8xx_MEMC_MCR_UPMB      (1<<23)     /* Cmd is for UPMB */
+#define M8xx_MEMC_MCR_MB(x)     ((x)<<13)   /* Memory bank when RUN cmd */
+#define M8xx_MEMC_MCR_MCLF(x)   ((x)<<8)    /* Memory command loop field */
+#define M8xx_MEMC_MCR_MAD(x)    (x)         /* Machine address */
+
+
+
+/*
+*************************************************************************
+*                         SI Mode Register (SIMODE)                     *
+*************************************************************************
+*/
+#define M8xx_SI_SMC2_BITS       0xFFFF0000      /* All SMC2 bits */
+#define M8xx_SI_SMC2_TDM        (1<<31) /* Multiplexed SMC2 */
+#define M8xx_SI_SMC2_BRG1       (0<<28) /* SMC2 clock souce */
+#define M8xx_SI_SMC2_BRG2       (1<<28)
+#define M8xx_SI_SMC2_BRG3       (2<<28)
+#define M8xx_SI_SMC2_BRG4       (3<<28)
+#define M8xx_SI_SMC2_CLK5       (0<<28)
+#define M8xx_SI_SMC2_CLK6       (1<<28)
+#define M8xx_SI_SMC2_CLK7       (2<<28)
+#define M8xx_SI_SMC2_CLK8       (3<<28)
+#define M8xx_SI_SMC1_BITS       0x0000FFFF      /* All SMC1 bits */
+#define M8xx_SI_SMC1_TDM        (1<<15) /* Multiplexed SMC1 */
+#define M8xx_SI_SMC1_BRG1       (0<<12) /* SMC1 clock souce */
+#define M8xx_SI_SMC1_BRG2       (1<<12)
+#define M8xx_SI_SMC1_BRG3       (2<<12)
+#define M8xx_SI_SMC1_BRG4       (3<<12)
+#define M8xx_SI_SMC1_CLK1       (0<<12)
+#define M8xx_SI_SMC1_CLK2       (1<<12)
+#define M8xx_SI_SMC1_CLK3       (2<<12)
+#define M8xx_SI_SMC1_CLK4       (3<<12)
+
+/*
+*************************************************************************
+*                  SDMA Configuration Register (SDCR)                   *
+*************************************************************************
+*/
+#define M8xx_SDCR_FREEZE        (2<<13) /* Freeze on next bus cycle */
+#define M8xx_SDCR_RAID_5        (1<<0)  /* Normal arbitration ID */
+
+/*
+*************************************************************************
+*                  SDMA Status Register (SDSR)                          *
+*************************************************************************
+*/
+#define M8xx_SDSR_SBER          (1<<7)  /* SDMA Channel bus error */
+#define M8xx_SDSR_DSP2          (1<<1)  /* DSP Chain 2 interrupt */
+#define M8xx_SDSR_DSP1          (1<<0)  /* DSP Chain 1 interrupt */
+
+/*
+*************************************************************************
+*                      Baud (sic) Rate Generators                       *
+*************************************************************************
+*/
+#define M8xx_BRG_RST            (1<<17)         /* Reset generator */
+#define M8xx_BRG_EN             (1<<16)         /* Enable generator */
+#define M8xx_BRG_EXTC_BRGCLK    (0<<14)         /* Source is BRGCLK */
+#define M8xx_BRG_EXTC_CLK2      (1<<14)         /* Source is CLK2 pin */
+#define M8xx_BRG_EXTC_CLK6      (2<<14)         /* Source is CLK6 pin */
+#define M8xx_BRG_ATB            (1<<13)         /* Autobaud */
+#define M8xx_BRG_115200         (21<<1)         /* Assume 40 MHz clock */
+#define M8xx_BRG_57600          (32<<1)
+#define M8xx_BRG_38400          (64<<1)
+#define M8xx_BRG_19200          (129<<1)
+#define M8xx_BRG_9600           (259<<1)
+#define M8xx_BRG_4800           (520<<1)
+#define M8xx_BRG_2400           (1040<<1)
+#define M8xx_BRG_1200           (2082<<1)
+#define M8xx_BRG_600            ((259<<1) | 1)
+#define M8xx_BRG_300            ((520<<1) | 1)
+#define M8xx_BRG_150            ((1040<<1) | 1)
+#define M8xx_BRG_75             ((2080<<1) | 1)
+
+#define M8xx_TGCR_CAS4          (1<<15)   /* Cascade timers 3 and 4 */
+#define M8xx_TGCR_CAS2          (1<<7)    /* Cascade timers 1 and 2 */
+#define M8xx_TGCR_FRZ1          (1<<2)    /* Halt timer if FREEZE asserted */
+#define M8xx_TGCR_FRZ2          (1<<6)    /* Halt timer if FREEZE asserted */
+#define M8xx_TGCR_FRZ3          (1<<10)   /* Halt timer if FREEZE asserted */
+#define M8xx_TGCR_FRZ4          (1<<14)   /* Halt timer if FREEZE asserted */
+#define M8xx_TGCR_STP1          (1<<1)    /* Stop timer */
+#define M8xx_TGCR_STP2          (1<<5)    /* Stop timer */
+#define M8xx_TGCR_STP3          (1<<9)    /* Stop timer */
+#define M8xx_TGCR_STP4          (1<<13)   /* Stop timer */
+#define M8xx_TGCR_RST1          (1<<0)    /* Enable timer */
+#define M8xx_TGCR_RST2          (1<<4)    /* Enable timer */
+#define M8xx_TGCR_RST3          (1<<8)    /* Enable timer */
+#define M8xx_TGCR_RST4          (1<<12)   /* Enable timer */
+#define M8xx_TGCR_GM1           (1<<3)    /* Gate Mode 1 for TMR1 or TMR2 */
+#define M8xx_TGCR_GM2           (1<<11)   /* Gate Mode 2 for TMR3 or TMR4 */
+
+#define M8xx_TMR_PS(x)          ((x)<<8)  /* Timer prescaler */
+#define M8xx_TMR_CE_RISE        (1<<6)    /* Capture on rising edge */
+#define M8xx_TMR_CE_FALL        (2<<6)    /* Capture on falling edge */
+#define M8xx_TMR_CE_ANY         (3<<6)    /* Capture on any edge */
+#define M8xx_TMR_OM_TOGGLE      (1<<5)    /* Toggle TOUTx pin */
+#define M8xx_TMR_ORI            (1<<4)    /* Interrupt on reaching reference */
+#define M8xx_TMR_RESTART        (1<<3)    /* Restart timer after reference */
+#define M8xx_TMR_ICLK_INT       (1<<1)    /* Internal clock is timer source */
+#define M8xx_TMR_ICLK_INT16     (2<<1)    /* Internal clock/16 is tmr src */
+#define M8xx_TMR_ICLK_TIN       (3<<1)    /* TIN pin is timer source */
+#define M8xx_TMR_TGATE          (1<<0)    /* TGATE controls timer */
+
+#define M8xx_PISCR_PIRQ(x)      (1<<(15-x))  /* PIT interrupt level */
+#define M8xx_PISCR_PS           (1<<7)    /* PIT Interrupt state */
+#define M8xx_PISCR_PIE          (1<<2)    /* PIT interrupt enable */
+#define M8xx_PISCR_PITF         (1<<1)    /* Stop timer when freeze asserted */
+#define M8xx_PISCR_PTE          (1<<0)    /* PIT enable */
+
+#define M8xx_TBSCR_TBIRQ(x)     (1<<(15-x))  /* TB interrupt level */
+#define M8xx_TBSCR_REFA         (1<<7)    /* TB matches TBREFF0 */
+#define M8xx_TBSCR_REFB         (1<<6)    /* TB matches TBREFF1 */
+#define M8xx_TBSCR_REFAE        (1<<3)    /* Enable ints for REFA */
+#define M8xx_TBSCR_REFBE        (1<<2)    /* Enable ints for REFB */
+#define M8xx_TBSCR_TBF          (1<<1)    /* TB stops on FREEZE */
+#define M8xx_TBSCR_TBE          (1<<0)    /* enable TB and decrementer */
+
+#define M8xx_SIMASK_IRM0        (1<<31)
+#define M8xx_SIMASK_LVM0        (1<<30)
+#define M8xx_SIMASK_IRM1        (1<<29)
+#define M8xx_SIMASK_LVM1        (1<<28)
+#define M8xx_SIMASK_IRM2        (1<<27)
+#define M8xx_SIMASK_LVM2        (1<<26)
+#define M8xx_SIMASK_IRM3        (1<<25)
+#define M8xx_SIMASK_LVM3        (1<<24)
+#define M8xx_SIMASK_IRM4        (1<<23)
+#define M8xx_SIMASK_LVM4        (1<<22)
+#define M8xx_SIMASK_IRM5        (1<<21)
+#define M8xx_SIMASK_LVM5        (1<<20)
+#define M8xx_SIMASK_IRM6        (1<<19)
+#define M8xx_SIMASK_LVM6        (1<<18)
+#define M8xx_SIMASK_IRM7        (1<<17)
+#define M8xx_SIMASK_LVM7        (1<<16)
+
+#define M8xx_SIUMCR_EARB        (1<<31)
+#define M8xx_SIUMCR_EARP0       (0<<28)
+#define M8xx_SIUMCR_EARP1       (1<<28)
+#define M8xx_SIUMCR_EARP2       (2<<28)
+#define M8xx_SIUMCR_EARP3       (3<<28)
+#define M8xx_SIUMCR_EARP4       (4<<28)
+#define M8xx_SIUMCR_EARP5       (5<<28)
+#define M8xx_SIUMCR_EARP6       (6<<28)
+#define M8xx_SIUMCR_EARP7       (7<<28)
+#define M8xx_SIUMCR_DSHW        (1<<23)
+#define M8xx_SIUMCR_DBGC0       (0<<21)
+#define M8xx_SIUMCR_DBGC1       (1<<21)
+#define M8xx_SIUMCR_DBGC2       (2<<21)
+#define M8xx_SIUMCR_DBGC3       (3<<21)
+#define M8xx_SIUMCR_DBPC0       (0<<19)
+#define M8xx_SIUMCR_DBPC1       (1<<19)
+#define M8xx_SIUMCR_DBPC2       (2<<19)
+#define M8xx_SIUMCR_DBPC3       (3<<19)
+#define M8xx_SIUMCR_FRC         (1<<17)
+#define M8xx_SIUMCR_DLK         (1<<16)
+#define M8xx_SIUMCR_PNCS        (1<<15)
+#define M8xx_SIUMCR_OPAR        (1<<14)
+#define M8xx_SIUMCR_DPC         (1<<13)
+#define M8xx_SIUMCR_MPRE        (1<<12)
+#define M8xx_SIUMCR_MLRC0       (0<<10)
+#define M8xx_SIUMCR_MLRC1       (1<<10)
+#define M8xx_SIUMCR_MLRC2       (2<<10)
+#define M8xx_SIUMCR_MLRC3       (3<<10)
+#define M8xx_SIUMCR_AEME        (1<<9)
+#define M8xx_SIUMCR_SEME        (1<<8)
+#define M8xx_SIUMCR_BSC         (1<<7)
+#define M8xx_SIUMCR_GB5E        (1<<6)
+#define M8xx_SIUMCR_B2DD        (1<<5)
+#define M8xx_SIUMCR_B3DD        (1<<4)
+
+/*
+ *  Value to write to a key register to unlock the corresponding SIU register
+ */
+#define M8xx_UNLOCK_KEY         0x55CCAA33
+ 
+/*
+*************************************************************************
+*   MPC8xx INTERNAL MEMORY MAP REGISTERS (IMMR provides base address)   *
+*************************************************************************
+*/
+typedef struct m8xx_ {
+        
+  /*
+   * SIU Block
+   */
+  rtems_unsigned32      siumcr;
+  rtems_unsigned32      sypcr;
+#if defined(mpc860)
+  rtems_unsigned32      swt;
+#elif defined(mpc821)
+  rtems_unsigned32      _pad70;
+#endif
+  rtems_unsigned16      _pad0;
+  rtems_unsigned16      swsr;
+  rtems_unsigned32      sipend;
+  rtems_unsigned32      simask;
+  rtems_unsigned32      siel;
+  rtems_unsigned32      sivec;
+  rtems_unsigned32      tesr;
+  rtems_unsigned32      _pad1[3];
+  rtems_unsigned32      sdcr;
+  rtems_unsigned8       _pad2[0x80-0x34];
+  
+  /*
+   * PCMCIA Block
+   */
+  rtems_unsigned32      pbr0;
+  rtems_unsigned32      por0;
+  rtems_unsigned32      pbr1;
+  rtems_unsigned32      por1;
+  rtems_unsigned32      pbr2;
+  rtems_unsigned32      por2;
+  rtems_unsigned32      pbr3;
+  rtems_unsigned32      por3;
+  rtems_unsigned32      pbr4;
+  rtems_unsigned32      por4;
+  rtems_unsigned32      pbr5;
+  rtems_unsigned32      por5;
+  rtems_unsigned32      pbr6;
+  rtems_unsigned32      por6;
+  rtems_unsigned32      pbr7;
+  rtems_unsigned32      por7;
+  rtems_unsigned8       _pad3[0xe0-0xc0];
+  rtems_unsigned32      pgcra;
+  rtems_unsigned32      pgcrb;
+  rtems_unsigned32      pscr;
+  rtems_unsigned32      _pad4;
+  rtems_unsigned32      pipr;
+  rtems_unsigned32      _pad5;
+  rtems_unsigned32      per;
+  rtems_unsigned32      _pad6;
+  
+  /*
+   * MEMC Block
+   */
+  m8xxMEMCRegisters_t   memc[8];
+  rtems_unsigned8       _pad7[0x164-0x140];
+  rtems_unsigned32      mar;
+  rtems_unsigned32      mcr;
+  rtems_unsigned32      _pad8;
+  rtems_unsigned32      mamr;
+  rtems_unsigned32      mbmr;
+  rtems_unsigned16      mstat;
+  rtems_unsigned16      mptpr;
+  rtems_unsigned32      mdr;
+  rtems_unsigned8       _pad9[0x200-0x180];
+  
+  /*
+   * System integration timers
+   */
+  rtems_unsigned16      tbscr;
+  rtems_unsigned16      _pad10;
+  rtems_unsigned32      tbreff0;
+  rtems_unsigned32      tbreff1;
+  rtems_unsigned8       _pad11[0x220-0x20c];
+  rtems_unsigned16      rtcsc;
+  rtems_unsigned16      _pad12;
+  rtems_unsigned32      rtc;
+  rtems_unsigned32      rtsec;
+  rtems_unsigned32      rtcal;
+  rtems_unsigned32      _pad13[4];
+  rtems_unsigned16      piscr;
+  rtems_unsigned16      _pad14;
+  rtems_unsigned16      pitc;
+  rtems_unsigned16      _pad_14_1;
+  rtems_unsigned16      pitr;
+  rtems_unsigned16      _pad_14_2;
+  rtems_unsigned8       _pad15[0x280-0x24c];
+  
+  
+  /*
+   * Clocks and Reset
+   */
+  rtems_unsigned32      sccr;
+  rtems_unsigned32      plprcr;
+  rtems_unsigned32      rsr;
+  rtems_unsigned8       _pad16[0x300-0x28c];
+  
+  
+  /*
+   * System integration timers keys
+   */
+  rtems_unsigned32      tbscrk;
+  rtems_unsigned32      tbreff0k;
+  rtems_unsigned32      tbreff1k;
+  rtems_unsigned32      tbk;
+  rtems_unsigned32      _pad17[4];
+  rtems_unsigned32      rtcsk;
+  rtems_unsigned32      rtck;
+  rtems_unsigned32      rtseck;
+  rtems_unsigned32      rtcalk;
+  rtems_unsigned32      _pad18[4];
+  rtems_unsigned32      piscrk;
+  rtems_unsigned32      pitck;
+  rtems_unsigned8       _pad19[0x380-0x348];
+  
+  /*
+   * Clocks and Reset Keys
+   */
+  rtems_unsigned32      sccrk;
+  rtems_unsigned32      plprck;
+  rtems_unsigned32      rsrk;
+  rtems_unsigned8       _pad20[0x400-0x38c];
+  rtems_unsigned8       _pad21[0x800-0x400];
+  rtems_unsigned8       _pad22[0x860-0x800];
+  
+  
+  /*
+   * I2C
+   */
+  rtems_unsigned8       i2mod;
+  rtems_unsigned8       _pad23[3];
+  rtems_unsigned8       i2add;
+  rtems_unsigned8       _pad24[3];
+  rtems_unsigned8       i2brg;
+  rtems_unsigned8       _pad25[3];
+  rtems_unsigned8       i2com;
+  rtems_unsigned8       _pad26[3];
+  rtems_unsigned8       i2cer;
+  rtems_unsigned8       _pad27[3];
+  rtems_unsigned8       i2cmr;
+  rtems_unsigned8       _pad28[0x900-0x875];
+  
+  /*
+   * DMA Block
+   */
+  rtems_unsigned32      _pad29;
+  rtems_unsigned32      sdar;
+  rtems_unsigned8       sdsr;
+  rtems_unsigned8       _pad30[3];
+  rtems_unsigned8       sdmr;
+  rtems_unsigned8       _pad31[3];
+  rtems_unsigned8       idsr1;
+  rtems_unsigned8       _pad32[3];
+  rtems_unsigned8       idmr1;
+  rtems_unsigned8       _pad33[3];
+  rtems_unsigned8       idsr2;
+  rtems_unsigned8       _pad34[3];
+  rtems_unsigned8       idmr2;
+  rtems_unsigned8       _pad35[0x930-0x91d];
+  
+  /*
+   * CPM Interrupt Control Block
+   */
+  rtems_unsigned16      civr;
+  rtems_unsigned8       _pad36[14];
+  rtems_unsigned32      cicr;
+  rtems_unsigned32      cipr;
+  rtems_unsigned32      cimr;
+  rtems_unsigned32      cisr;
+  
+  /*
+   * I/O Port Block
+   */
+  rtems_unsigned16      padir;
+  rtems_unsigned16      papar;
+  rtems_unsigned16      paodr;
+  rtems_unsigned16      padat;
+  rtems_unsigned8       _pad37[8];
+  rtems_unsigned16      pcdir;
+  rtems_unsigned16      pcpar;
+  rtems_unsigned16      pcso;
+  rtems_unsigned16      pcdat;
+  rtems_unsigned16      pcint;
+  rtems_unsigned8       _pad39[6];
+  rtems_unsigned16      pddir;
+  rtems_unsigned16      pdpar;
+  rtems_unsigned16      _pad40;
+  rtems_unsigned16      pddat;
+  rtems_unsigned8       _pad41[8];
+  
+  /*
+   * CPM Timers Block
+   */
+  rtems_unsigned16      tgcr;
+  rtems_unsigned8       _pad42[14];
+  rtems_unsigned16      tmr1;
+  rtems_unsigned16      tmr2;
+  rtems_unsigned16      trr1;
+  rtems_unsigned16      trr2;
+  rtems_unsigned16      tcr1;
+  rtems_unsigned16      tcr2;
+  rtems_unsigned16      tcn1;
+  rtems_unsigned16      tcn2;
+  rtems_unsigned16      tmr3;
+  rtems_unsigned16      tmr4;
+  rtems_unsigned16      trr3;
+  rtems_unsigned16      trr4;
+  rtems_unsigned16      tcr3;
+  rtems_unsigned16      tcr4;
+  rtems_unsigned16      tcn3;
+  rtems_unsigned16      tcn4;
+  rtems_unsigned16      ter1;
+  rtems_unsigned16      ter2;
+  rtems_unsigned16      ter3;
+  rtems_unsigned16      ter4;
+  rtems_unsigned8       _pad43[8];
+
+  /*
+   * CPM Block
+   */
+  rtems_unsigned16      cpcr;
+  rtems_unsigned16      _pad44;
+  rtems_unsigned16      rccr;
+  rtems_unsigned8       _pad45;
+  rtems_unsigned8       rmds;
+  rtems_unsigned32      rmdr;
+  rtems_unsigned16      rctr1;
+  rtems_unsigned16      rctr2;
+  rtems_unsigned16      rctr3;
+  rtems_unsigned16      rctr4;
+  rtems_unsigned16      _pad46;
+  rtems_unsigned16      rter;
+  rtems_unsigned16      _pad47;
+  rtems_unsigned16      rtmr;
+  rtems_unsigned8       _pad48[0x9f0-0x9dc];
+  
+  /*
+   * BRG Block
+   */
+  rtems_unsigned32      brgc1;
+  rtems_unsigned32      brgc2;
+  rtems_unsigned32      brgc3;
+  rtems_unsigned32      brgc4;
+  
+  /*
+   * SCC Block
+   */
+  m8xxSCCRegisters_t    scc1;
+  m8xxSCCRegisters_t    scc2;
+#if defined(mpc860)
+  m8xxSCCRegisters_t    scc3;
+  m8xxSCCRegisters_t    scc4;
+#elif defined(mpc821)
+  rtems_unsigned8	_pad72[0xa80-0xa40];
+#endif
+
+  /*
+   * SMC Block
+   */
+  m8xxSMCRegisters_t    smc1;
+  m8xxSMCRegisters_t    smc2;
+  
+  /*
+   * SPI Block
+   */
+  rtems_unsigned16      spmode;
+  rtems_unsigned16      _pad49[2];
+  rtems_unsigned8       spie;
+  rtems_unsigned8       _pad50;
+  rtems_unsigned16      _pad51;
+  rtems_unsigned8       spim;
+  rtems_unsigned8       _pad52[2];
+  rtems_unsigned8       spcom;
+  rtems_unsigned16      _pad53[2];
+  
+  /*
+   * PIP Block
+   */
+  rtems_unsigned16      pipc;
+  rtems_unsigned16      _pad54;
+  rtems_unsigned16      ptpr;
+  rtems_unsigned32      pbdir;
+  rtems_unsigned32      pbpar;
+  rtems_unsigned16      _pad55;
+  rtems_unsigned16      pbodr;
+  rtems_unsigned32      pbdat;
+  rtems_unsigned32      _pad56[6];
+  
+  /*
+   * SI Block
+   */
+  rtems_unsigned32      simode;
+  rtems_unsigned8       sigmr;
+  rtems_unsigned8       _pad57;
+  rtems_unsigned8       sistr;
+  rtems_unsigned8       sicmr;
+  rtems_unsigned32      _pad58;
+  rtems_unsigned32      sicr;
+  rtems_unsigned16      sirp[2];
+  rtems_unsigned32      _pad59[3];
+  rtems_unsigned8       _pad60[0xc00-0xb00];
+  rtems_unsigned8       siram[512];
+#if defined(mpc860)
+  /*
+   * This is only used on the MPC8xxT - for the Fast Ethernet Controller (FEC)
+   */
+  m8xxFECRegisters_t    fec;
+#elif defined(mpc821)
+  rtems_unsigned8       lcdram[512];
+#endif
+  rtems_unsigned8       _pad62[0x2000-0x1000];
+  
+  /*
+   * Dual-port RAM
+   */
+  rtems_unsigned8       dpram0[0x200];  /* BD/DATA/UCODE */
+  rtems_unsigned8       dpram1[0x200];  /* BD/DATA/UCODE */
+  rtems_unsigned8       dpram2[0x400];  /* BD/DATA/UCODE */
+  rtems_unsigned8       dpram3[0x600];  /* BD/DATA*/
+  rtems_unsigned8       dpram4[0x200];  /* BD/DATA/UCODE */
+  rtems_unsigned8       _pad63[0x3c00-0x3000];
+  
+  /* When using SCC1 for ethernet, we lose the use of I2C since
+   *  their parameters would overlap. Motorola has a microcode
+   *  patch to move parameters around so that both can be used
+   *  together. It is available on their web site somewhere 
+   *  under http://www.mot.com/mpc8xx. If ethernet is used on
+   *  one (or more) of the other SCCs, then other CPM features
+   *  will be unavailable:
+   *    SCC2    -> lose SPI
+   *    SCC3    -> lose SMC1
+   *    SCC4    -> lose SMC2
+   *  However, Ethernet only works on SCC1 on the 8xx.
+   */
+  m8xxSCCENparms_t      scc1p;
+  rtems_unsigned8       _rsv1[0xCB0-0xC00-sizeof(m8xxSCCENparms_t)];
+  m8xxMiscParms_t       miscp;
+  rtems_unsigned8       _rsv2[0xcc0-0xCB0-sizeof(m8xxMiscParms_t)];
+  m8xxIDMAparms_t       idma1p;
+  rtems_unsigned8       _rsv3[0xd00-0xcc0-sizeof(m8xxIDMAparms_t)];
+  
+  m8xxSCCparms_t        scc2p;
+  rtems_unsigned8       _rsv4[0xD80-0xD00-sizeof(m8xxSCCparms_t)];
+  m8xxSPIparms_t        spip;
+  rtems_unsigned8       _rsv5[0xDB0-0xD80-sizeof(m8xxSPIparms_t)];
+  m8xxTimerParms_t      tmp;
+  rtems_unsigned8       _rsv6[0xDC0-0xDB0-sizeof(m8xxTimerParms_t)];
+  m8xxIDMAparms_t       idma2p;
+  rtems_unsigned8       _rsv7[0xE00-0xDC0-sizeof(m8xxIDMAparms_t)];
+  
+  m8xxSCCparms_t        scc3p; /* Not available on MPC821 */
+  rtems_unsigned8       _rsv8[0xE80-0xE00-sizeof(m8xxSCCparms_t)];
+  m8xxSMCparms_t        smc1p;
+  rtems_unsigned8       _rsv9[0xEC0-0xE80-sizeof(m8xxSMCparms_t)];
+  m8xxDSPparms_t        dsp1p;
+  rtems_unsigned8       _rsv10[0xF00-0xEC0-sizeof(m8xxDSPparms_t)];
+  
+  m8xxSCCparms_t        scc4p; /* Not available on MPC821 */
+  rtems_unsigned8       _rsv11[0xF80-0xF00-sizeof(m8xxSCCparms_t)];
+  m8xxSMCparms_t        smc2p;
+  rtems_unsigned8       _rsv12[0xFC0-0xF80-sizeof(m8xxSMCparms_t)];
+  m8xxDSPparms_t        dsp2p;
+  rtems_unsigned8       _rsv13[0x1000-0xFC0-sizeof(m8xxDSPparms_t)];
+} m8xx_t;
+
+extern volatile m8xx_t m8xx;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* ASM */
+
+#endif /* __MPC8xx_h */
Index: c/src/lib/libcpu/powerpc/mpc8xx/mmu/Makefile.am
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/mmu/Makefile.am	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
+++ c/src/lib/libcpu/powerpc/mpc8xx/mmu/Makefile.am	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
@@ -0,0 +1,30 @@
+## 
+## $Id$
+## 
+
+AUTOMAKE_OPTIONS = foreign 1.4
+
+PGM = ${ARCH}/mmu.rel
+
+## C sources
+C_FILES = mmu.c
+
+clock_rel_OBJECTS = $(C_FILES:%.c=${ARCH}/%.o)
+
+include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
+include $(top_srcdir)/../../../../../automake/lib.am
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+AM_CFLAGS = $(CFLAGS_OS_V)
+
+$(PGM): $(clock_rel_OBJECTS)
+	$(make-rel)
+
+all-local: ${ARCH} $(PGM)
+
+EXTRA_DIST = $(C_FILES)
+
+include $(top_srcdir)/../../../../../automake/local.am
Index: c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
+++ c/src/lib/libcpu/powerpc/mpc8xx/mmu/mmu.c	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
@@ -0,0 +1,120 @@
+/* 
+ * mmu.c
+ * 
+ * This file contains routines for initializing 
+ * and manipulating the MMU on the MPC8xx.
+ *
+ * Copyright (c) 1999, National Research Council of Canada
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.OARcorp.com/rtems/license.html.
+ */
+
+#include <bsp.h>
+#include <mpc8xx/mmu.h>
+
+/*
+ * mmu_init
+ *
+ * This routine sets up the virtual memory maps on an MPC8xx. 
+ * The MPC8xx does not support block address translation (BATs) 
+ * and does not have segment registers. Thus, we must set up page 
+ * translation. However, its MMU supports variable size pages
+ * (1-, 4-, 16-, 512-Kbyte or 8-Mbyte), which simplifies the task.
+ *
+ * The MPC8xx has separate data and instruction 32-entry translation 
+ * lookaside buffers (TLB). By mapping all of DRAM as one huge page, 
+ * we can preload the TLBs and not have to be concerned with taking 
+ * TLB miss exceptions.
+ *
+ * We set up the virtual memory map so that virtual address of a 
+ * location is equal to its real address.
+ */
+void mmu_init( void )
+{
+  register unsigned32 reg1, i;
+
+  /*
+   * Initialize the TLBs
+   *
+   * Instruction address translation and data address translation
+   * must be disabled during initialization (IR=0, DR=0 in MSR).
+   * We can assume the MSR has already been set this way.
+   */
+
+  /*	
+   * Initialize IMMU & DMMU Control Registers (MI_CTR & MD_CTR)
+   * 	GPM [0]			0b0 = PowerPC mode
+   *	PPM [1]			0b0 = Page resolution of protection
+   *	CIDEF [2]		0b0/0b1 = Default cache-inhibit attribute = 
+   *							NO for IMMU, YES for DMMU!
+   *	reserved/WTDEF [3]	0b0 = Default write-through attribute = not
+   *	RSV4x [4]		0b0 = 4 entries not reserved
+   *	reserved/TWAM [5]	0b0/0b1 = 4-Kbyte page hardware assist
+   *	PPCS [6]		0b0 = Ignore user/supervisor state
+   *	reserved [7-18]		0x00
+   *	xTLB_INDX [19-23]	31 = 0x1F
+   *	reserved [24-31]	0x00
+   *	
+   * Note: It is important that cache-inhibit be set as the default for the
+   * data cache when the DMMU is disabled in order to prevent internal memory
+   * mapped registers from being cached accidentally when address translation
+   * is turned off at the start of exception processing.
+   */
+  reg1 = M8xx_MI_CTR_ITLB_INDX(31);
+  _mtspr( M8xx_MI_CTR, reg1 );
+  reg1 = M8xx_MD_CTR_CIDEF | M8xx_MD_CTR_TWAM | M8xx_MD_CTR_DTLB_INDX(31);
+  _mtspr( M8xx_MD_CTR, reg1 );
+  _isync;
+  
+  /* 
+   * Invalidate all TLB entries in both TLBs.
+   * Note: We rely on the RSV4 bit in MI_CTR and MD_CTR being 0b0, so
+   *       all 32 entries are invalidated.
+   */
+  __asm__ volatile ("tlbia\n"::);
+  _isync;
+  
+  /*
+   * Set Current Address Space ID Register (M_CASID).
+   * Supervisor: CASID = 0
+   */
+  reg1 = 0;
+  _mtspr( M8xx_M_CASID, reg1 );
+
+  /* 
+   * Initialize the MMU Access Protection Registers (MI_AP, MD_AP)
+   * We ignore the Access Protection Group (APG) mechanism globally
+   * by setting all of the Mx_AP fields to 0b01 : client access
+   * permission is defined by page protection bits.
+   */
+  reg1 = 0x55555555;
+  _mtspr( M8xx_MI_AP, reg1 );
+  _mtspr( M8xx_MD_AP, reg1 );
+
+  /*  
+   * Load both 32-entry TLBs with values from the MMU_TLB_table
+   * which is defined in the BSP.
+   * Note the _TLB_Table must have at most 32 entries. This code 
+   * makes no effort to enforce this restriction.
+   */
+  for( i = 0; i < MMU_N_TLB_Table_Entries; ++i ) {
+    reg1 = MMU_TLB_table[i].mmu_epn;
+    _mtspr( M8xx_MI_EPN, reg1 );
+    _mtspr( M8xx_MD_EPN, reg1 );
+    reg1 = MMU_TLB_table[i].mmu_twc;
+    _mtspr( M8xx_MI_TWC, reg1 );
+    _mtspr( M8xx_MD_TWC, reg1 );
+    reg1 = MMU_TLB_table[i].mmu_rpn;	/* RPN must be written last! */
+    _mtspr( M8xx_MI_RPN, reg1 );
+    _mtspr( M8xx_MD_RPN, reg1 );
+  }
+
+  /* 
+   * Turn on address translation by setting MSR[IR] and MSR[DR].
+   */ 
+  _CPU_MSR_Value( reg1 );
+  reg1 |= PPC_MSR_IR | PPC_MSR_DR;
+  _CPU_MSR_SET( reg1 );
+}
Index: c/src/lib/libcpu/powerpc/mpc8xx/timer/Makefile.am
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/timer/Makefile.am	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
+++ c/src/lib/libcpu/powerpc/mpc8xx/timer/Makefile.am	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
@@ -0,0 +1,30 @@
+## 
+## $Id$
+## 
+
+AUTOMAKE_OPTIONS = foreign 1.4
+
+PGM = ${ARCH}/timer.rel
+
+## C sources
+C_FILES = timer.c
+
+timer_rel_OBJECTS = $(C_FILES:%.c=${ARCH}/%.o)
+
+include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
+include $(top_srcdir)/../../../../../automake/lib.am
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+AM_CFLAGS = $(CFLAGS_OS_V)
+
+$(PGM): $(timer_rel_OBJECTS)
+	$(make-rel)
+
+all-local: ${ARCH} $(PGM)
+
+EXTRA_DIST = $(C_FILES)
+
+include $(top_srcdir)/../../../../../automake/local.am
Index: c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
+++ c/src/lib/libcpu/powerpc/mpc8xx/timer/timer.c	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
@@ -0,0 +1,104 @@
+/*  timer.c
+ *
+ *  This file manages the interval timer on the PowerPC MPC8xx.
+ *  NOTE: This is not the PIT, but rather the RTEMS interval
+ *        timer
+ *  We shall use the bottom 32 bits of the timebase register,
+ *
+ *  The following was in the 403 version of this file. I don't
+ *  know what it means. JTM 5/19/98
+ *  NOTE: It is important that the timer start/stop overhead be
+ *        determined when porting or modifying this code.
+ *
+ *  Author: Jay Monkman (jmonkman@frasca.com)
+ *  Copywright (C) 1998 by Frasca International, Inc.
+ *
+ *  Derived from c/src/lib/libcpu/ppc/ppc403/timer/timer.c:
+ *
+ *  Author:     Andrew Bray <andy@i-cubed.co.uk>
+ *
+ *  COPYRIGHT (c) 1995 by i-cubed ltd.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of i-cubed limited not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      i-cubed limited makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Derived from c/src/lib/libcpu/hppa1_1/timer/timer.c:
+ *
+ *  COPYRIGHT (c) 1989-1998.
+ *  On-Line Applications Research Corporation (OAR).
+ *  Copyright assigned to U.S. Government, 1994.
+ *
+ *  The license and distribution terms for this file may be
+ *  found in the file LICENSE in this distribution or at
+ *  http://www.OARcorp.com/rtems/license.html.
+ *
+ *  $Id$
+ */
+
+#include <bsp.h>
+#include <rtems.h>
+#include <mpc8xx.h>
+
+extern rtems_cpu_table           Cpu_table;             /* owned by BSP */
+
+static volatile rtems_unsigned32 Timer_starting;
+static rtems_boolean Timer_driver_Find_average_overhead;
+
+/*
+ *  This is so small that this code will be reproduced where needed.
+ */
+static inline rtems_unsigned32 get_itimer(void)
+{
+   rtems_unsigned32 ret;
+
+   asm volatile ("mftb %0" : "=r" ((ret))); /* TBLO */
+
+   return ret;
+}
+
+void Timer_initialize(void)
+{
+  /* set interrupt level and enable timebase. This should never */
+  /*  generate an interrupt however. */
+  m8xx.tbscr |= M8xx_TBSCR_TBIRQ(4) | M8xx_TBSCR_TBE;
+  
+  Timer_starting = get_itimer();
+}
+
+int Read_timer(void)
+{
+  rtems_unsigned32 clicks;
+  rtems_unsigned32 total;
+
+  clicks = get_itimer();
+
+  total = clicks - Timer_starting;
+
+  if ( Timer_driver_Find_average_overhead == 1 )
+    return total;          /* in XXX microsecond units */
+
+  else {
+    if ( total < Cpu_table.timer_least_valid ) {
+      return 0;            /* below timer resolution */
+    }
+    return (total - Cpu_table.timer_average_overhead);
+  }
+}
+
+rtems_status_code Empty_function(void)
+{
+  return RTEMS_SUCCESSFUL;
+}
+
+void Set_find_average_overhead(rtems_boolean find_flag)
+{
+  Timer_driver_Find_average_overhead = find_flag;
+}
Index: c/src/lib/libcpu/powerpc/mpc8xx/vectors/Makefile.am
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/vectors/Makefile.am	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
+++ c/src/lib/libcpu/powerpc/mpc8xx/vectors/Makefile.am	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
@@ -0,0 +1,33 @@
+## 
+## $Id$
+## 
+
+AUTOMAKE_OPTIONS = foreign 1.4
+
+## FIXME
+VPATH = @srcdir@:@srcdir@/../../ppc403/vectors
+
+PGM = ${ARCH}/vectors.rel
+
+## Assembly sources
+S_FILES = vectors.S align_h.S
+
+vectors_rel_OBJECTS = $(S_FILES:%.S=${ARCH}/%.o)
+
+include $(RTEMS_ROOT)/make/custom/@RTEMS_BSP@.cfg
+include $(top_srcdir)/../../../../../automake/lib.am
+
+#
+# (OPTIONAL) Add local stuff here using +=
+#
+
+AM_CFLAGS = $(CFLAGS_OS_V)
+
+$(PGM): $(vectors_rel_OBJECTS)
+	$(make-rel)
+
+all-local: ${ARCH} $(PGM)
+
+EXTRA_DIST = vectors.S README
+
+include $(top_srcdir)/../../../../../automake/local.am
Index: c/src/lib/libcpu/powerpc/mpc8xx/vectors/README
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/vectors/README	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
+++ c/src/lib/libcpu/powerpc/mpc8xx/vectors/README	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
@@ -0,0 +1,23 @@
+#
+#  $Id$
+#
+
+The location of the vectors file object is critical.
+
+From the comments at the head of vectors.S:
+
+  The issue with this file is getting it loaded at the right place.
+  The first vector MUST be at address 0x????0100.
+  How this is achieved is dependant on the tool chain.
+
+...
+
+  The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the
+  offset from 0x????0000 to the first location in the file.  This
+  will be either 0x0000 or 0xfff0.
+
+The eth_comm BSP defines PPC_VECTOR_FILE_BASE to be 0x00000000.
+The MBX8xx BSP also defines PPC_VECTOR_FILE_BASE to be 0x00000000.
+Change these values to 0xFFF00000 if your are implementing an actual
+boot rom.
+
Index: c/src/lib/libcpu/powerpc/mpc8xx/vectors/align_h.S
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/vectors/align_h.S	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
+++ c/src/lib/libcpu/powerpc/mpc8xx/vectors/align_h.S	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
@@ -0,0 +1,430 @@
+/*  align_h.S	1.1 - 95/12/04
+ *
+ *  This file contains the assembly code for the MPC860
+ *  alignment exception handler for RTEMS.
+ *
+ *  Based upon IBM provided code for the PowerPC 403 with the following release:
+ *
+ *  This source code has been made available to you by IBM on an AS-IS
+ *  basis.  Anyone receiving this source is licensed under IBM
+ *  copyrights to use it in any way he or she deems fit, including
+ *  copying it, modifying it, compiling it, and redistributing it either
+ *  with or without modifications.  No license under IBM patents or
+ *  patent applications is to be implied by the copyright license.
+ *
+ *  Any user of this software should understand that IBM cannot provide
+ *  technical support for this software and will not be responsible for
+ *  any consequences resulting from the use of this software.
+ *
+ *  Any person who transfers this source code or any derivative work
+ *  must include the IBM copyright notice, this paragraph, and the
+ *  preceding two paragraphs in the transferred software.
+ *
+ *      COPYRIGHT   I B M   CORPORATION 1995
+ *      LICENSED MATERIAL  -  PROGRAM PROPERTY OF I B M
+ *
+ * Modifications:
+ *
+ *  Author:	Andrew Bray <andy@i-cubed.co.uk>
+ *
+ *  COPYRIGHT (c) 1995 by i-cubed ltd.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of i-cubed limited not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      i-cubed limited makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Additional modifications by Darlene Stewart (Darlene.Stewart@iit.nrc.ca):
+ *	Removed saving and restoring of PPC403-specific SRR2 and SRR3.
+ *	Access DAR instead of PPC403-specific DEAR.
+ *
+ *  $Id$
+ */
+
+#include "asm.h"
+#define ALIGN_REGS 0x0140
+
+.set    CACHE_SIZE,16           # cache line size of 32 bytes
+.set    CACHE_SIZE_L2,4         # cache line size, log 2
+
+.set	Open_gpr0,0
+.set	Open_gpr1,4
+.set	Open_gpr2,8
+.set	Open_gpr3,12
+.set	Open_gpr4,16
+.set	Open_gpr5,20
+.set	Open_gpr6,24
+.set	Open_gpr7,28
+.set	Open_gpr8,32
+.set	Open_gpr9,36
+.set	Open_gpr10,40
+.set	Open_gpr11,44
+.set	Open_gpr12,48
+.set	Open_gpr13,52
+.set	Open_gpr14,56
+.set	Open_gpr15,60
+.set	Open_gpr16,64
+.set	Open_gpr17,68
+.set	Open_gpr18,72
+.set	Open_gpr19,76
+.set	Open_gpr20,80
+.set	Open_gpr21,84
+.set	Open_gpr22,88
+.set	Open_gpr23,92
+.set	Open_gpr24,96
+.set	Open_gpr25,100
+.set	Open_gpr26,104
+.set	Open_gpr27,108
+.set	Open_gpr28,112
+.set	Open_gpr29,116
+.set	Open_gpr30,120
+.set	Open_gpr31,124
+.set	Open_xer,128
+.set	Open_lr,132
+.set	Open_ctr,136
+.set	Open_cr,140
+.set	Open_srr0,144
+.set	Open_srr1,148
+
+
+/*
+ *  This code makes several assumptions for processing efficiency
+ *  *  General purpose registers are continuous in the image, beginning with
+ *     Open_gpr0
+ *  *  Hash table is highly dependent on opcodes - opcode changes *will*
+ *     require rework of the instruction decode mechanism.
+ */
+
+        .text
+        .globl  align_h
+
+	.align	CACHE_SIZE_L2
+align_h:
+        /*-----------------------------------------------------------------------
+         * Store GPRs in Open Reg save area
+         * Set up r2 as base reg, r1 pointing to Open Reg save area
+         *----------------------------------------------------------------------*/
+        stmw    r0,ALIGN_REGS(r0)
+        li	r1,ALIGN_REGS
+        /*-----------------------------------------------------------------------
+         * Store special purpose registers in reg save area
+         *----------------------------------------------------------------------*/
+        mfxer   r7
+        mflr    r8
+        mfcr    r9
+        mfctr   r10
+        stw     r7,Open_xer(r1)
+        stw     r8,Open_lr(r1)
+        stw     r9,Open_cr(r1)
+        stw     r10,Open_ctr(r1)
+        mfspr	r9, srr0		/* SRR 0 */
+        mfspr	r10, srr1		/* SRR 1 */
+        stw     r9,Open_srr0(r1)
+        stw     r10,Open_srr1(r1)
+
+/*      Set up common registers */
+        mfspr	r5, dar			/* DAR: R5 is data (exception) address */
+        lwz     r9,Open_srr0(r1)        /* get faulting instruction */
+        addi    r7,r9,4                 /* bump instruction */
+        stw     r7,Open_srr0(r1)        /* restore to image */
+        lwz     r9, 0(r9)               /* retrieve actual instruction */
+        rlwinm  r6,r9,18,25,29          /* r6 is RA * 4 field from instruction */
+        rlwinm  r7,r9,6,26,31           /* r7 is primary opcode */
+        bl      ref_point               /* establish addressibility */
+ref_point:
+        mflr    r11                     /* r11 is the anchor point for ref_point */
+        addi    r10, r7, -31            /* r10 = r7 - 31 */
+        rlwinm  r10,r10,2,2,31          /* r10 *= 4 */
+        add     r10, r10, r11           /* r10 += anchor point */
+        lwz     r10, primary_jt-ref_point(r10)
+        mtlr    r10
+        rlwinm  r8,r9,13,25,29          /* r8 is RD * 4 */
+        la      r7,Open_gpr0(r1)        /* r7 is address of GPR 0 in list */
+        blr
+primary_jt:
+        .long   xform
+        .long   lwz
+        .long   lwzu
+        .long   0
+        .long   0
+        .long   stw
+        .long   stwu
+        .long   0
+        .long   0
+        .long   lhz
+        .long   lhzu
+        .long   lha
+        .long   lhau
+        .long   sth
+        .long   sthu
+        .long   lmw
+        .long   stmw
+/*
+ *   handlers
+ */
+/*
+ * xform instructions require an additional decode.  Fortunately, a relatively
+ * simple hash step breaks the instructions out with no collisions
+ */
+xform:
+        rlwinm  r7,r9,31,22,31          /* r7 is secondary opcode */
+        rlwinm  r10,r7,27,5,31          /* r10 = r7 >> 5 */
+        add     r10,r7,r10              /* r10 = r7 + r10 */
+        rlwinm  r10,r10,2,25,29         /* r10 = (r10 & 0x1F) * 4 */
+        add     r10,r10,r11             /* r10 += anchor point */
+        lwz     r10, secondary_ht-ref_point(r10)
+        mtlr    r10
+        la      r7,Open_gpr0(r1)        /* r7 is address of GPR 0 in list */
+        rlwinm  r8,r9,13,25,29          /* r8 is RD * 4 */
+        blrl
+
+secondary_ht:
+        .long   lhzux                   /* b 0  0x137 */
+        .long   lhax                    /* b 1  0x157 */
+        .long   lhaux                   /* b 2  0x177 */
+        .long   sthx                    /* b 3  0x197 */
+        .long   sthux                   /* b 4  0x1b7 */
+        .long   0                       /* b 5 */
+        .long   lwbrx                   /* b 6  0x216 */
+        .long   0                       /* b 7 */
+        .long   0                       /* b 8 */
+        .long   0                       /* b 9 */
+        .long   stwbrx                  /* b A  0x296 */
+        .long   0                       /* b B */
+        .long   0                       /* b C */
+        .long   0                       /* b D */
+        .long   lhbrx                   /* b E   0x316 */
+        .long   0                       /* b F */
+        .long   0                       /* b 10 */
+        .long   0                       /* b 11 */
+        .long   sthbrx                  /* b 12  0x396 */
+        .long   0                       /* b 13 */
+        .long   lwarx                   /* b 14  0x014 */
+        .long   dcbz                    /* b 15  0x3f6 */
+        .long   0                       /* b 16 */
+        .long   lwzx                    /* b 17  0x017 */
+        .long   lwzux                   /* b 18  0x037 */
+        .long   0                       /* b 19 */
+        .long   stwcx                   /* b 1A  0x096 */
+        .long   stwx                    /* b 1B  0x097 */
+        .long   stwux                   /* b 1C  0x0B7 */
+        .long   0                       /* b 1D */
+        .long   0                       /* b 1E */
+        .long   lhzx                    /* b 1F 0x117 */
+
+/*
+ * for all handlers
+ *       r4 - Addressability to interrupt context
+ *       r5 - DAR address (faulting data address)
+ *       r6 - RA field * 4
+ *       r7 - Address of GPR 0 in image
+ *       r8 - RD field * 4
+ *       r9 - Failing instruction
+ */
+
+/*       Load halfword algebraic with update */
+lhau:
+/*       Load halfword algebraic with update indexed */
+lhaux:
+        stwx    r5,r7,r6                /* update RA with effective addr */
+
+/*       Load halfword algebraic */
+lha:
+/*       Load halfword algebraic indexed */
+lhax:
+        lswi    r10,r5,2                /* load two bytes into r10 */
+        srawi   r10,r10,16              /* shift right 2 bytes, extending sign */
+        stwx    r10,r7,r8               /* update reg image */
+        b       align_complete          /* return */
+
+/*       Load Half Word Byte-Reversed Indexed */
+lhbrx:
+        lswi    r10,r5,2                /* load two bytes from DEAR into r10 */
+        rlwinm  r10,r10,0,0,15          /* mask off lower 2 bytes */
+        stwbrx  r10,r7,r8               /* store reversed in reg image */
+        b       align_complete          /* return */
+
+/*       Load Half Word and Zero with Update */
+lhzu:
+/*       Load Half Word and Zero with Update Indexed */
+lhzux:
+        stwx    r5,r7,r6                /* update RA with effective addr */
+
+/*       Load Half Word and Zero */
+lhz:
+/*       Load Half Word and Zero Indexed */
+lhzx:
+        lswi    r10,r5,2                /* load two bytes from DEAR into r10 */
+        rlwinm  r10,r10,16,16,31        /* shift right 2 bytes, with zero fill */
+        stwx    r10,r7,r8               /* update reg image */
+        b       align_complete          /* return */
+
+/*
+ *       Load Multiple Word
+ */
+lmw:
+        lwzx    r9,r6,r7                /* R9 contains saved value of RA */
+        addi    r10,r7,32*4             /* r10 points to r31 in image  + 4 */
+        rlwinm  r8,r8,30,2,31           /* r8 >>= 2  (recovers RT) */
+        subfic  r8,r8,32                /* r8 is reg count to load */
+        mtctr   r8                      /* load counter */
+        addi    r8,r8,-1                /* r8-- */
+        rlwinm  r8,r8,2,2,31            /* r8 *= 4 */
+        add     r5,r5,r8                /* update DEAR to point to last reg */
+lwmloop:
+        lswi    r11,r5,4                /* load r11 with 4 bytes from DEAR */
+        stwu    r11,-4(r10)             /* load image and decrement pointer */
+        addi    r5,r5,-4                /* decrement effective address */
+        bdnz    lwmloop
+        stwx    r9,r6,r7                /* restore RA (in case it was trashed) */
+        b       align_complete          /* return */
+
+/*
+ *       Load Word and Reserve Indexed
+ */
+lwarx:
+        lswi    r10,r5,4                /* load four bytes from DEAR into r10 */
+        stwx    r10,r7,r8               /* update reg image */
+        rlwinm  r5,r5,0,0,29            /* Word align address */
+        lwarx   r10,0,r5                /* Set reservation */
+        b       align_complete          /* return */
+
+/*
+ *       Load Word Byte-Reversed Indexed
+ */
+lwbrx:
+        lswi    r10,r5,4                /* load four bytes from DEAR into r10 */
+        stwbrx  r10,r7,r8               /* store reversed in reg image */
+        b       align_complete          /* return */
+
+/*       Load Word and Zero with Update */
+lwzu:
+/*       Load Word and Zero with Update Indexed */
+lwzux:
+        stwx    r5,r7,r6                /* update RA with effective addr */
+
+/*       Load Word and Zero */
+lwz:
+/*       Load Word and Zero Indexed */
+lwzx:
+        lswi    r10,r5,4                /* load four bytes from DEAR into r10 */
+        stwx    r10,r7,r8               /* update reg image */
+        b       align_complete          /* return */
+
+/*    Store instructions */
+
+/* */
+/*       Store Half Word and Update */
+sthu:
+/*       Store Half Word and Update Indexed */
+sthux:
+        stwx    r5,r7,r6                /* Update RA with effective address */
+
+/*       Store Half Word */
+sth:
+/*       Store Half Word Indexed */
+sthx:
+        lwzx    r10,r8,r7               /* retrieve source register value */
+        rlwinm  r10,r10,16,0,15         /* move two bytes to high end of reg */
+        stswi   r10,r5,2                /* store bytes to DEAR address */
+        b       align_complete          /* return */
+
+/* */
+/*       Store Half Word Byte-Reversed Indexed */
+sthbrx:
+        lwbrx   r10,r8,r7               /* retrieve src reg value byte reversed */
+        stswi   r10,r5,2                /* move two bytes to DEAR address */
+        b       align_complete          /* return */
+
+/* */
+/*       Store Multiple Word */
+stmw:
+        addi    r10,r7,32*4             /* r10 points to r31 in image  + 4 */
+        rlwinm  r8,r8,30,2,31           /* r8 >>= 2  (recovers RT) */
+        subfic  r8,r8,32                /* r8 is reg count to load */
+        mtctr   r8                      /* load counter */
+        addi    r8,r8,-1                /* r8-- */
+        rlwinm  r8,r8,2,2,31            /* r8 *= 4 */
+        add     r5,r5,r8                /* update DEAR to point to last reg */
+stmloop:
+        lwzu    r11,-4(r10)             /* get register value */
+        stswi   r11,r5,4                /* output to DEAR address */
+        addi    r5,r5,-4                /* decrement effective address */
+        bdnz    stmloop
+        b       align_complete          /* return */
+
+/* */
+/*       Store Word and Update */
+stwu:
+/*       Store Word and Update Indexed */
+stwux:
+        stwx    r5,r7,r6                /* Update RA with effective address */
+
+/*       Store Word */
+stw:
+/*       Store Word Indexed */
+stwx:
+        lwzx    r10,r8,r7               /* retrieve source register value */
+        stswi   r10,r5,4                /* store bytes to DEAR address */
+        b       align_complete          /* return */
+
+/* */
+/*       Store Word Byte-Reversed Indexed */
+stwbrx:
+        lwbrx   r10,r8,r7               /* retrieve src reg value byte reversed */
+        stswi   r10,r5,4                /* move two bytes to DEAR address */
+        b       align_complete          /* return */
+
+/* */
+/*       Store Word Conditional Indexed */
+stwcx:
+        rlwinm  r10,r5,0,0,29           /* r10 = word aligned DEAR */
+        lwz     r11,0(r10)              /* save original value of store */
+        stwcx.  r11,r0,r10              /* attempt store to address */
+        bne     stwcx_moveon            /* store failed, move on */
+        stw     r11,0(r10)              /* repair damage */
+        lwzx    r9,r7,r8                /* get register value */
+        stswi   r10,r5,4                /* store bytes to DEAR address */
+stwcx_moveon:
+        mfcr    r11                     /* get condition reg */
+        lwz     r9,Open_cr(r1)          /* get condition reg image */
+        rlwimi  r9,r11,0,0,2            /* insert 3 CR bits into cr image */
+        lwz     r11,Open_xer(r1)        /* get XER reg */
+        rlwimi  r9,r11,29,2,2           /* insert XER SO bit into cr image */
+        stw     r9,Open_cr(r1)          /* store cr image */
+        b       align_complete          /* return */
+
+/* */
+/*       Data Cache Block Zero */
+dcbz:
+        rlwinm  r5,r5,0,0,31-CACHE_SIZE_L2
+                                        /* get address to nearest Cache line */
+        addi    r5,r5,-4                /* adjust by a word */
+        addi    r10,r0,CACHE_SIZE/4     /* set counter value */
+        mtctr   r10
+        addi    r11,r0,0                /* r11 = 0 */
+dcbz_loop:
+        stwu    r11,4(r5)               /* store a word and update EA */
+        bdnz    dcbz_loop
+        b       align_complete          /* return */
+
+align_complete:
+        /*-----------------------------------------------------------------------
+         * Restore regs and return from the interrupt
+         *----------------------------------------------------------------------*/
+        lmw     r26,Open_xer+ALIGN_REGS(r0)
+        mtxer   r26
+        mtlr    r27
+        mtctr   r28
+        mtcrf   0xFF, r29
+        mtspr	srr0, r30		/* SRR 0 */
+        mtspr	srr1, r31		/* SRR 1 */
+        lmw     r1,Open_gpr1+ALIGN_REGS(r0)
+        lwz     r0,Open_gpr0+ALIGN_REGS(r0)
+        rfi
Index: c/src/lib/libcpu/powerpc/mpc8xx/vectors/vectors.S
===================================================================
--- c/src/lib/libcpu/powerpc/mpc8xx/vectors/vectors.S	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
+++ c/src/lib/libcpu/powerpc/mpc8xx/vectors/vectors.S	(revision 8ef38186faea3d9b5e6f0f1242f668cb7e7a3d52)
@@ -0,0 +1,1300 @@
+/*  vectors.S	1.1 - 95/12/04
+ *
+ *  This file contains the assembly code for the PowerPC MPC8xx
+ *  interrupt veneers for RTEMS.
+ * 
+ *  Author: Jay Monkman (jmonkman@frasca.com)
+ *
+ *  Copyright (C) 1998 by Frasca International, Inc.
+ *
+ *  Derived from c/src/lib/libcpu/ppc/ppc403/vectors/vectors.s:
+ *
+ *  Author:	Andrew Bray <andy@i-cubed.co.uk>
+ *
+ *  COPYRIGHT (c) 1995 by i-cubed ltd.
+ *
+ *  To anyone who acknowledges that this file is provided "AS IS"
+ *  without any express or implied warranty:
+ *      permission to use, copy, modify, and distribute this file
+ *      for any purpose is hereby granted without fee, provided that
+ *      the above copyright notice and this notice appears in all
+ *      copies, and that the name of i-cubed limited not be used in
+ *      advertising or publicity pertaining to distribution of the
+ *      software without specific, written prior permission.
+ *      i-cubed limited makes no representations about the suitability
+ *      of this software for any purpose.
+ *
+ *  Dwarf debugging info added by Darlene Stewart (Darlene.Stewart@iit.nrc.ca)
+ *  Also, made changes to turn address translation back on.
+ *
+ *  Modifications for to add DWARF debugging info, turn address translation on
+ *  and to coexist with EPPCBug:
+ *  Copyright (c) 1999, National Research Council of Canada
+ *
+ */
+
+/*
+ *  The issue with this file is getting it loaded at the right place.
+ *  The first vector MUST be at address 0x????0100.
+ *  How this is achieved is dependant on the tool chain.
+ *
+ *  However the basic mechanism for ELF assemblers is to create a
+ *  section called ".vectors", which will be loaded to an address
+ *  between 0x????0000 and 0x????0100 (inclusive) via a link script.
+ *
+ *  The basic mechanism for XCOFF assemblers is to place it in the
+ *  normal text section, and arrange for this file to be located
+ *  at an appropriate position on the linker command line.
+ *
+ *  The variable 'PPC_VECTOR_FILE_BASE' must be defined to be the
+ *  offset from 0x????0000 to the first location in the file.  This
+ *  will be either 0x0000 or 0xfff0.
+ *
+ *  If EPPCBUG_VECTORS is #defined, vectors 0x100 (system reset),
+ *  0x700 (program), 0xC00 (system call) and 0xD00 (trace) are set
+ *  up identically to the EPPCBug vectors in order to preserve the
+ *  firmware runtime environment.
+ *
+ *  THE FOUR ABOVE VECTORS MAY NEED TO BE MODIFIED TO MATCH YOUR
+ *  REVISION OF THE FIRMWARE.
+ *
+ *  Coexisting with the firmware only makes sense when the 
+ *  PPC_VECTOR_FILE_BASE is 0.
+ *
+ *  $Id$
+ */
+
+#include "asm.h"
+#include <mpc8xx.h>
+
+/* Location of your rtems source tree for source-level debugging purposes */
+#define PATH_PREFIX "/home/stewart"
+
+#ifndef PPC_VECTOR_FILE_BASE
+#error "PPC_VECTOR_FILE_BASE is not defined."
+#endif
+
+	/* Where this file will be loaded */
+	.set	file_base, PPC_VECTOR_FILE_BASE
+
+	/* Offset to store reg 0 */
+
+	.set	IP_LINK, 0
+#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
+	.set	IP_0, (IP_LINK + 56)
+#else
+	.set	IP_0, (IP_LINK + 8)
+#endif
+	.set	IP_2, (IP_0 + 4)
+
+	.set	IP_3, (IP_2 + 4)
+	.set	IP_4, (IP_3 + 4)
+	.set	IP_5, (IP_4 + 4)
+	.set	IP_6, (IP_5 + 4)
+	
+	.set	IP_7, (IP_6 + 4)
+	.set	IP_8, (IP_7 + 4)
+	.set	IP_9, (IP_8 + 4)
+	.set	IP_10, (IP_9 + 4)
+	
+	.set	IP_11, (IP_10 + 4)
+	.set	IP_12, (IP_11 + 4)
+	.set	IP_13, (IP_12 + 4)
+	.set	IP_28, (IP_13 + 4)
+	
+	.set	IP_29, (IP_28 + 4)
+	.set	IP_30, (IP_29 + 4)
+	.set	IP_31, (IP_30 + 4)
+	.set	IP_CR, (IP_31 + 4)
+	
+	.set	IP_CTR, (IP_CR + 4)
+	.set	IP_XER, (IP_CTR + 4)
+	.set	IP_LR, (IP_XER + 4)
+	.set	IP_PC, (IP_LR + 4)
+	
+	.set	IP_MSR, (IP_PC + 4)
+	
+	.set	IP_END, (IP_MSR + 16)
+
+	/* Vector offsets			 */
+	.set    begin_vector,     0x0000
+	.set    reset_vector,     0x0100
+	.set    mach_vector,      0x0200
+	.set    dsi_vector,       0x0300
+	.set    isi_vector,       0x0400
+	.set    ext_vector,       0x0500
+	.set    align_vector,     0x0600
+	.set    prog_vector,      0x0700
+	.set    float_vector,     0x0800
+	.set    dec_vector,       0x0900
+	.set    sys_vector,       0x0C00
+	.set    trace_vector,     0x0d00
+	.set	syscall_vector,   0x0c00
+	.set	fpassist_vector,  0x0e00
+	.set	software_vector,  0x1000
+	.set	itlbm_vector,     0x1100
+	.set	dtlbm_vector,     0x1200
+	.set	itlbe_vector,     0x1300
+	.set	dtlbe_vector,     0x1400
+	.set	databkpt_vector,  0x1c00
+	.set	insbkpt_vector,   0x1d00
+	.set	perbkpt_vector,   0x1e00
+	.set	dev_vector,       0x1f00
+	.set    siu_vector,       0x2000
+	.set    cpm_vector,       0x2400
+
+/* Go to the right section */
+#if PPC_ASM == PPC_ASM_XCOFF
+	.csect	.text[PR]
+#elif PPC_ASM == PPC_ASM_ELF
+	.section .vectors,"awx",@progbits
+.L_text_b:
+.L_LC1:
+	.previous
+
+.section	.debug_sfnames
+.L_sfnames_b:
+	.byte   PATH_PREFIX"rtems/c/src/lib/libcpu/powerpc/mpc8xx/vectors/"
+	.byte   0
+.L_F0:
+	.byte   "vectors.S"
+	.byte   0
+	.previous
+
+.section	.line
+.L_line_b:
+	.4byte	.L_line_e-.L_line_b
+	.4byte	.L_text_b
+.L_LE1:
+.L_line_last:
+	.4byte	0x0
+	.2byte	0xffff
+	.4byte	.L_text_e-.L_text_b
+.L_line_e:
+	.previous
+
+.section	.debug_srcinfo
+.L_srcinfo_b:
+	.4byte	.L_line_b
+	.4byte	.L_sfnames_b
+	.4byte	.L_text_b
+	.4byte	.L_text_e
+	.4byte	0xffffffff
+	.4byte	.L_LE1-.L_line_b
+	.4byte	.L_F0-.L_sfnames_b
+	.4byte	.L_line_last-.L_line_b
+	.4byte	0xffffffff
+	.previous
+
+.section	.debug_pubnames
+	.4byte	.L_debug_b
+	.4byte	.L_P0
+	.byte   "__vectors"
+	.byte   0
+	.4byte	0x0
+	.byte   0
+	.previous
+
+.section	.debug_aranges
+	.4byte	.L_debug_b
+	.4byte	.L_text_b
+	.4byte	.L_text_e-.L_text_b
+	.4byte	0
+	.4byte	0
+	.4byte	0
+	.4byte	0
+	.4byte	0
+	.4byte	0
+	.4byte	0x0
+	.4byte	0x0
+	.previous
+
+.section	.debug
+.L_debug_b:
+.L_D1:
+	.4byte	.L_D1_e-.L_D1
+	.2byte	0x11	/* TAG_compile_unit */
+	.2byte	0x12	/* AT_sibling */
+	.4byte	.L_D2
+	.2byte	0x38	/* AT_name */
+	.byte   "vectors.S"
+	.byte   0
+	.2byte	0x258	/* AT_producer */
+	.byte   "GAS 2.5.2"
+	.byte   0
+	.2byte	0x111	/* AT_low_pc */
+	.4byte	.L_text_b
+	.2byte	0x121	/* AT_high_pc */
+	.4byte	.L_text_e
+	.2byte	0x106	/* AT_stmt_list */
+	.4byte	.L_line_b
+	.2byte	0x1b8	/* AT_comp_dir */
+	.byte   PATH_PREFIX"rtems/c/src/lib/libcpu/powerpc/mpc8xx/vectors/"
+	.byte   0
+	.2byte	0x8006	/* AT_sf_names */
+	.4byte	.L_sfnames_b
+	.2byte	0x8016	/* AT_src_info */
+	.4byte	.L_srcinfo_b
+.L_D1_e:
+.L_P0:
+.L_D3:
+	.4byte	.L_D3_e-.L_D3
+	.2byte	0x6	/* TAG_global_subroutine */
+	.2byte	0x12	/* AT_sibling */
+	.4byte	.L_D4
+	.2byte	0x38	/* AT_name */
+	.byte   "__vectors"
+	.byte   0
+	.2byte	0x278	/* AT_prototyped */
+	.byte   0
+	.2byte	0x111	/* AT_low_pc */
+	.4byte	.L_text_b
+	.2byte	0x121	/* AT_high_pc */
+	.4byte	.L_text_e
+	.2byte	0x8041	/* AT_body_begin */
+	.4byte	.L_text_b
+	.2byte	0x8051	/* AT_body_end */
+	.4byte	.L_text_e
+.L_D3_e:
+
+.L_D4:
+	.4byte	.L_D4_e-.L_D4
+	.align  2
+.L_D4_e:
+.L_D2:
+	.previous
+	
+	.section .vectors
+#endif /* PPC_ASM_ELF */
+
+	PUBLIC_VAR (__vectors)
+SYM (__vectors):
+	
+
+/* 0x100 -- Critical error handling */
+	.org	reset_vector - file_base
+base_vectors:
+	
+#ifdef EPPCBUG_VECTORS
+	mtsprg  0, r1
+	mflr	r1
+	mtsprg  1, r1
+	bl	0xFE003EF8 	/* 0xFE004004 */
+#else
+#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
+#if (PPC_HAS_FPU)
+	stwu	r1, -(20*4 + 18*8 + IP_END)(r1)
+#else
+	stwu	r1, -(20*4 + IP_END)(r1)
+#endif /* PPC_HAS_FPU */
+#else
+	stwu	r1, -(IP_END)(r1)
+#endif /* PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27 */
+	stw	r0, IP_0(r1)
+
+	/* Turn address translation back on to re-enable the caches. */
+	mfmsr	r0
+	ori	r0, r0, 0x30
+	mtmsr	r0
+	
+	li      r0, PPC_IRQ_SYSTEM_RESET
+	b       PROC (_ISR_Handler)
+#endif /* EPPCBUG_VECTORS */
+
+
+/*  0x200 -- Machine check exception */
+	.org	mach_vector - file_base 
+#ifdef EPPCBUG_VECTORS
+	mtsprg  0, r1
+	mflr	r1
+	mtsprg  1, r1
+	bl	0xFE003DF8 	/* 0xFE004004 */
+#else
+#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
+#if (PPC_HAS_FPU)
+	stwu	r1, -(20*4 + 18*8 + IP_END)(r1)
+#else
+	stwu	r1, -(20*4 + IP_END)(r1)
+#endif
+#else
+	stwu	r1, -(IP_END)(r1)
+#endif
+	stw	r0, IP_0(r1)
+
+	/* Turn address translation back on to re-enable the caches. */
+	mfmsr	r0
+	ori	r0, r0, 0x30
+	mtmsr	r0
+	
+	li      r0, PPC_IRQ_MCHECK
+	b       PROC (_ISR_Handler)
+#endif /* EPPCBUG_VECTORS */
+
+	
+/*  0x300 -- Protection exception */
+	.org	dsi_vector - file_base
+#ifdef EPPCBUG_VECTORS
+	mtsprg  0, r1
+	mflr	r1
+	mtsprg  1, r1
+	bl	0xFE003CF8 	/* 0xFE004004 */
+#else
+#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
+#if (PPC_HAS_FPU)
+	stwu	r1, -(20*4 + 18*8 + IP_END)(r1)
+#else
+	stwu	r1, -(20*4 + IP_END)(r1)
+#endif
+#else
+	stwu	r1, -(IP_END)(r1)
+#endif
+	stw	r0, IP_0(r1)
+
+	/* Turn address translation back on to re-enable the caches. */
+	mfmsr	r0
+	ori	r0, r0, 0x30
+	mtmsr	r0
+	
+	li      r0, PPC_IRQ_PROTECT
+	b       PROC (_ISR_Handler)
+#endif /* EPPCBUG_VECTORS */
+
+
+/*  0x400 -- Instruction Storage exception */
+	.org	isi_vector - file_base
+#ifdef EPPCBUG_VECTORS
+	mtsprg  0, r1
+	mflr	r1
+	mtsprg  1, r1
+	bl	0xFE003BF8 	/* 0xFE004004 */
+#else
+#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
+#if (PPC_HAS_FPU)
+	stwu	r1, -(20*4 + 18*8 + IP_END)(r1)
+#else
+	stwu	r1, -(20*4 + IP_END)(r1)
+#endif
+#else
+	stwu	r1, -(IP_END)(r1)
+#endif
+	stw	r0, IP_0(r1)
+
+	/* Turn address translation back on to re-enable the caches. */
+	mfmsr	r0
+	ori	r0, r0, 0x30
+	mtmsr	r0
+
+	li      r0, PPC_IRQ_ISI
+	b       PROC (_ISR_Handler)
+#endif /* EPPCBUG_VECTORS */
+
+
+/*  0x500 -- External interrupt */
+/* When an external interrupt occurs, we must find out what caused it */
+/*  before calling the RTEMS handler. First we use SIVEC to decide    */
+/*  what signalled the interrupt to the SIU.                          */
+	.org	ext_vector - file_base
+#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
+#if (PPC_HAS_FPU)
+	stwu	r1, -(20*4 + 18*8 + IP_END)(r1)
+#else
+	stwu	r1, -(20*4 + IP_END)(r1)
+#endif
+#else
+	stwu	r1, -(IP_END)(r1)
+#endif
+	stw	r0, IP_0(r1)
+
+	/* Turn address translation back on to re-enable the caches. */
+	mfmsr	r0
+	ori	r0, r0, 0x30
+	mtmsr	r0
+	
+        stw     r9, IP_9(r1)  	/* r9 will be restored in the next level */
+        stw     r10, IP_10(r1)
+
+	lis  	r9, m8xx@ha
+        addi 	r9, r9, m8xx@l
+	lbz   	r10, 0x1c(r9)		/* SIVEC */
+        rlwinm	r10, r10, 4, 0, 27	/* each psuedo vector will have */
+        				/* room for 16 instructions */
+	addis	r10, r10, siu_vectors@ha
+	addi 	r10, r10, siu_vectors@l
+	mflr	r0
+	mtlr	r10
+	lwz 	r10, IP_10(r1)
+	blr
+
+
+/*  0x600 -- Align exception */
+	.org	align_vector - file_base
+	.extern	align_h
+	b	align_h
+	
+
+/*  0x700 -- Program exception */
+	.org	prog_vector - file_base
+#ifdef EPPCBUG_VECTORS
+	mtsprg  0, r1
+	mflr	r1
+	mtsprg  1, r1
+	bl	0xFE0038F8 	/* 0xFE004004 */
+#else
+#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
+#if (PPC_HAS_FPU)
+	stwu	r1, -(20*4 + 18*8 + IP_END)(r1)
+#else
+	stwu	r1, -(20*4 + IP_END)(r1)
+#endif
+#else
+	stwu	r1, -(IP_END)(r1)
+#endif
+	stw	r0, IP_0(r1)
+
+	/* Turn address translation back on to re-enable the caches. */
+	mfmsr	r0
+	ori	r0, r0, 0x30
+	mtmsr	r0
+
+	li      r0, PPC_IRQ_PROGRAM
+	b       PROC (_ISR_Handler)
+#endif /* EPPCBUG_VECTORS */
+
+
+/*  0x800 -- Float exception */
+	.org    float_vector - file_base
+#ifdef EPPCBUG_VECTORS
+	mtsprg  0, r1
+	mflr	r1
+	mtsprg  1, r1
+	bl	0xFE0037F8 	/* 0xFE004004 */
+#else
+#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
+#if (PPC_HAS_FPU)
+	stwu	r1, -(20*4 + 18*8 + IP_END)(r1)
+#else
+	stwu	r1, -(20*4 + IP_END)(r1)
+#endif
+#else
+	stwu	r1, -(IP_END)(r1)
+#endif
+	stw	r0, IP_0(r1)
+
+	/* Turn address translation back on to re-enable the caches. */
+	mfmsr	r0
+	ori	r0, r0, 0x30
+	mtmsr	r0
+
+	li      r0, PPC_IRQ_NOFP
+	b       PROC (_ISR_Handler)
+#endif /* EPPCBUG_VECTORS */
+
+
+/*  0x900 -- Decrementer exception */
+	.org	dec_vector - file_base
+#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
+#if (PPC_HAS_FPU)
+	stwu	r1, -(20*4 + 18*8 + IP_END)(r1)
+#else
+	stwu	r1, -(20*4 + IP_END)(r1)
+#endif
+#else
+	stwu	r1, -(IP_END)(r1)
+#endif
+	stw	r0, IP_0(r1)
+
+	/* Turn address translation back on to re-enable the caches. */
+	mfmsr	r0
+	ori	r0, r0, 0x30
+	mtmsr	r0
+
+	li      r0, PPC_IRQ_DECREMENTER
+	b       PROC (_ISR_Handler)
+
+
+/*  0xC00 -- System call */
+	.org	sys_vector - file_base
+#ifdef EPPCBUG_VECTORS
+	mtsprg  0, r1
+	mflr	r1
+	mtsprg  1, r1
+	bl	0xFE0033F8 	/* 0xFE004004 */
+#else
+#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
+#if (PPC_HAS_FPU)
+	stwu	r1, -(20*4 + 18*8 + IP_END)(r1)
+#else
+	stwu	r1, -(20*4 + IP_END)(r1)
+#endif
+#else
+	stwu	r1, -(IP_END)(r1)
+#endif
+	stw	r0, IP_0(r1)
+
+	/* Turn address translation back on to re-enable the caches. */
+	mfmsr	r0
+	ori	r0, r0, 0x30
+	mtmsr	r0
+
+	li      r0, PPC_IRQ_SCALL
+	b       PROC (_ISR_Handler)
+#endif /* EPPCBUG_VECTORS */
+
+
+/*  0xD00 -- Trace interrupt */
+	.org	trace_vector - file_base
+#ifdef EPPCBUG_VECTORS
+	mtsprg  0, r1
+	mflr	r1
+	mtsprg  1, r1
+	bl	0xFE0032F8 	/* 0xFE004004 */
+#else
+#if (PPC_ABI == PPC_ABI_POWEROPEN || PPC_ABI == PPC_ABI_GCC27)
+#if (PPC_HAS_FPU)
+	stwu	r1, -(20*4 + 18*8 + IP_END)(r1)
+#else
+	stwu	r1, -(20*4 + IP_END)(r1)
+#endif
+#else
+	stwu	r1, -(IP_END)(r1)
+#endif
+	stw	r0, IP_0(r1)
+
+	/* Turn address translation back on to re-enable the caches. */
+	mfmsr	r0
+	ori	r0, r0, 0x30
+	mtmsr	r0
+
+	li      r0, PPC_IRQ_TRACE
+	b       PROC (_ISR_Handler)
+#endif /* EPPCBUG_VECTORS */
+
+
+#ifdef EPPCBUG_VECTORS
+/*  0xE00 -- Floating Point Assist */
+	.org	fpassist_vector - file_base
+	mtsprg  0, r1
+	mflr	r1
+	mtsprg  1, r1
+	bl	0xFE0031F8 	/* 0xFE004004 */
+
+/*  0x1000 -- Software Emulation */
+	.org	software_vector - file_base
+software_vectors:
+	mtsprg  0, r1
+	mflr	r1
+	mtsprg  1, r1
+	bl	0xFE002FF8 	/* 0xFE004004 */
+#endif
+
+
+/*  0x1100 -- Intruction TLB Miss */
+	.org	itlbm_vector - file_base
+itlbm_vectors:
+#ifdef EPPCBUG_VECTORS
+	mtsprg  0, r1
+	mflr	r1
+	mtsprg  1, r1
+	bl	0xFE002EF8 	/* 0xFE004004 */
+#else
+	mfspr	r2, 784      /* MI_CTR */
+	mfspr	r3, 792      /* MD_CTR */
+	mfspr	r4, 787      /* MI_EPN */
+	mfspr	r5, 789      /* MI_TWC */
+	mfspr	r6, 797      /* MD_TWC */
+	mfspr	r7, 789      /* MI_TWC */
+	mfspr	r8, 790      /* MI_RPN */
+	mfspr	r9, 798      /* MD_RPN */
+	mfspr	r10, 796      /* M_TWB */
+	mfspr	r11, 793      /* M_CASID */
+	mfspr	r12, 786      /* MI_AP */
+	mfspr	r13, 794      /* MD_AP */
+	mfspr	r14, 799      /* M_TW */
+	mfspr	r15, 816      /* MI_CAM */
+	mfspr	r16, 817      /* MI_RAM0 */
+	mfspr	r17, 818      /* MI_RAM1 */
+	mfspr	r18, 824      /* MD_CAM */
+	mfspr	r19, 825      /* M_RAM0 */
+	mfspr	r20, 826      /* M_RAM1 */
+	.long   0
+#endif /* EPPCBUG_VECTORS */
+
+
+/*  0x1200 -- Data TLB Miss */
+	.org	dtlbm_vector - file_base
+dtlbm_vectors:
+#ifdef EPPCBUG_VECTORS
+	mtsprg  0, r1
+	mflr	r1
+	mtsprg  1, r1
+	bl	0xFE002DF8 	/* 0xFE004004 */
+#else
+	mfspr	r1, 0x1a
+	mfspr	r2, 784      /* MI_CTR */
+	mfspr	r3, 792      /* MD_CTR */
+	lis	r3, 0x400
+	mtspr	792, r3
+	mfspr	r4, 787      /* MI_EPN */
+	mfspr	r5, 789      /* MI_TWC */
+	mfspr	r6, 797      /* MD_TWC */
+	mfspr	r7, 789      /* MI_TWC */
+	mfspr	r8, 790      /* MI_RPN */
+	mfspr	r9, 798      /* MD_RPN */
+	mfspr	r10, 796      /* M_TWB */
+	mfspr	r11, 793      /* M_CASID */
+	mfspr	r12, 786      /* MI_AP */
+	mfspr	r13, 794      /* MD_AP */
+	mfspr	r14, 799      /* M_TW */
+	mfspr	r15, 816      /* MI_CAM */
+	mfspr	r16, 817      /* MI_RAM0 */
+	mfspr	r17, 818      /* MI_RAM1 */
+	mtspr	824, r18 
+	mfspr	r18, 824      /* MD_CAM */
+	mfspr	r19, 825      /* M_RAM0 */
+	mfspr	r20, 826      /* M_RAM1 */
+	.long   0
+#endif /* EPPCBUG_VECTORS */
+
+
+/*  0x1300 -- Instruction TLB Error */
+	.org	itlbe_vector - file_base
+itlbe_vectors:
+#ifdef EPPCBUG_VECTORS
+	mtsprg  0, r1
+	mflr	r1
+	mtsprg  1, r1
+	bl	0xFE002CF8 	/* 0xFE004004 */
+#else
+	mfspr	r2, 784      /* MI_CTR */
+	mfspr	r3, 792      /* MD_CTR */
+	mfspr	r4, 787      /* MI_EPN */
+	mfspr	r5, 789      /* MI_TWC */
+	mfspr	r6, 797      /* MD_TWC */
+	mfspr	r7, 789      /* MI_TWC */
+	mfspr	r8, 790      /* MI_RPN */
+	mfspr	r9, 798      /* MD_RPN */
+	mfspr	r10, 796      /* M_TWB */
+	mfspr	r11, 793      /* M_CASID */
+	mfspr	r12, 786      /* MI_AP */
+	mfspr	r13, 794      /* MD_AP */
+	mfspr	r14, 799      /* M_TW */
+	mfspr	r15, 816      /* MI_CAM */
+	mfspr	r16, 817      /* MI_RAM0 */
+	mfspr	r17, 818      /* MI_RAM1 */
+	mfspr	r18, 824      /* MD_CAM */
+	mfspr	r19, 825      /* M_RAM0 */
+	mfspr	r20, 826      /* M_RAM1 */
+	.long   0
+#endif /* EPPCBUG_VECTORS */
+
+
+/*  0x1400 -- Data TLB Error */
+	.org	dtlbe_vector - file_base
+dtlbe_vectors:
+#ifdef EPPCBUG_VECTORS
+	mtsprg  0, r1
+	mflr	r1
+	mtsprg  1, r1
+	bl	0xFE002BF8 	/* 0xFE004004 */
+#else
+	mfspr	r2, 784      /* MI_CTR */
+	mfspr	r3, 792      /* MD_CTR */
+	mfspr	r4, 787      /* MI_EPN */
+	mfspr	r5, 789      /* MI_TWC */
+	mfspr	r6, 797      /* MD_TWC */
+	mfspr	r7, 789      /* MI_TWC */
+	mfspr	r8, 790      /* MI_RPN */
+	mfspr	r9, 798      /* MD_RPN */
+	mfspr	r10, 796      /* M_TWB */
+	mfspr	r11, 793      /* M_CASID */
+	mfspr	r12, 786      /* MI_AP */
+	mfspr	r13, 794      /* MD_AP */
+	mfspr	r14, 799      /* M_TW */
+	mfspr	r15, 816      /* MI_CAM */
+	mfspr	r16, 817      /* MI_RAM0 */
+	mfspr	r17, 818      /* MI_RAM1 */
+	mfspr	r18, 824      /* MD_CAM */
+	mfspr	r19, 825      /* M_RAM0 */
+	mfspr	r20, 826      /* M_RAM1 */
+	.long   0
+#endif /* EPPCBUG_VECTORS */
+
+
+#ifdef EPPCBUG_VECTORS
+/*  0x1C00 -- Data Breakpoint */
+	.org	databkpt_vector - file_base
+databkpt_vectors:
+	mtsprg  0, r1
+	mflr	r1
+	mtsprg  1, r1
+	bl	0xFE0023F8 	/* 0xFE004004 */
+
+/*  0x1D00 -- Instruction Breakpoint */
+	.org	insbkpt_vector - file_base
+insbkpt_vectors:
+	mtsprg  0, r1
+	mflr	r1
+	mtsprg  1, r1
+	bl	0xFE0022F8 	/* 0xFE004004 */
+
+/*  0x1E00 -- Peripheral Breakpoint */
+	.org	perbkpt_vector - file_base
+perbkpt_vectors:
+	mtsprg  0, r1
+	mflr	r1
+	mtsprg  1, r1
+	bl	0xFE0021F8 	/* 0xFE004004 */
+
+/*  0x1F00 -- Non-Makable Development Port */
+	.org	dev_vector - file_base
+dev_vectors:
+	mtsprg  0, r1
+	mflr	r1
+	mtsprg  1, r1
+	bl	0xFE0020F8 	/* 0xFE004004 */
+#endif
+
+
+	
+/* Now we look at what signaled the interrupt to the SIU. */
+/*   I needed to do this in order to decode the CPM interrupts before  */
+/*    calling _ISR_Handler                                             */
+
+/* *IRQ0 */
+	.org    siu_vector - file_base
+siu_vectors:
+	mtlr  	r0
+	lwz 	r9, IP_9(r1)
+	li      r0, PPC_IRQ_IRQ0
+	b       PROC (_ISR_Handler)
+
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+/* Level 0 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li      r0, PPC_IRQ_LVL0
+	b       PROC (_ISR_Handler)
+
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+/* *IRQ1 */
+	mtlr  	r0
+	lwz	r9, IP_9(r1)
+	li      r0, PPC_IRQ_IRQ1
+	b       PROC (_ISR_Handler)
+
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+/* This is probably not the "correct" way to do this. I need to have a 
+ *  way of calling _ISR_Handler for the CPM interrupts and this is the
+ *  simplest way I can think of. Since I have the CPM interrupt mapped
+ *  to the SIU interrupt level 1 on the eth-comm board, I put it here.
+ *  It would probably be ok if I moved this directory to under libbsp
+ *  instead of libcpu. For now, deal with it.
+*/
+/* Level 1 - CPM */
+/* Now we need to get the CPM interrupt vector */
+	/* Registers:                                 */
+	/*   R0 - has stored value of LR 	      */
+	/*   R9 - pointer to m8xx struct 	      */
+	/*   R10 has already been saved and restored  */
+	li	r10, 1
+	sth	r10, 0x930(r9)	     /* CIVR */
+	lbz	r10, 0x930(r9)	     /* if we use this as an offset into a */
+	rlwinm	r10, r10, 1, 0, 31   /*  table, each entry will have room  */
+				     /*  4 instructions.                   */
+	addis	r10, r10, cpm_vectors@ha
+	addi	r10, r10, cpm_vectors@l
+
+	mtlr	r10
+	lwz	r10, IP_10(r1)
+	blr
+
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+#if 0
+/* Level 1 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li      r0, PPC_IRQ_LVL1
+	b       PROC (_ISR_Handler)
+
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+#endif
+
+/* *IRQ2 */
+	mtlr  	r0
+	lwz	r9, IP_9(r1)
+	li      r0, PPC_IRQ_IRQ2
+	b       PROC (_ISR_Handler)
+
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+/* Level 2 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li      r0, PPC_IRQ_LVL2
+	b       PROC (_ISR_Handler)
+
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+/* *IRQ3 */
+	mtlr  	r0
+	lwz	r9, IP_9(r1)
+	li      r0, PPC_IRQ_IRQ3
+	b       PROC (_ISR_Handler)
+
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+/* Level 3 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li      r0, PPC_IRQ_LVL3
+	b       PROC (_ISR_Handler)
+
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+/* *IRQ4 */
+	mtlr  	r0
+	lwz	r9, IP_9(r1)
+	li      r0, PPC_IRQ_IRQ4
+	b       PROC (_ISR_Handler)
+
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+/* Level 4 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li      r0, PPC_IRQ_LVL4
+	b       PROC (_ISR_Handler)
+
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+/* *IRQ5 */
+	mtlr  	r0
+	lwz	r9, IP_9(r1)
+	li      r0, PPC_IRQ_IRQ5
+	b       PROC (_ISR_Handler)
+
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+/* Level 5 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li      r0, PPC_IRQ_LVL5
+	b       PROC (_ISR_Handler)
+
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+/* *IRQ6 */
+	mtlr  	r0
+	lwz	r9, IP_9(r1)
+	li      r0, PPC_IRQ_IRQ6
+	b       PROC (_ISR_Handler)
+
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+/* Level 6 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li      r0, PPC_IRQ_LVL6
+	b       PROC (_ISR_Handler)
+
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+/* *IRQ7 */
+	mtlr  	r0
+	lwz	r9, IP_9(r1)
+	li      r0, PPC_IRQ_IRQ7
+	b       PROC (_ISR_Handler)
+
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+/* Level 7 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li      r0, PPC_IRQ_LVL7
+	b       PROC (_ISR_Handler)
+
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+	nop
+
+	
+/*	.org	cpm_vector - file_base*/
+cpm_vectors:		
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_ERROR
+	b	PROC (_ISR_Handler)
+
+	/* PC4 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_PC4
+	b	PROC (_ISR_Handler)
+
+	/* PC5 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_PC5
+	b	PROC (_ISR_Handler)
+
+	/* SMC2 / PIP */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_SMC2
+	b	PROC (_ISR_Handler)
+
+	/* SMC1 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_SMC1
+	b	PROC (_ISR_Handler)
+
+	/* SPI */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_SPI
+	b	PROC (_ISR_Handler)
+
+	/* PC6 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_PC6
+	b	PROC (_ISR_Handler)
+
+	/* Timer 4 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_TIMER4
+	b	PROC (_ISR_Handler)
+
+	/* Reserved - we should never see this */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_RESERVED_8
+        .long   0
+
+	/* PC7 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_PC7
+	b	PROC (_ISR_Handler)
+
+	/* PC8 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_PC8
+	b	PROC (_ISR_Handler)
+
+	/* PC9 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_PC9
+	b	PROC (_ISR_Handler)
+
+	/* Timer 3 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_TIMER3
+	b	PROC (_ISR_Handler)
+
+	/* Reserved - we should never get here */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_RESERVED_D
+        .long   0
+
+	/* PC10 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_PC10
+	b	PROC (_ISR_Handler)
+
+	/* PC11 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_PC11
+	b	PROC (_ISR_Handler)
+
+	/* I2C */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_I2C
+	b	PROC (_ISR_Handler)
+
+	/* RISC Timer Table */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_RISC_TIMER
+	b	PROC (_ISR_Handler)
+
+	/* Timer 2 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_TIMER2
+	b	PROC (_ISR_Handler)
+
+	/* Reserved - we should never get here */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_RESERVED_13
+        .long   0
+
+	/* IDMA2 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_IDMA2
+	b	PROC (_ISR_Handler)
+
+	/* IDMA1 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_IDMA1
+	b	PROC (_ISR_Handler)
+
+	/* SDMA Channel Bus Error */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_SDMA_ERROR
+	b	PROC (_ISR_Handler)
+
+	/* PC12 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_PC12
+	b	PROC (_ISR_Handler)
+
+	/* PC13 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_PC13
+	b	PROC (_ISR_Handler)
+
+	/* Timer 1 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_TIMER1
+	b	PROC (_ISR_Handler)
+
+	/* PC14 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_PC14
+	b	PROC (_ISR_Handler)
+
+	/* SCC4 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_SCC4
+	b	PROC (_ISR_Handler)
+
+	/* SCC3 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_SCC3
+	b	PROC (_ISR_Handler)
+
+	/* SCC2 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_SCC2
+	b	PROC (_ISR_Handler)
+
+	/* SCC1 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_SCC1
+	b	PROC (_ISR_Handler)
+
+	/* PC15 */
+	mtlr	r0
+	lwz	r9, IP_9(r1)
+	li	r0, PPC_IRQ_CPM_PC15
+	b	PROC (_ISR_Handler)
+
+.L_text_e:
+
+
