Changeset 8ef3818 in rtems


Ignore:
Timestamp:
Jun 12, 2000, 7:57:02 PM (20 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
41ab6966
Parents:
f481c39c
Message:

Patch from John Cotton <john.cotton@…>, Charles-Antoine Gauthier
<charles.gauthier@…>, and Darlene A. Stewart
<Darlene.Stewart@…> to add support for a number of very
significant things:

+ BSPs for many variations on the Motorola MBX8xx board series
+ Cache Manager including initial support for m68040

and PowerPC

+ Rework of mpc8xx libcpu code so all mpc8xx CPUs now use

same code base.

+ Rework of eth_comm BSP to utiltize above.

John reports this works on the 821 and 860

Files:
51 added
74 edited

Legend:

Unmodified
Added
Removed
  • aclocal/bsp-alias.m4

    rf481c39c r8ef3818  
    1515    p4600)        $2=p4000            ;; # mips64orion - p4000 board w/IDT 4600
    1616    p4650)        $2=p4000            ;; # mips64orion - p4000 board w/IDT 4650
     17    mbx8*)        $2=mbx8xx           ;; # MBX821/MBX860 board
    1718    pc486)        $2=pc386            ;; # i386 - PC with i486DX
    1819    pc586)        $2=pc386            ;; # i386 - PC with Pentium
  • aclocal/check-bsps.m4

    rf481c39c r8ef3818  
    2424        p4000)             rtems_bsp="$rtems_bsp p4600 p4650";;
    2525        mvme162)           rtems_bsp="$rtems_bsp mvme162 mvme162lx";;
     26        mbx8xx)            rtems_bsp="$rtems_bsp mbx821_001 mbx860_002";;
    2627        motorola_powerpc)  rtems_bsp="$rtems_bsp mvme2307 mcp750";;
    2728        pc386)             rtems_bsp="$rtems_bsp pc386 pc486 pc586 pc686";;
  • c/src/exec/libcsupport/include/sys/termios.h

    rf481c39c r8ef3818  
    182182int     tcgetattr(int, struct termios *);
    183183int     tcsetattr(int, int, struct termios *);
     184int     tcdrain(int);
    184185pid_t   tcgetprgrp(int);
    185186int     tcsetprgrp(int, pid_t);
  • c/src/exec/libcsupport/src/malloc.c

    rf481c39c r8ef3818  
    419419  free( ptr );
    420420}
    421 #endif
    422 
     421
     422
     423/*
     424 *  rtems_cache_aligned_malloc
     425 *
     426 *  DESCRIPTION:
     427 *
     428 *  This function is used to allocate storage that spans an
     429 *  integral number of cache blocks.
     430 */
     431RTEMS_INLINE_ROUTINE void * rtems_cache_aligned_malloc (
     432  size_t nbytes
     433)
     434{
     435  /*
     436   * Arrange to have the user storage start on the first cache
     437   * block beyond the header.
     438   */
     439  return (void *) ((((unsigned long) malloc( nbytes + _CPU_DATA_CACHE_ALIGNMENT - 1 ))
     440                                                                        + _CPU_DATA_CACHE_ALIGNMENT - 1 ) &(~(_CPU_DATA_CACHE_ALIGNMENT - 1)) );
     441}
     442
     443#endif
     444
  • c/src/exec/libcsupport/src/termios.c

    rf481c39c r8ef3818  
    2424#include <termios.h>
    2525#include <unistd.h>
     26#include <sys/filio.h>
    2627
    2728/*
     
    244245                 * Set default parameters
    245246                 */
    246                 tty->termios.c_iflag = BRKINT | ICRNL | IMAXBEL;
     247                tty->termios.c_iflag = BRKINT | ICRNL | IXON | IMAXBEL;
    247248                tty->termios.c_oflag = OPOST | ONLCR | XTABS;
    248249                tty->termios.c_cflag = B9600 | CS8 | CREAD | CLOCAL;
     
    474475        case RTEMS_IO_TCDRAIN:
    475476                drainOutput (tty);
     477                break;
     478
     479        case FIONREAD:
     480                /* Half guess that this is the right operation */
     481                *(int *)args->buffer = tty->ccount - tty->cindex;
    476482                break;
    477483        }
  • c/src/exec/posix/src/waitpid.c

    rf481c39c r8ef3818  
    11/*
    2  *  wait() - POSIX 1003.1b 3.2.1
     2 *  waitpid() - POSIX 1003.1 3.2.1
    33 *
    44 *  $Id$
  • c/src/exec/rtems/include/rtems/rtems/Makefile.am

    rf481c39c r8ef3818  
    99    taskmp.h
    1010
    11 STD_H_FILES = asr.h attr.h clock.h config.h dpmem.h event.h eventset.h \
    12     intr.h message.h modes.h options.h part.h ratemon.h region.h rtemsapi.h \
    13     sem.h signal.h status.h support.h tasks.h timer.h types.h
     11STD_H_FILES = asr.h attr.h cache.h clock.h config.h dpmem.h event.h eventset.h \
     12    intr.h message.h modes.h options.h part.h ratemon.h region.h rtemsapi.h sem.h \
     13    signal.h status.h support.h tasks.h timer.h types.h
    1414
    1515if HAS_MP
  • c/src/exec/rtems/src/Makefile.am

    rf481c39c r8ef3818  
    5151    dpmemident.c dpmeminternal2external.c
    5252
    53 STD_C_FILES = attr.c $(TASK_C_FILES) $(RATEMON_C_FILES) $(INTR_C_FILES) \
     53STD_C_FILES = attr.c cache.c $(TASK_C_FILES) $(RATEMON_C_FILES) $(INTR_C_FILES) \
    5454    $(CLOCK_C_FILES) $(TIMER_C_FILES) $(SEMAPHORE_C_FILES) \
    5555    $(MESSAGE_QUEUE_C_FILES) $(EVENT_C_FILES) $(SIGNAL_C_FILES) \
  • c/src/exec/score/cpu/i386/rtems/score/i386.h

    rf481c39c r8ef3818  
    145145
    146146
     147/*
     148 * Added for pagination management
     149 */
     150 
     151static inline unsigned int i386_get_cr0()
     152{
     153  register unsigned int segment = 0;
     154
     155  asm volatile ( "movl %%cr0,%0" : "=r" (segment) : "0" (segment) );
     156
     157  return segment;
     158}
     159
     160static inline void i386_set_cr0(unsigned int segment)
     161{
     162  asm volatile ( "movl %0,%%cr0" : "=r" (segment) : "0" (segment) );
     163}
     164
     165static inline unsigned int i386_get_cr2()
     166{
     167  register unsigned int segment = 0;
     168
     169  asm volatile ( "movl %%cr2,%0" : "=r" (segment) : "0" (segment) );
     170
     171  return segment;
     172}
     173
     174static inline unsigned int i386_get_cr3()
     175{
     176  register unsigned int segment = 0;
     177
     178  asm volatile ( "movl %%cr3,%0" : "=r" (segment) : "0" (segment) );
     179
     180  return segment;
     181}
     182
     183static inline void i386_set_cr3(unsigned int segment)
     184{
     185  asm volatile ( "movl %0,%%cr3" : "=r" (segment) : "0" (segment) );
     186}
     187
     188/*
     189 * Disable the entire cache
     190 */
     191void _CPU_disable_cache() {
     192  cr0 regCr0;
     193
     194  regCr0.i = i386_get_cr0();
     195  regCr0.cr0.page_level_cache_disable = 1;
     196  regCr0.cr0.no_write_through = 1;
     197  i386_set_cr0( regCr0.i );
     198  rtems_flush_entire_data_cache();
     199}
     200
     201/*
     202 * Enable the entire cache
     203 */
     204static inline void _CPU_enable_cache() {
     205  cr0 regCr0;
     206
     207  regCr0.i = i386_get_cr0();
     208  regCr0.cr0.page_level_cache_disable = 0;
     209  regCr0.cr0.no_write_through = 0;
     210  i386_set_cr0( regCr0.i );
     211  /*rtems_flush_entire_data_cache();*/
     212}
     213
     214/*
     215 * CACHE MANAGER: The following functions are CPU-specific.
     216 * They provide the basic implementation for the rtems_* cache
     217 * management routines. If a given function has no meaning for the CPU,
     218 * it does nothing by default.
     219 *
     220 * FIXME: Definitions for I386_CACHE_ALIGNMENT are missing above for
     221 *        each CPU. The routines below should be implemented per CPU,
     222 *        to accomodate the capabilities of each.
     223 */
     224
     225/* FIXME: I don't belong here. */
     226#define I386_CACHE_ALIGNMENT 16
     227
     228#if defined(I386_CACHE_ALIGNMENT)
     229#define _CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT
     230#define _CPU_INST_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT
     231
     232static inline void _CPU_flush_1_data_cache_line (const void * d_addr) {}
     233static inline void _CPU_invalidate_1_data_cache_line (const void * d_addr) {}
     234static inline void _CPU_freeze_data_cache (void) {}
     235static inline void _CPU_unfreeze_data_cache (void) {}
     236static inline void _CPU_invalidate_1_inst_cache_line const void * d_addr() {}
     237static inline void _CPU_freeze_inst_cache (void) {}
     238static inline void _CPU_unfreeze_inst_cache (void) {}
     239
     240static inline void _CPU_flush_entire_data_cache (
     241  const void * d_addr )
     242{
     243  asm ("wbinvd");
     244}
     245static inline void _CPU_invalidate_entire_data_cache (
     246  const void * d_addr )
     247{
     248  asm ("invd");
     249}
     250
     251static inline void _CPU_enable_data_cache (
     252        void )
     253{
     254        _CPU_enable_cache();
     255}
     256
     257static inline void _CPU_disable_data_cache (
     258        void )
     259{
     260        _CPU_disable_cache();
     261}
     262
     263static inline void _CPU_invalidate_entire_inst_cache (
     264  const void * i_addr )
     265{
     266  asm ("invd");
     267}
     268
     269static inline void _CPU_enable_inst_cache (
     270        void )
     271{
     272        _CPU_enable_cache();
     273}
     274
     275static inline void _CPU_disable_inst_cache (
     276        void )
     277{
     278        _CPU_disable_cache();
     279}
     280#endif
     281
     282
    147283/* routines */
    148284
  • c/src/exec/score/cpu/m68k/rtems/score/m68k.h

    rf481c39c r8ef3818  
    158158 
    159159#elif defined(__mc68302__)
     160
    160161#define CPU_MODEL_NAME          "m68302"
    161162#define M68K_HAS_VBR             0
     
    351352}
    352353
    353 /* XXX this is only valid for some m68k family members and should be fixed */
    354 
    355 #define m68k_enable_caching() \
    356   { register unsigned32 _ctl=0x01; \
    357     asm volatile ( "movec   %0,%%cacr" \
    358                        : "=d" (_ctl) : "0" (_ctl) ); \
    359   }
    360 
    361354#define CPU_swap_u32( value )  m68k_swap_u32( value )
    362355#define CPU_swap_u16( value )  m68k_swap_u16( value )
    363356
     357
     358/*
     359 *  _CPU_virtual_to_physical
     360 *
     361 *  DESCRIPTION:
     362 *
     363 *      This function is used to map virtual addresses to physical
     364 *      addresses.
     365 *
     366 *      FIXME: ASSUMES THAT VIRTUAL ADDRESSES ARE THE SAME AS THE
     367 *      PHYSICAL ADDRESSES
     368 */
     369static inline void * _CPU_virtual_to_physical (
     370  const void * d_addr )
     371{
     372  return (void *) d_addr;
     373}
     374
     375
     376/* 
     377 *  Since the cacr is common to all mc680x0, provide macros
     378 *  for masking values in that register.
     379 */
     380
     381/*
     382 *  Used to clear bits in the cacr.
     383 */
     384#define _CPU_CACR_AND(mask)                                        \
     385  {                                                                \
     386  register unsigned long _value = mask;                            \
     387  register unsigned long _ctl = 0;                                 \
     388  asm volatile ( "movec %%cacr, %0;           /* read the cacr */  \
     389                  andl %2, %0;                /* and with _val */  \
     390                  movec %1, %%cacr"           /* write the cacr */ \
     391   : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" );            \
     392  }
     393
     394
     395/* 
     396 *  Used to set bits in the cacr.
     397 */
     398#define _CPU_CACR_OR(mask)                                         \
     399        {                                                                \
     400  register unsigned long _value = mask;                            \
     401  register unsigned long _ctl = 0;                                 \
     402  asm volatile ( "movec %%cacr, %0;           /* read the cacr */  \
     403                  orl %2, %0;                 /* or with _val */   \
     404                  movec %1, %%cacr"           /* write the cacr */ \
     405   : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" );            \
     406  }
     407
     408   
     409/*
     410 * CACHE MANAGER: The following functions are CPU-specific.
     411 * They provide the basic implementation for the rtems_* cache
     412 * management routines. If a given function has no meaning for the CPU,
     413 * it does nothing by default.
     414 */
     415#if ( defined(__mc68020__) || defined(__mc68030__) )
     416#define M68K_INST_CACHE_ALIGNMENT 16
     417
     418#if defined(__mc68030__)
     419#define M68K_DATA_CACHE_ALIGNMENT 16
     420
     421/* Only the mc68030 has a data cache; it is writethrough only. */
     422
     423static inline void _CPU_flush_1_data_cache_line ( const void * d_addr ) {}
     424static inline void _CPU_flush_entire_data_cache ( const void * d_addr ) {}
     425
     426static inline void _CPU_invalidate_1_data_cache_line (
     427  const void * d_addr )
     428{
     429  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
     430  asm volatile ( "movec %0, %%caar" :: "a" (p_address) );      /* write caar */
     431  _CPU_CACR_OR(0x00000400);
     432}
     433
     434static inline void _CPU_invalidate_entire_data_cache (
     435        void )
     436{
     437  _CPU_CACR_OR( 0x00000800 );
     438}
     439
     440static inline void _CPU_freeze_data_cache (
     441        void )
     442{
     443  _CPU_CACR_OR( 0x00000200 );
     444}
     445
     446static inline void _CPU_unfreeze_data_cache (
     447        void )
     448{
     449  _CPU_CACR_AND( 0xFFFFFDFF );
     450}
     451
     452static inline void _CPU_enable_data_cache (     void )
     453{
     454  _CPU_CACR_OR( 0x00000100 );
     455}
     456static inline void _CPU_disable_data_cache (    void )
     457{
     458  _CPU_CACR_AND( 0xFFFFFEFF );
     459}
     460#endif
     461
     462
     463/* Both the 68020 and 68030 have instruction caches */
     464
     465static inline void _CPU_invalidate_1_inst_cache_line (
     466  const void * d_addr )
     467{
     468  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
     469  asm volatile ( "movec %0, %%caar" :: "a" (p_address) );      /* write caar */
     470  _CPU_CACR_OR( 0x00000004 );
     471}
     472
     473static inline void _CPU_invalidate_entire_inst_cache (
     474        void )
     475{
     476  _CPU_CACR_OR( 0x00000008 );
     477}
     478
     479static inline void _CPU_freeze_inst_cache (
     480        void )
     481{
     482  _CPU_CACR_OR( 0x00000002);
     483}
     484
     485static inline void _CPU_unfreeze_inst_cache (
     486        void )
     487{
     488  _CPU_CACR_AND( 0xFFFFFFFD );
     489}
     490
     491static inline void _CPU_enable_inst_cache (     void )
     492{
     493  _CPU_CACR_OR( 0x00000001 );
     494}
     495
     496static inline void _CPU_disable_inst_cache (    void )
     497{
     498  _CPU_CACR_AND( 0xFFFFFFFE );
     499}
     500
     501
     502#elif ( defined(__mc68040__) || defined (__mc68060__) )
     503
     504#define M68K_INST_CACHE_ALIGNMENT 16
     505#define M68K_DATA_CACHE_ALIGNMENT 16
     506
     507/* Cannot be frozen */
     508static inline void _CPU_freeze_data_cache ( void ) {}
     509static inline void _CPU_unfreeze_data_cache ( void ) {}
     510static inline void _CPU_freeze_inst_cache ( void ) {}
     511static inline void _CPU_unfreeze_inst_cache ( void ) {}
     512
     513static inline void _CPU_flush_1_data_cache_line (
     514  const void * d_addr )
     515{
     516  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
     517  asm volatile ( "cpushl %%dc,(%0)" :: "a" (p_address) );
     518}
     519
     520static inline void _CPU_invalidate_1_data_cache_line (
     521  const void * d_addr )
     522{
     523  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
     524  asm volatile ( "cinvl %%dc,(%0)" :: "a" (p_address) );
     525}
     526
     527static inline void _CPU_flush_entire_data_cache (
     528        void )
     529{
     530        asm volatile ( "cpusha %%dc" :: );
     531}
     532
     533static inline void _CPU_invalidate_entire_data_cache (
     534        void )
     535{
     536        asm volatile ( "cinva %%dc" :: );
     537}
     538
     539static inline void _CPU_enable_data_cache (
     540        void )
     541{
     542  _CPU_CACR_OR( 0x80000000 );
     543}
     544
     545static inline void _CPU_disable_data_cache (
     546        void )
     547{
     548  _CPU_CACR_AND( 0x7FFFFFFF );
     549}
     550
     551static inline void _CPU_invalidate_1_inst_cache_line (
     552  const void * i_addr )
     553{
     554  void * p_address = (void *)  _CPU_virtual_to_physical( i_addr );
     555  asm volatile ( "cinvl %%ic,(%0)" :: "a" (p_address) );
     556}
     557
     558static inline void _CPU_invalidate_entire_inst_cache (
     559        void )
     560{
     561                asm volatile ( "cinva %%ic" :: );
     562}
     563
     564static inline void _CPU_enable_inst_cache (
     565        void )
     566{
     567  _CPU_CACR_OR( 0x00008000 );
     568}
     569
     570static inline void _CPU_disable_inst_cache (
     571        void )
     572{
     573        _CPU_CACR_AND( 0xFFFF7FFF );
     574}
     575#endif
     576
     577
     578#if defined(M68K_DATA_CACHE_ALIGNMENT)
     579#define _CPU_DATA_CACHE_ALIGNMENT M68K_DATA_CACHE_ALIGNMENT
     580#endif
     581
     582#if defined(M68K_INST_CACHE_ALIGNMENT)
     583#define _CPU_INST_CACHE_ALIGNMENT M68K_INST_CACHE_ALIGNMENT
     584#endif
     585
     586
    364587#endif  /* !ASM */
    365588
     
    368591#endif
    369592
    370 #endif
     593#endif /* __M68K_h */
    371594/* end of include file */
  • c/src/exec/score/cpu/powerpc/asm.h

    rf481c39c r8ef3818  
    165165#define srr0    0x01a
    166166#define srr1    0x01b
     167#ifdef ppc403
    167168#define srr2    0x3de   /* IBM 400 series only */
    168169#define srr3    0x3df   /* IBM 400 series only */
     170#endif /* ppc403 */
     171
    169172#define sprg0   0x110
    170173#define sprg1   0x111
     
    172175#define sprg3   0x113
    173176
    174 
     177#define dar     0x013   /* Data Address Register */
     178#define dec             0x016   /* Decrementer Register */
     179
     180#if defined(ppc403)
    175181/* the following SPR/DCR registers exist only in IBM 400 series */
    176182#define dear    0x3d5   
     
    191197/* end of IBM400 series register definitions */
    192198
     199#elif defined(mpc860) || defined(mpc821)
    193200/* The following registers are for the MPC8x0 */
    194201#define der     0x095   /* Debug Enable Register */
     202#define ictrl   0x09E   /* Instruction Support Control Register */
     203#define immr    0x27E   /* Internal Memory Map Register */
    195204/* end of MPC8x0 registers */
     205#endif
    196206
    197207/*
  • c/src/exec/score/cpu/powerpc/old_exception_processing/Makefile.am

    rf481c39c r8ef3818  
    66
    77# C source names
    8 C_FILES = cpu.c ppccache.c
     8C_FILES = cpu.c
    99C_O_FILES = $(C_FILES:%.c=${ARCH}/%.o)
    1010
  • c/src/exec/score/cpu/powerpc/old_exception_processing/cpu.c

    rf481c39c r8ef3818  
    5151static void ppc_spurious(int, CPU_Interrupt_frame *);
    5252
     53int _CPU_spurious_count = 0;
     54int _CPU_last_spurious = 0;
     55
    5356void _CPU_Initialize(
    5457  rtems_cpu_table  *cpu_table,
     
    370373        }
    371374#endif
     375    ++_CPU_spurious_count;
     376    _CPU_last_spurious = v;
    372377}
    373378
     
    749754      Offset = 0x23c0;
    750755      break;
    751     case PPC_IRQ_CPM_RESERVED_0:
     756    case PPC_IRQ_CPM_ERROR:
    752757      Offset = 0x2400;
    753758      break;
  • c/src/exec/score/cpu/powerpc/old_exception_processing/cpu.h

    rf481c39c r8ef3818  
    767767  } while (0)
    768768
     769#define _CPU_Data_Cache_Block_Invalidate( _address ) \
     770  do { register void *__address = (_address); \
     771       register unsigned32 _zero = 0; \
     772       asm volatile ( "dcbi %0,%1" : \
     773                      "=r" (_zero), "=r" (__address) : \
     774                      "0" (_zero), "1" (__address) \
     775       ); \
     776  } while (0)
     777
    769778
    770779/*
  • c/src/exec/score/cpu/powerpc/rtems/score/ppc.h

    rf481c39c r8ef3818  
    4444extern "C" {
    4545#endif
     46
     47#include <rtems/score/ppctypes.h>
    4648
    4749/*
     
    221223/*
    222224 *  Added by Jay Monkman (jmonkman@frasca.com) 6/28/98
     225 *  with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca)
    223226 */
    224227#define CPU_MODEL_NAME  "PowerPC MPC860"
     
    232235#define PPC_HAS_DOUBLE          0
    233236#define PPC_USE_MULTIPLE        1
    234 #define PPC_USE_SPRG            1
    235237
    236238#define PPC_MSR_0               0x00009000
     
    382384#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
    383385#endif
     386
     387#ifndef ASM
     388
     389/*
     390 * CACHE MANAGER: The following functions are CPU-specific.
     391 * They provide the basic implementation for the rtems_* cache
     392 * management routines. If a given function has no meaning for the CPU,
     393 * it does nothing by default.
     394 *
     395 * FIXME: Some functions simply have not been implemented.
     396 */
     397 
     398#if defined(ppc603)                     /* And possibly others */
     399#define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
     400#define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
     401
     402/* Helpful macros */
     403#define PPC_Get_HID0( _value ) \
     404  do { \
     405      _value = 0;        /* to avoid warnings */ \
     406      asm volatile( \
     407          "mfspr %0, 0x3f0;"     /* get HID0 */ \
     408          "isync" \
     409          : "=r" (_value) \
     410          : "0" (_value) \
     411      ); \
     412  } while (0)
     413
     414#define PPC_Set_HID0( _value ) \
     415  do { \
     416      asm volatile( \
     417          "isync;" \
     418          "mtspr 0x3f0, %0;"     /* load HID0 */ \
     419          "isync" \
     420          : "=r" (_value) \
     421          : "0" (_value) \
     422      ); \
     423  } while (0)
     424
     425static inline void _CPU_enable_data_cache (
     426        void )
     427{
     428  unsigned32 value;
     429  PPC_Get_HID0( value );
     430  value |= 0x00004000;        /* set DCE bit */
     431  PPC_Set_HID0( value );
     432}
     433
     434static inline void _CPU_disable_data_cache (
     435        void )
     436{
     437  unsigned32 value;
     438  PPC_Get_HID0( value );
     439  value &= 0xFFFFBFFF;        /* clear DCE bit */
     440  PPC_Set_HID0( value );
     441}
     442
     443static inline void _CPU_enable_inst_cache (
     444        void )
     445{
     446  unsigned32 value;
     447  PPC_Get_HID0( value );
     448  value |= 0x00008000;       /* Set ICE bit */
     449  PPC_Set_HID0( value );
     450}
     451
     452static inline void _CPU_disable_inst_cache (
     453        void )
     454{
     455  unsigned32 value;
     456  PPC_Get_HID0( value );
     457  value &= 0xFFFF7FFF;       /* Clear ICE bit */
     458  PPC_Set_HID0( value );
     459}
     460
     461#elif ( defined(mpc860) || defined(mpc821) )
     462
     463#define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
     464#define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
     465
     466#define mtspr(_spr,_reg)   __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) )
     467#define isync   __asm__ volatile ("isync\n"::)
     468
     469static inline void _CPU_flush_1_data_cache_line(
     470        const void * _address )
     471{
     472  register const void *__address = _address;
     473  asm volatile ( "dcbf 0,%0" :: "r" (__address) );
     474}
     475
     476static inline void _CPU_invalidate_1_data_cache_line(
     477        const void * _address )
     478{
     479  register const void *__address = _address;
     480  asm volatile ( "dcbi 0,%0" :: "r" (__address) );
     481}
     482
     483static inline void _CPU_flush_entire_data_cache ( void ) {}
     484static inline void _CPU_invalidate_entire_data_cache ( void ) {}
     485static inline void _CPU_freeze_data_cache ( void ) {}
     486static inline void _CPU_unfreeze_data_cache ( void ) {}
     487
     488static inline void _CPU_enable_data_cache (
     489        void )
     490{
     491  unsigned32 r1;
     492  r1 = (0x2<<24);
     493  mtspr( 568, r1 );
     494  isync;
     495}
     496
     497static inline void _CPU_disable_data_cache (
     498        void )
     499{
     500  unsigned32 r1;
     501  r1 = (0x4<<24);
     502  mtspr( 568, r1 );
     503  isync;
     504}
     505
     506static inline void _CPU_invalidate_1_inst_cache_line(
     507        const void * _address )
     508{
     509  register const void *__address = _address;
     510  asm volatile ( "icbi 0,%0" :: "r" (__address) );
     511}
     512
     513static inline void _CPU_invalidate_entire_inst_cache ( void ) {}
     514static inline void _CPU_freeze_inst_cache ( void ) {}
     515static inline void _CPU_unfreeze_inst_cache ( void ) {}
     516
     517static inline void _CPU_enable_inst_cache (
     518        void )
     519{
     520  unsigned32 r1;
     521  r1 = (0x2<<24);
     522  mtspr( 560, r1 );
     523  isync;
     524}
     525
     526static inline void _CPU_disable_inst_cache (
     527        void )
     528{
     529  unsigned32 r1;
     530  r1 = (0x4<<24);
     531  mtspr( 560, r1 );
     532  isync;
     533}
     534#endif
     535
     536#endif  /* !ASM */
    384537
    385538/*
     
    551704#define PPC_IRQ_IRQ7            (PPC_STD_IRQ_LAST + 24)
    552705#define PPC_IRQ_LVL7            (PPC_STD_IRQ_LAST + 25)
    553 #define PPC_IRQ_CPM_RESERVED_0  (PPC_STD_IRQ_LAST + 26)
     706#define PPC_IRQ_CPM_ERROR       (PPC_STD_IRQ_LAST + 26)
    554707#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 27)
    555708#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 28)
  • c/src/exec/score/cpu/powerpc/shared/asm.h

    rf481c39c r8ef3818  
    165165#define srr0    0x01a
    166166#define srr1    0x01b
     167#ifdef ppc403
    167168#define srr2    0x3de   /* IBM 400 series only */
    168169#define srr3    0x3df   /* IBM 400 series only */
     170#endif /* ppc403 */
     171
    169172#define sprg0   0x110
    170173#define sprg1   0x111
     
    172175#define sprg3   0x113
    173176
    174 
     177#define dar     0x013   /* Data Address Register */
     178#define dec             0x016   /* Decrementer Register */
     179
     180#if defined(ppc403)
    175181/* the following SPR/DCR registers exist only in IBM 400 series */
    176182#define dear    0x3d5   
     
    191197/* end of IBM400 series register definitions */
    192198
     199#elif defined(mpc860) || defined(mpc821)
    193200/* The following registers are for the MPC8x0 */
    194201#define der     0x095   /* Debug Enable Register */
     202#define ictrl   0x09E   /* Instruction Support Control Register */
     203#define immr    0x27E   /* Internal Memory Map Register */
    195204/* end of MPC8x0 registers */
     205#endif
    196206
    197207/*
  • c/src/exec/score/cpu/powerpc/shared/ppc.h

    rf481c39c r8ef3818  
    4444extern "C" {
    4545#endif
     46
     47#include <rtems/score/ppctypes.h>
    4648
    4749/*
     
    221223/*
    222224 *  Added by Jay Monkman (jmonkman@frasca.com) 6/28/98
     225 *  with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca)
    223226 */
    224227#define CPU_MODEL_NAME  "PowerPC MPC860"
     
    232235#define PPC_HAS_DOUBLE          0
    233236#define PPC_USE_MULTIPLE        1
    234 #define PPC_USE_SPRG            1
    235237
    236238#define PPC_MSR_0               0x00009000
     
    382384#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
    383385#endif
     386
     387#ifndef ASM
     388
     389/*
     390 * CACHE MANAGER: The following functions are CPU-specific.
     391 * They provide the basic implementation for the rtems_* cache
     392 * management routines. If a given function has no meaning for the CPU,
     393 * it does nothing by default.
     394 *
     395 * FIXME: Some functions simply have not been implemented.
     396 */
     397 
     398#if defined(ppc603)                     /* And possibly others */
     399#define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
     400#define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
     401
     402/* Helpful macros */
     403#define PPC_Get_HID0( _value ) \
     404  do { \
     405      _value = 0;        /* to avoid warnings */ \
     406      asm volatile( \
     407          "mfspr %0, 0x3f0;"     /* get HID0 */ \
     408          "isync" \
     409          : "=r" (_value) \
     410          : "0" (_value) \
     411      ); \
     412  } while (0)
     413
     414#define PPC_Set_HID0( _value ) \
     415  do { \
     416      asm volatile( \
     417          "isync;" \
     418          "mtspr 0x3f0, %0;"     /* load HID0 */ \
     419          "isync" \
     420          : "=r" (_value) \
     421          : "0" (_value) \
     422      ); \
     423  } while (0)
     424
     425static inline void _CPU_enable_data_cache (
     426        void )
     427{
     428  unsigned32 value;
     429  PPC_Get_HID0( value );
     430  value |= 0x00004000;        /* set DCE bit */
     431  PPC_Set_HID0( value );
     432}
     433
     434static inline void _CPU_disable_data_cache (
     435        void )
     436{
     437  unsigned32 value;
     438  PPC_Get_HID0( value );
     439  value &= 0xFFFFBFFF;        /* clear DCE bit */
     440  PPC_Set_HID0( value );
     441}
     442
     443static inline void _CPU_enable_inst_cache (
     444        void )
     445{
     446  unsigned32 value;
     447  PPC_Get_HID0( value );
     448  value |= 0x00008000;       /* Set ICE bit */
     449  PPC_Set_HID0( value );
     450}
     451
     452static inline void _CPU_disable_inst_cache (
     453        void )
     454{
     455  unsigned32 value;
     456  PPC_Get_HID0( value );
     457  value &= 0xFFFF7FFF;       /* Clear ICE bit */
     458  PPC_Set_HID0( value );
     459}
     460
     461#elif ( defined(mpc860) || defined(mpc821) )
     462
     463#define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
     464#define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
     465
     466#define mtspr(_spr,_reg)   __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) )
     467#define isync   __asm__ volatile ("isync\n"::)
     468
     469static inline void _CPU_flush_1_data_cache_line(
     470        const void * _address )
     471{
     472  register const void *__address = _address;
     473  asm volatile ( "dcbf 0,%0" :: "r" (__address) );
     474}
     475
     476static inline void _CPU_invalidate_1_data_cache_line(
     477        const void * _address )
     478{
     479  register const void *__address = _address;
     480  asm volatile ( "dcbi 0,%0" :: "r" (__address) );
     481}
     482
     483static inline void _CPU_flush_entire_data_cache ( void ) {}
     484static inline void _CPU_invalidate_entire_data_cache ( void ) {}
     485static inline void _CPU_freeze_data_cache ( void ) {}
     486static inline void _CPU_unfreeze_data_cache ( void ) {}
     487
     488static inline void _CPU_enable_data_cache (
     489        void )
     490{
     491  unsigned32 r1;
     492  r1 = (0x2<<24);
     493  mtspr( 568, r1 );
     494  isync;
     495}
     496
     497static inline void _CPU_disable_data_cache (
     498        void )
     499{
     500  unsigned32 r1;
     501  r1 = (0x4<<24);
     502  mtspr( 568, r1 );
     503  isync;
     504}
     505
     506static inline void _CPU_invalidate_1_inst_cache_line(
     507        const void * _address )
     508{
     509  register const void *__address = _address;
     510  asm volatile ( "icbi 0,%0" :: "r" (__address) );
     511}
     512
     513static inline void _CPU_invalidate_entire_inst_cache ( void ) {}
     514static inline void _CPU_freeze_inst_cache ( void ) {}
     515static inline void _CPU_unfreeze_inst_cache ( void ) {}
     516
     517static inline void _CPU_enable_inst_cache (
     518        void )
     519{
     520  unsigned32 r1;
     521  r1 = (0x2<<24);
     522  mtspr( 560, r1 );
     523  isync;
     524}
     525
     526static inline void _CPU_disable_inst_cache (
     527        void )
     528{
     529  unsigned32 r1;
     530  r1 = (0x4<<24);
     531  mtspr( 560, r1 );
     532  isync;
     533}
     534#endif
     535
     536#endif  /* !ASM */
    384537
    385538/*
     
    551704#define PPC_IRQ_IRQ7            (PPC_STD_IRQ_LAST + 24)
    552705#define PPC_IRQ_LVL7            (PPC_STD_IRQ_LAST + 25)
    553 #define PPC_IRQ_CPM_RESERVED_0  (PPC_STD_IRQ_LAST + 26)
     706#define PPC_IRQ_CPM_ERROR       (PPC_STD_IRQ_LAST + 26)
    554707#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 27)
    555708#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 28)
  • c/src/exec/score/include/rtems/score/object.h

    rf481c39c r8ef3818  
    445445
    446446/*
     447 * _Objects_Get_by_index
     448 *
     449 *  DESCRIPTION:
     450 *
     451 * This routine sets the object pointer for the given
     452 * object id based on the given object information structure.
     453 */
     454
     455Objects_Control *_Objects_Get_by_index(
     456  Objects_Information *information,
     457  unsigned32           index,
     458  Objects_Locations   *location
     459);
     460
     461/*
    447462 *  _Objects_Get_next
    448463 *
     
    461476
    462477/*
     478 *  _Objects_Local_iterate
     479 *
     480 *  DESCRIPTION:
     481 *
     482 *  This function invokes the callback function for each existing object
     483 *  of the type specified by the information block pointer. Iteration
     484 *  continues until either all objects have been processed, or, if
     485 *  break_on_error is TRUE, until an invocation of the callback returns
     486 *  something other than 0.
     487 */
     488
     489unsigned32 _Objects_Local_iterate(
     490  Objects_Information *information,
     491  unsigned32 (*callback)(Objects_Control *object, void * arg),
     492  void * arg,
     493  boolean break_on_error
     494);
     495
     496/*
    463497 *  Pieces of object.inl are promoted out to the user
    464498 */
  • c/src/exec/score/include/rtems/score/thread.h

    rf481c39c r8ef3818  
    735735
    736736/*
     737 *  _Thread_Local_iterate
     738 *
     739 *  DESCRIPTION:
     740 *
     741 *  This function invokes the callback function for each existing thread.
     742 *  Iteration continues until either all threads have been processed, or,
     743 *  if break_on_error is TRUE, until an invocation of the callback returns
     744 *  an integer value other than 0.
     745 */
     746
     747unsigned32 _Thread_Local_iterate(
     748  unsigned32 (*callback)(Thread_Control *the_thread, void * arg),
     749  void * arg,
     750  boolean break_on_error
     751);
     752
     753/*
    737754 *  _Thread_Idle_body
    738755 *
  • c/src/exec/score/src/Makefile.am

    rf481c39c r8ef3818  
    2828    objectcopynameraw.c objectcopynamestring.c objectextendinformation.c \
    2929    objectfree.c objectget.c objectgetbyindex.c objectgetnext.c \
    30     objectinitializeinformation.c objectnametoid.c objectshrinkinformation.c
     30    objectinitializeinformation.c objectlocaliterate.c objectnametoid.c \
     31    objectshrinkinformation.c
    3132
    3233THREAD_C_FILES = thread.c threadchangepriority.c threadclearstate.c \
    3334    threadclose.c threadcreateidle.c threaddelayended.c threaddispatch.c \
    3435    threadevaluatemode.c threadget.c threadhandler.c threadidlebody.c \
    35     threadinitialize.c threadloadenv.c threadready.c threadresettimeslice.c \
    36     threadreset.c threadrestart.c threadresume.c threadrotatequeue.c \
    37     threadsetpriority.c threadsetstate.c threadsettransient.c \
    38     threadstackallocate.c threadstackfree.c threadstart.c \
    39     threadstartmultitasking.c threadsuspend.c threadtickletimeslice.c \
    40     threadyieldprocessor.c
     36    threadinitialize.c threadloadenv.c threadlocaliterate.c threadready.c \
     37    threadresettimeslice.c threadreset.c threadrestart.c threadresume.c \
     38    threadrotatequeue.c threadsetpriority.c threadsetstate.c \
     39    threadsettransient.c threadstackallocate.c threadstackfree.c \
     40    threadstart.c threadstartmultitasking.c threadsuspend.c \
     41    threadtickletimeslice.c threadyieldprocessor.c
    4142
    4243THREADQ_C_FILES = threadq.c threadqdequeue.c threadqdequeuefifo.c \
     
    5455
    5556STD_C_FILES = apiext.c chain.c $(CORE_MESSAGE_QUEUE_C_FILES) \
    56     $(CORE_MUTEX_C_FILES) $(CORE_SEMAPHORE_C_FILES) $(HEAP_C_FILES) interr.c \
    57     isr.c $(OBJECT_C_FILES) $(THREAD_C_FILES) $(THREADQ_C_FILES) \
     57    $(CORE_MUTEX_C_FILES) $(CORE_SEMAPHORE_C_FILES) $(HEAP_C_FILES) \
     58    interr.c isr.c $(OBJECT_C_FILES) $(THREAD_C_FILES) $(THREADQ_C_FILES) \
    5859    $(TOD_C_FILES) userext.c $(WATCHDOG_C_FILES) wkspace.c
    5960
  • c/src/lib/include/sys/termios.h

    rf481c39c r8ef3818  
    182182int     tcgetattr(int, struct termios *);
    183183int     tcsetattr(int, int, struct termios *);
     184int     tcdrain(int);
    184185pid_t   tcgetprgrp(int);
    185186int     tcsetprgrp(int, pid_t);
  • c/src/lib/libbsp/m68k/gen68360/startup/bspstart.c

    rf481c39c r8ef3818  
    3232
    3333char *rtems_progname;
     34
     35/* Amount of RAM on this board. Dynamically set in start.S */
     36unsigned long _M68K_RamSize;
    3437
    3538/*
  • c/src/lib/libbsp/m68k/mvme167/README

    rf481c39c r8ef3818  
    99Charles-Antoine Gauthier
    1010charles.gauthier@nrc.ca
     11
    1112or
    1213
    1314Darlene Stewart
    1415Darlene.Stewart@nrc.ca
    15 
     16 
    1617Software Engineering Group
    1718Institute for Information Technology
     
    2021Canada
    2122
    22 
    23 WARNING:
    24 --------
    25 
    26 The network driver is currently being worked on. It is somewhat functional,
    27 but it does run out of buffers under certain conditions. The code is
    28 also undergoing a substantial reorganization. Before making any changes,
    29 you should check with us for the availability of updates.
    30 
    31 Note from Joel:  The ttcp performance reported is very nice even if the
    32 driver is still early in its life. :)
    33 
    34  
    3523
    3624Disclaimer
     
    6856Port Description
    6957Console driver
    70 
    7158---------------
    7259
     
    148135
    149136
     137Configuration Parameters
     138
     139If Jumper J1-4 is installed, certain configuration parameters may be read from
     140the first 31 bytes of User Area NVRAM starting at 0xFFFC0000. In this case, the
     141user is responsible for writing the appropriate values to this memory location
     142(via 167Bug) in order to alter the default behaviour. A zero value results in
     143the default behaviour. The paramaters that are configurable and their default
     144settings are described below.
     145
     146        Data Cache Enable (0xFFFC0000 - 1 byte)
     147                write a non-zero value to this location to enable the data cache
     148                default: disabled
     149       
     150        Instruction Cache Activation (0xFFFC0001 - 1 byte)
     151                write a non-zero value to this location to enable the instruction cache
     152                default: disabled
     153               
     154        Cache Mode (0xFFFC0002 - 2 bytes)
     155                0xFFF0 = cachable, write-through
     156                0xFFF1 = cachable, copyback
     157                0xFFF2 = noncachable, serialized
     158                0xFFF3 = noncachable,
     159                default: cachable, copyback
     160
     161        IP Address (0xFFFC0004 - 4 bytes)
     162                write the hexidecimal representation of the board's IP address in this
     163                location for example, 192.168.1.2 = 0xC0A80102
     164                default: obtain the IP address from an rtems_bsdnet_ifconfig structure
     165
     166        Netmask (0xFFFC0008 - 4 bytes)
     167                write the hexidecimal representation of the netmask in this location
     168                for example, 255.255.255.0 = 0xFFFFFF00
     169                default: obtain the netmask from an rtems_bsdnet_ifconfig structure
     170               
     171        Ethernet Address (0xFFFC000C - 6 bytes)
     172                write the board's hardware address in this location
     173                default: obtain the hardware address from an rtems_bsdnet_ifconfig structure
     174
     175        Processor ID (0xFFFC0012 - 2 bytes)
     176                reserved for future use
     177               
     178        RMA start (0xFFFC0014 - 4 bytes)
     179                reserved for future use
     180               
     181        VMA start (0xFFFC0018 - 4 bytes)
     182                reserved for future use
     183               
     184        RamSize (0xFFFC001C - 4 bytes)
     185                reserved for future use
     186
     187
    150188Cache Control and Memory Mapping
     189
     190If configuration is not obtained from non-volatile RAM (ie. J1-4 is off),
     191cache control is done through the remaining J1 jumpers as follows:
    151192
    152193If Jumper J1-7 is installed, the data cache will be turned on. If Jumper
     
    501542    rtems_rate_monotonic_period: obtain status 13
    502543
    503 
  • c/src/lib/libbsp/m68k/mvme167/bsp_specs

    rf481c39c r8ef3818  
    1111%{!qrtems: %(old_lib)} %{qrtems: --start-group \
    1212%{!qrtems_debug: -lrtemsall} %{qrtems_debug: -lrtemsall_g} \
    13 %{qjava: -lffi -lzgcj -lgcj} %{qc++: -lstdc++} -lc -lgcc --end-group \
     13%{qjava: -lffi -lgcjgc -lzgcj -lgcj} %{qc++: -lstdc++} -lc -lgcc --end-group \
    1414%{!qnolinkcmds: -T linkcmds%s}}
    1515
  • c/src/lib/libbsp/m68k/mvme167/include/bsp.h

    rf481c39c r8ef3818  
    423423 */
    424424typedef volatile struct i82596_regs_ {
    425   unsigned short        port_lower;                               /* 0xFFF46000 */
    426   unsigned short        port_upper;                     /* 0xFFF46002 */
    427   unsigned long         chan_attn;                                /* 0xFFF46004 */
     425  unsigned short        port_lower;             /* 0xFFF46000 */
     426  unsigned short        port_upper;             /* 0xFFF46002 */
     427  unsigned long         chan_attn;              /* 0xFFF46004 */
    428428} i82596_regs;
    429429
     
    433433#define i82596    ((i82596_regs * const) 0xFFF46000)
    434434
     435/*
     436 *  Representation of initialization data in NVRAM
     437 */
     438typedef volatile struct nvram_config_ {
     439  unsigned char  dcache_enable;                         /* 0xFFFC0000 */
     440  unsigned char  icache_enable;                         /* 0xFFFC0001 */
     441  unsigned short cache_mode;                            /* 0xFFFC0002 */
     442  unsigned long  ipaddr;                                        /* 0xFFFC0004 */
     443  unsigned long  netmask;                                       /* 0xFFFC0008 */
     444  unsigned char  enaddr[6];                                     /* 0xFFFC000C */
     445  unsigned short processor_id;                          /* 0xFFFC0012 */
     446  unsigned long  rma_start;                                     /* 0xFFFC0014 */
     447  unsigned long  vma_start;                                     /* 0xFFFC0018 */
     448  unsigned long  ramsize;                                       /* 0xFFFC001C */
     449} nvram_config;
     450
     451/*
     452 *  Pointer to the base of User Area NVRAM
     453 */
     454#define nvram                   ((nvram_config * const) 0xFFFC0000)
    435455
    436456
  • c/src/lib/libbsp/m68k/mvme167/network/network.c

    rf481c39c r8ef3818  
    4141#define UTI_596_ETH_MIN_SIZE  60
    4242
     43#define INET_ADDR_MAX_BUF_SIZE (sizeof "255.255.255.255")
     44
    4345/*
    4446 * RTEMS events
     
    5860#include <sys/socket.h>
    5961#include <sys/sockio.h>
     62#include <sys/types.h>
    6063#include <net/if.h>
    6164#include <netinet/in.h>
    6265#include <netinet/if_ether.h>
     66#include <arpa/inet.h>
    6367
    6468#include "uti596.h"
     
    8084
    8185/* Types of waiting for commands */
    82 #define UTI596_NO_WAIT                                  0
    83 #define UTI596_WAIT_FOR_CU_ACCEPT               1
    84 #define UTI596_WAIT_FOR_INITIALIZATION  2
    85 #define UTI596_WAIT_FOR_STAT_C                  3
     86#define UTI596_NO_WAIT                                                                  0
     87#define UTI596_WAIT_FOR_CU_ACCEPT                               1
     88#define UTI596_WAIT_FOR_INITIALIZATION  2
     89#define UTI596_WAIT_FOR_STAT_C                                  3
    8690
    8791/* Device dependent data structure */
     
    418422 *    sc - pointer to the uti596_softc struct
    419423 *    wait_type - UTI596_NO_WAIT
     424 *                                              UTI596_WAIT
    420425 *                UTI596_WAIT_FOR_CU_ACCEPT
    421426 *                UTI596_WAIT_FOR_INITIALIZATION
     
    433438{
    434439  rtems_interval ticks_per_second, start_ticks, end_ticks;
     440
     441  rtems_clock_get(RTEMS_CLOCK_GET_TICKS_PER_SECOND, &ticks_per_second);
     442        rtems_clock_get(RTEMS_CLOCK_GET_TICKS_SINCE_BOOT, &start_ticks);
     443        end_ticks = start_ticks + ticks_per_second;
     444
     445  switch( waitType ) {
    435446 
    436   switch( waitType ) {
    437447    case UTI596_NO_WAIT:
    438448      return 0;
    439449
     450
    440451    case UTI596_WAIT_FOR_CU_ACCEPT:
    441       rtems_clock_get(RTEMS_CLOCK_GET_TICKS_PER_SECOND, &ticks_per_second);
    442                   rtems_clock_get(RTEMS_CLOCK_GET_TICKS_SINCE_BOOT, &start_ticks);
    443                   end_ticks = start_ticks + ticks_per_second;
    444 
    445452                  do {
    446453                          if (sc->scb.command == 0)
     
    460467 
    461468    case UTI596_WAIT_FOR_INITIALIZATION:
    462       rtems_clock_get(RTEMS_CLOCK_GET_TICKS_PER_SECOND, &ticks_per_second);
    463                   rtems_clock_get(RTEMS_CLOCK_GET_TICKS_SINCE_BOOT, &start_ticks);
    464                   end_ticks = start_ticks + ticks_per_second;
    465 
    466469                  do {
    467470                    if( !sc->iscp.busy )
     
    485488
    486489         case UTI596_WAIT_FOR_STAT_C:
    487            rtems_clock_get(RTEMS_CLOCK_GET_TICKS_PER_SECOND, &ticks_per_second);
    488                  rtems_clock_get(RTEMS_CLOCK_GET_TICKS_SINCE_BOOT, &start_ticks);
    489                  end_ticks = start_ticks + ticks_per_second;
    490 
    491490                 do {
    492491                   if( *sc->pCurrent_command_status & STAT_C )
     
    15511550  } while( m != NULL && ++bd_count < 16 );
    15521551
    1553   /* This should never happen */
    1554   if ( bd_count == 16 ) {
    1555     printk(("TX ERROR:Too many mbufs in the packet!!!\n"))
    1556     printk(("Must coalesce!\n"))
    1557   }
    1558 
    15591552  if ( length < UTI_596_ETH_MIN_SIZE ) {
    15601553    pTbd->data = (char *) word_swap ((unsigned long) sc->zeroes); /* add padding to pTbd */
     
    16621655  uti596_softc_ *sc = &uti596_softc;                            /* device dependent data structure */
    16631656  struct ifnet * ifp = &sc->arpcom.ac_if;   /* ifnet structure */
    1664 
    1665         int unitNumber;
    1666         char *unitName;
     1657        int unitNumber;
     1658        char *unitName;
     1659        char *pAddr;
     1660        int addr;
    16671661
    16681662        #ifdef DBG_ATTACH
     
    16901684    ifp->if_mtu = ETHERMTU;
    16911685
    1692   /* Ethernet address can be specified in the ifconfig structure or
    1693    * it can be read in from BBRAM at $FFFC1F2C (6 bytes)
    1694    * mvme167 manual p. 1-47
     1686  /*
     1687   * If an IP address and netmask are provided in NVRAM, cheat,
     1688   * and stuff them into the ifconfig structure, overriding any
     1689   * existing or NULL values.
     1690   *
     1691   * Warning: If values are provided in NVRAM, the ifconfig entries
     1692   * should be NULL because buffer memory allocated to hold the
     1693   * structure values is unrecoverable and would be lost here.
    16951694   */
    1696   if ( pConfig->hardware_address) {
     1695  if ( addr = nvram->ipaddr ) {
     1696        if ( pAddr = malloc ( INET_ADDR_MAX_BUF_SIZE, 0, M_NOWAIT ) )
     1697                        pConfig->ip_address = inet_ntop(AF_INET, &addr, pAddr, INET_ADDR_MAX_BUF_SIZE -1 );
     1698                else
     1699                        rtems_panic("Can't allocate ip_address buffer!\n");
     1700  }
     1701  if ( addr = nvram->netmask ) {
     1702        if ( pAddr = malloc ( INET_ADDR_MAX_BUF_SIZE, 0, M_NOWAIT ) )
     1703                        pConfig->ip_netmask = inet_ntop(AF_INET, &addr, pAddr, INET_ADDR_MAX_BUF_SIZE -1 );
     1704                else
     1705                        rtems_panic("Can't allocate ip_netmask buffer!\n");
     1706  }
     1707
     1708  /* Ethernet address can be specified in NVRAM, or in the ifconfig
     1709   * structure. It will be read by default from BBRAM at $FFFC1F2C
     1710   * (6 bytes) mvme167 manual p. 1-47
     1711   */
     1712  if ( nvram->enaddr ) {
     1713        memcpy (sc->arpcom.ac_enaddr, &nvram->enaddr, ETHER_ADDR_LEN);
     1714  }
     1715  else if ( pConfig->hardware_address) {
    16971716    memcpy (sc->arpcom.ac_enaddr, pConfig->hardware_address, ETHER_ADDR_LEN);
    16981717  }
     
    17001719    memcpy (sc->arpcom.ac_enaddr, (char *)0xFFFC1F2C, ETHER_ADDR_LEN);
    17011720  }
     1721
     1722  /* Possibly override default acceptance of broadcast packets */
     1723  if (pConfig->ignore_broadcast)
     1724        uti596initSetup[8] |= 0x02;
    17021725
    17031726  /* Assign requested receive buffer descriptor count */
     
    17161739  ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX;
    17171740  ifp->if_snd.ifq_maxlen = ifqmaxlen;
    1718         ifp->if_init = uti596_init;
     1741  ifp->if_init = uti596_init;
    17191742  ifp->if_ioctl = uti596_ioctl;
    17201743  ifp->if_start = uti596_start;
  • c/src/lib/libbsp/m68k/mvme167/startup/linkcmds

    rf481c39c r8ef3818  
    1818
    1919/* These are not really needed here */
    20 /* OUTPUT_FORMAT("elf32-m68k") */
     20OUTPUT_FORMAT("elf32-m68k")
    2121OUTPUT_ARCH(m68k)
    2222ENTRY(_start)
    2323
    2424/*
    25  * Declare some sizes.  Heap is sized at whatever ram space is left.
     25 * Declare some sizes. Heap is sized at whatever ram space is left.
    2626 */
    2727_RamBase = DEFINED(_RamBase) ? _RamBase : 0x00800000;
  • c/src/lib/libbsp/m68k/mvme167/startup/page_table.c

    rf481c39c r8ef3818  
    3333 *  errors if we address non-existent memory within this range. Our two
    3434 *  MVME167s are configured to exist at physical addresses 0x00800000 to
    35  *  0x00BFFFFF and 0x00C00000 to 0x00FFFFFF respectively. We map the space
    36  *  from 0x0 to 0x7FFFFFFF as copyback, unless jumper J1-5 is removed, in
    37  *  which case we map as writethrough. If jumper J1-7 is removed, the data
    38  *  cache is NOT enabled. If jumper J1-6 is removed, the instruction cache
    39  *  is not enabled.
     35 *  0x00BFFFFF and 0x00C00000 to 0x00FFFFFF respectively. If jumper J1-4 is
     36 *  installed, memeory and cache control can be done by providing parameters
     37 *  in NVRAM. See the README for details. If J1-4 is removed, behaviour
     38 *  defaults to the following. We map the space from 0x0 to 0x7FFFFFFF as
     39 *  copyback, unless jumper J1-5 is removed, in which case we map as writethrough.
     40 *  If jumper J1-7 is removed, the data cache is NOT enabled. If jumper J1-6
     41 *  is removed, the instruction cache is not enabled.
    4042 *
    4143 *  Copyright (c) 1998, National Research Council of Canada
     
    8587  dtt0 = 0x007FC020;
    8688 
    87   cacr = 0x80008000;              /* Data and instruction cache on */
     89  cacr = 0x00000000;              /* Data and instruction cache off */
    8890 
    8991  /* Read the J1 header */
    9092  j1 = (unsigned char)(lcsr->vector_base & 0xFF);
     93
     94  if ( !(j1 & 0x10) ) {
     95        /* Jumper J1-4 is on, configure from NVRAM */
     96
     97        if ( nvram->dcache_enable )
     98                cacr |= 0x80000000;
     99
     100        if ( nvram->icache_enable )
     101                cacr |= 0x00008000;
     102
     103        if ( nvram->cache_mode )
     104                dtt0 = ((nvram->cache_mode & 0x0003) << 5) | (dtt0 & 0xFFFFFF9F);
     105  }
     106        else {
     107                /* Configure according to other jumper settings */
    91108 
    92   if ( j1 & 0x80 )
    93     /* Jumper J1-7 if off, disable data caching */
    94     cacr &= 0x7FFFFFFF;
     109          if ( j1 & 0x80 )
     110          /* Jumper J1-7 if off, disable data caching */
     111                cacr &= 0x7FFFFFFF;
    95112     
    96   if ( j1 & 0x40 )
    97     /* Jumper J1-6 if off, disable instruction caching */
    98     cacr &= 0xFFFF7FFF;
     113          if ( j1 & 0x40 )
     114            /* Jumper J1-6 if off, disable instruction caching */
     115            cacr &= 0xFFFF7FFF;
    99116     
    100   if ( j1 & 0x20 )
    101     /* Jumper J1-5 is off, enable writethrough caching */
    102     dtt0 &= 0xFFFFFF9F;
    103  
     117          if ( j1 & 0x20 )
     118            /* Jumper J1-5 is off, enable writethrough caching */
     119            dtt0 &= 0xFFFFFF9F;
     120        }
     121
    104122  /* do it ! */
    105123  asm volatile("movec %0, %%tc    /* turn off paged address translation */
  • c/src/lib/libbsp/powerpc/eth_comm/canbus/canbus.c

    rf481c39c r8ef3818  
    1717#include <stdio.h>
    1818#include <bsp.h>
    19 #include <mpc860.h>
    2019#include <rtems/error.h>
    2120#include <canbus.h>
     
    310309  candev[minor]->ctrl &= ~(I82527_CTRL_CCE | I82527_CTRL_INIT);
    311310  switch (minor) {
    312   case 0: m860.simask |= M860_SIMASK_IRM3; break;
    313   case 1: m860.simask |= M860_SIMASK_IRM4; break;
    314   case 2: m860.simask |= M860_SIMASK_IRM2; break;
     311  case 0: m8xx.simask |= M8xx_SIMASK_IRM3; break;
     312  case 1: m8xx.simask |= M8xx_SIMASK_IRM4; break;
     313  case 2: m8xx.simask |= M8xx_SIMASK_IRM2; break;
    315314  default: return;
    316315  }
  • c/src/lib/libbsp/powerpc/eth_comm/console/console.c

    rf481c39c r8ef3818  
    2828 */
    2929
     30#include <bsp.h>                /* Must be before libio.h */
    3031#include <rtems/libio.h>
    31 #include <mpc860.h>
    32 #include <mpc860/console.h>
    3332#include <termios.h>
    3433
     
    3837{
    3938  rtems_status_code status;
    40   rtems_isr_entry old_handler;
    41   rtems_status_code sc;
    4239 
    4340#ifdef I_WANT_TERMIOS
     
    4946
    5047  /*
    51    * Set up Buffer Descriptors
    52    */
    53   m860_console_initialize();
     48   *  Do common initialization.
     49   */
     50  m8xx_uart_initialize();
    5451
    5552  /*
    5653   * Do device-specific initialization
    5754   */
    58   m860_scc_initialize(2);  /* /dev/console */
    59   m860_scc_initialize(3);  /* /dev/tty3   */
    60   m860_scc_initialize(4);  /* /dev/tty4   */
    61   m860_smc_initialize(1);  /* /dev/tty0   */
    62   m860_smc_initialize(2);  /* /dev/tty1   */
     55  m8xx_uart_smc_initialize(SMC1_MINOR); /* /dev/tty0 */
     56  m8xx_uart_smc_initialize(SMC2_MINOR); /* /dev/tty1 */                             
     57  m8xx_uart_scc_initialize(SCC2_MINOR); /* /dev/tty2    */
     58  m8xx_uart_scc_initialize(SCC3_MINOR); /* /dev/tty3    */
     59  m8xx_uart_scc_initialize(SCC4_MINOR); /* /dev/tty4    */
    6360 
    64   sc = rtems_interrupt_catch (m860_scc2_console_interrupt_handler,
    65                               PPC_IRQ_CPM_SCC2,
    66                               &old_handler);
    67   sc = rtems_interrupt_catch (m860_scc3_console_interrupt_handler,
    68                               PPC_IRQ_CPM_SCC3,
    69                               &old_handler);
    70   sc = rtems_interrupt_catch (m860_scc4_console_interrupt_handler,
    71                               PPC_IRQ_CPM_SCC4,
    72                               &old_handler);
    73   sc = rtems_interrupt_catch (m860_smc1_console_interrupt_handler,
    74                               PPC_IRQ_CPM_SMC1,
    75                               &old_handler);
    76   sc = rtems_interrupt_catch (m860_smc2_console_interrupt_handler,
    77                               PPC_IRQ_CPM_SMC2,
    78                               &old_handler);
     61  /*
     62   * Set up interrupts
     63   */
     64   m8xx_uart_interrupts_initialize();
    7965
    8066  /*
     
    10389                                 void *arg)
    10490{
    105   volatile m860SCCRegisters_t *sccregs;
     91  volatile m8xxSCCRegisters_t *sccregs;
    10692
    10793#ifdef I_WANT_TERMIOS
     
    10995    NULL,                       /* firstOpen */
    11096    NULL,                       /* lastClose */
    111     m860_char_poll_read,        /* pollRead */
    112     m860_char_poll_write,       /* write */
    113     m860_scc_set_attributes,    /* setAttributes */
     97    m8xx_uart_pollRead,        /* pollRead */
     98    m8xx_uart_pollWrite,       /* write */
     99    m8xx_uart_setAttributes,    /* setAttributes */
    114100    NULL,                       /* stopRemoteTx */
    115101    NULL,                       /* startRemoteTx */
     
    122108  switch (minor) {
    123109  case 0:
    124     m860.smc1.smcm = 1;           /* Enable SMC1 RX interrupts */
    125     m860.cimr |= 1UL <<  4;       /* Enable SMC1 interrupts */
     110    m8xx.smc1.smcm = 1;           /* Enable SMC1 RX interrupts */
     111    m8xx.cimr |= 1UL <<  4;       /* Enable SMC1 interrupts */
    126112    break;
    127113  case 1:
    128     m860.smc2.smcm = 1;           /* Enable SMC2 RX interrupts */
    129     m860.cimr |= 1UL <<  3;       /* Enable SMC2 interrupts */
     114    m8xx.smc2.smcm = 1;           /* Enable SMC2 RX interrupts */
     115    m8xx.cimr |= 1UL <<  3;       /* Enable SMC2 interrupts */
    130116    break;
    131117  case 2:
    132     m860.cimr |= 1UL << 30;      /* Enable SCC1 interrupts */
    133     sccregs = &m860.scc1;
     118    m8xx.cimr |= 1UL << 30;      /* Enable SCC1 interrupts */
     119    sccregs = &m8xx.scc1;
    134120    break;
    135121  case 3:
    136122#ifndef I_WANT_TERMIOS
    137     m860.cimr |= 1UL << 29;      /* Enable SCC2 interrupts */
     123    m8xx.cimr |= 1UL << 29;      /* Enable SCC2 interrupts */
    138124#endif /* I_WANT_TERMIOS */
    139     sccregs = &m860.scc2;
     125    sccregs = &m8xx.scc2;
    140126    break;
    141127  case 4:
    142     m860.cimr |= 1UL << 28;      /* Enable SCC3 interrupts */
    143     sccregs = &m860.scc3;
     128    m8xx.cimr |= 1UL << 28;      /* Enable SCC3 interrupts */
     129    sccregs = &m8xx.scc3;
    144130    break;
    145131  case 5:
    146     m860.cimr |= 1UL << 27;      /* Enable SCC4 interrupts */
    147     sccregs = &m860.scc4;
     132    m8xx.cimr |= 1UL << 27;      /* Enable SCC4 interrupts */
     133    sccregs = &m8xx.scc4;
    148134    break;
    149135  default:
     
    187173{
    188174#ifdef I_WANT_TERMIOS
    189   if (minor == SCC2_MINOR) {
     175  /*
     176  if (minor == SCC2_MINOR) {
     177  */
    190178    return rtems_termios_read(arg);
    191   }
    192   else {
    193     return m860_console_read(major, minor, arg);
    194   }
    195 #else
    196   return m860_console_read(major, minor, arg);
     179  /*
     180  }
     181  else {
     182    return m8xx_console_read(major, minor, arg);
     183  }
     184  */
     185#else
     186  return m8xx_console_read(major, minor, arg);
    197187#endif
    198188}
     
    203193{
    204194#ifdef I_WANT_TERMIOS
    205   if (minor == SCC2_MINOR) {
     195  /*
     196  if (minor == SCC2_MINOR) {
     197  */
    206198    return rtems_termios_write(arg);
    207   }
    208   else {
    209     return m860_console_write(major, minor, arg);
    210   }
    211 #else
    212   return m860_console_write(major, minor, arg);
     199  /*
     200  }
     201  else {
     202    return m8xx_console_write(major, minor, arg);
     203  }
     204  */
     205#else
     206  return m8xx_console_write(major, minor, arg);
    213207#endif
    214208}
  • c/src/lib/libbsp/powerpc/eth_comm/include/bsp.h

    rf481c39c r8ef3818  
    2525#include <console.h>
    2626#include <clockdrv.h>
     27#include <mpc8xx.h>
     28#include <mpc8xx/cpm.h>
     29#include <mpc8xx/mmu.h>
     30#include <mpc8xx/console.h>
    2731
    2832/*
  • c/src/lib/libbsp/powerpc/eth_comm/network/network.c

    rf481c39c r8ef3818  
    1818 */
    1919#include <bsp.h>
    20 #include <mpc860.h>
    2120#include <stdio.h>
    2221#include <rtems/error.h>
     
    8180        int                     txBdTail;
    8281        int                     txBdActiveCount;
    83         m860BufferDescriptor_t  *rxBdBase;
    84         m860BufferDescriptor_t  *txBdBase;
     82        m8xxBufferDescriptor_t  *rxBdBase;
     83        m8xxBufferDescriptor_t  *txBdBase;
    8584        rtems_id                rxDaemonTid;
    8685        rtems_id                txDaemonTid;
     
    119118         * Frame received?
    120119         */
    121         if ((m860.scc1.sccm & 0x8) && (m860.scc1.scce & 0x8)) {
    122                 m860.scc1.scce = 0x8;
     120        if ((m8xx.scc1.sccm & 0x8) && (m8xx.scc1.scce & 0x8)) {
     121                m8xx.scc1.scce = 0x8;
    123122                /* I don't think the next line is needed. It was in
    124123                 * the 68360 stuff, though.
    125                  *   m860.scc1.sccm &= ~0x8;
     124                 *   m8xx.scc1.sccm &= ~0x8;
    126125                 */
    127126                enet_driver[0].rxInterrupts++;
     
    132131         * Buffer transmitted or transmitter error?
    133132         */
    134         if ((m860.scc1.sccm & 0x12) && (m860.scc1.scce & 0x12)) {
    135                 m860.scc1.scce = 0x12;
     133        if ((m8xx.scc1.sccm & 0x12) && (m8xx.scc1.scce & 0x12)) {
     134                m8xx.scc1.scce = 0x12;
    136135                /* I don't think the next line is needed. It was in
    137136                 * the 68360 stuff, though.
    138                  *   m860.scc1.sccm &= ~0x12;
     137                 *   m8xx.scc1.sccm &= ~0x12;
    139138                 */
    140139                enet_driver[0].txInterrupts++;
    141140                rtems_event_send (enet_driver[0].txDaemonTid, INTERRUPT_EVENT);
    142141        }
    143         m860.cisr = 1UL << 30;  /* Clear SCC1 interrupt-in-service bit */
     142        m8xx.cisr = 1UL << 30;  /* Clear SCC1 interrupt-in-service bit */
    144143}
    145144
     
    153152   * Frame received?
    154153   */
    155   if (m860.fec.ievent & M860_FEC_IEVENT_RFINT) {
    156     m860.fec.ievent = M860_FEC_IEVENT_RFINT;
     154  if (m8xx.fec.ievent & M8xx_FEC_IEVENT_RFINT) {
     155    m8xx.fec.ievent = M8xx_FEC_IEVENT_RFINT;
    157156    enet_driver[0].rxInterrupts++;
    158157    rtems_event_send (enet_driver[0].rxDaemonTid, INTERRUPT_EVENT);
     
    162161   * Buffer transmitted or transmitter error?
    163162   */
    164   if (m860.fec.ievent & M860_FEC_IEVENT_TFINT) {
    165     m860.fec.ievent = M860_FEC_IEVENT_TFINT;
     163  if (m8xx.fec.ievent & M8xx_FEC_IEVENT_TFINT) {
     164    m8xx.fec.ievent = M8xx_FEC_IEVENT_TFINT;
    166165    enet_driver[0].txInterrupts++;
    167166    rtems_event_send (enet_driver[0].txDaemonTid, INTERRUPT_EVENT);
     
    183182   * Configure port A CLK1, CLK2, TXD1 and RXD1 pins
    184183   */
    185   m860.papar |=  0x303;
    186   m860.padir &= ~0x303;
    187   m860.paodr &= ~0x303;
     184  m8xx.papar |=  0x303;
     185  m8xx.padir &= ~0x303;
     186  m8xx.paodr &= ~0x303;
    188187 
    189188  /*
     
    191190   * 
    192191   */
    193   m860.pcpar &= ~0x30;
    194   m860.pcdir |= 0x0f00;
    195   m860.pcdir &= ~0x30;
    196   m860.pcso  |=  0x30;
    197   m860.pcdat &= ~0x0f00;  /* Clear LOOP */
    198   m860.pcdat |= 0x0700;   /* Set FULDL, TPSQEL, TPAPCE */
     192  m8xx.pcpar &= ~0x30;
     193  m8xx.pcdir |= 0x0f00;
     194  m8xx.pcdir &= ~0x30;
     195  m8xx.pcso  |=  0x30;
     196  m8xx.pcdat &= ~0x0f00;  /* Clear LOOP */
     197  m8xx.pcdat |= 0x0700;   /* Set FULDL, TPSQEL, TPAPCE */
    199198 
    200199  /*
    201200   * Connect CLK1 and CLK2 to SCC1
    202201   */
    203   m860.sicr &= ~0xFF;
    204   m860.sicr |= (5 << 3) | 4;
     202  m8xx.sicr &= ~0xFF;
     203  m8xx.sicr |= (5 << 3) | 4;
    205204 
    206205  /*
    207206   * Initialize SDMA configuration register
    208207   */
    209   m860.sdcr = 1;
     208  m8xx.sdcr = 1;
    210209 
    211210  /*
     
    222221   * Set receiver and transmitter buffer descriptor bases
    223222   */
    224   sc->rxBdBase = M860AllocateBufferDescriptors(sc->rxBdCount);
    225   sc->txBdBase = M860AllocateBufferDescriptors(sc->txBdCount);
    226   m860.scc1p.rbase = (char *)sc->rxBdBase - (char *)&m860;
    227   m860.scc1p.tbase = (char *)sc->txBdBase - (char *)&m860;
     223  sc->rxBdBase = m8xx_bd_allocate(sc->rxBdCount);
     224  sc->txBdBase = m8xx_bd_allocate(sc->txBdCount);
     225  m8xx.scc1p.rbase = (char *)sc->rxBdBase - (char *)&m8xx;
     226  m8xx.scc1p.tbase = (char *)sc->txBdBase - (char *)&m8xx;
    228227 
    229228  /*
    230229   * Send "Init parameters" command
    231230   */
    232   M860ExecuteRISC (M860_CR_OP_INIT_RX_TX | M860_CR_CHAN_SCC1);
     231  m8xx_cp_execute_cmd (M8xx_CR_OP_INIT_RX_TX | M8xx_CR_CHAN_SCC1);
    233232 
    234233  /*
    235234   * Set receive and transmit function codes
    236235   */
    237   m860.scc1p.rfcr = M860_RFCR_MOT | M860_RFCR_DMA_SPACE(0);
    238   m860.scc1p.tfcr = M860_TFCR_MOT | M860_TFCR_DMA_SPACE(0);
     236  m8xx.scc1p.rfcr = M8xx_RFCR_MOT | M8xx_RFCR_DMA_SPACE(0);
     237  m8xx.scc1p.tfcr = M8xx_TFCR_MOT | M8xx_TFCR_DMA_SPACE(0);
    239238 
    240239  /*
    241240   * Set maximum receive buffer length
    242241   */
    243   m860.scc1p.mrblr = RBUF_SIZE;
     242  m8xx.scc1p.mrblr = RBUF_SIZE;
    244243 
    245244  /*
    246245   * Set CRC parameters
    247246   */
    248   m860.scc1p.un.ethernet.c_pres = 0xFFFFFFFF;
    249   m860.scc1p.un.ethernet.c_mask = 0xDEBB20E3;
     247  m8xx.scc1p.un.ethernet.c_pres = 0xFFFFFFFF;
     248  m8xx.scc1p.un.ethernet.c_mask = 0xDEBB20E3;
    250249 
    251250  /*
    252251   * Clear diagnostic counters
    253252   */
    254   m860.scc1p.un.ethernet.crcec = 0;
    255   m860.scc1p.un.ethernet.alec = 0;
    256   m860.scc1p.un.ethernet.disfc = 0;
     253  m8xx.scc1p.un.ethernet.crcec = 0;
     254  m8xx.scc1p.un.ethernet.alec = 0;
     255  m8xx.scc1p.un.ethernet.disfc = 0;
    257256 
    258257  /*
    259258   * Set pad value
    260259   */
    261   m860.scc1p.un.ethernet.pads = 0x8888;
     260  m8xx.scc1p.un.ethernet.pads = 0x8888;
    262261 
    263262  /*
    264263   * Set retry limit
    265264   */
    266   m860.scc1p.un.ethernet.ret_lim = 15;
     265  m8xx.scc1p.un.ethernet.ret_lim = 15;
    267266 
    268267  /*
    269268   * Set maximum and minimum frame length
    270269   */
    271   m860.scc1p.un.ethernet.mflr = 1518;
    272   m860.scc1p.un.ethernet.minflr = 64;
    273   m860.scc1p.un.ethernet.maxd1 = RBUF_SIZE;
    274   m860.scc1p.un.ethernet.maxd2 = RBUF_SIZE;
     270  m8xx.scc1p.un.ethernet.mflr = 1518;
     271  m8xx.scc1p.un.ethernet.minflr = 64;
     272  m8xx.scc1p.un.ethernet.maxd1 = RBUF_SIZE;
     273  m8xx.scc1p.un.ethernet.maxd2 = RBUF_SIZE;
    275274 
    276275  /*
    277276   * Clear group address hash table
    278277   */
    279   m860.scc1p.un.ethernet.gaddr1 = 0;
    280   m860.scc1p.un.ethernet.gaddr2 = 0;
    281   m860.scc1p.un.ethernet.gaddr3 = 0;
    282   m860.scc1p.un.ethernet.gaddr4 = 0;
     278  m8xx.scc1p.un.ethernet.gaddr1 = 0;
     279  m8xx.scc1p.un.ethernet.gaddr2 = 0;
     280  m8xx.scc1p.un.ethernet.gaddr3 = 0;
     281  m8xx.scc1p.un.ethernet.gaddr4 = 0;
    283282 
    284283  /*
     
    287286  hwaddr = sc->arpcom.ac_enaddr;
    288287 
    289   m860.scc1p.un.ethernet.paddr_h = (hwaddr[5] << 8) | hwaddr[4];
    290   m860.scc1p.un.ethernet.paddr_m = (hwaddr[3] << 8) | hwaddr[2];
    291   m860.scc1p.un.ethernet.paddr_l = (hwaddr[1] << 8) | hwaddr[0];
     288  m8xx.scc1p.un.ethernet.paddr_h = (hwaddr[5] << 8) | hwaddr[4];
     289  m8xx.scc1p.un.ethernet.paddr_m = (hwaddr[3] << 8) | hwaddr[2];
     290  m8xx.scc1p.un.ethernet.paddr_l = (hwaddr[1] << 8) | hwaddr[0];
    292291 
    293292  /*
    294293   * Aggressive retry
    295294   */
    296   m860.scc1p.un.ethernet.p_per = 0;
     295  m8xx.scc1p.un.ethernet.p_per = 0;
    297296 
    298297  /*
    299298   * Clear individual address hash table
    300299   */
    301   m860.scc1p.un.ethernet.iaddr1 = 0;
    302   m860.scc1p.un.ethernet.iaddr2 = 0;
    303   m860.scc1p.un.ethernet.iaddr3 = 0;
    304   m860.scc1p.un.ethernet.iaddr4 = 0;
     300  m8xx.scc1p.un.ethernet.iaddr1 = 0;
     301  m8xx.scc1p.un.ethernet.iaddr2 = 0;
     302  m8xx.scc1p.un.ethernet.iaddr3 = 0;
     303  m8xx.scc1p.un.ethernet.iaddr4 = 0;
    305304 
    306305  /*
    307306   * Clear temp address
    308307   */
    309   m860.scc1p.un.ethernet.taddr_l = 0;
    310   m860.scc1p.un.ethernet.taddr_m = 0;
    311   m860.scc1p.un.ethernet.taddr_h = 0;
     308  m8xx.scc1p.un.ethernet.taddr_l = 0;
     309  m8xx.scc1p.un.ethernet.taddr_m = 0;
     310  m8xx.scc1p.un.ethernet.taddr_h = 0;
    312311 
    313312  /*
     
    331330   * Clear any outstanding events
    332331   */
    333   m860.scc1.scce = 0xFFFF;
     332  m8xx.scc1.scce = 0xFFFF;
    334333 
    335334  /*
     
    343342                 rtems_status_text (status));
    344343  }
    345   m860.scc1.sccm = 0;     /* No interrupts unmasked till necessary */
    346   m860.cimr |= (1UL << 30);       /* Enable SCC1 interrupt */
     344  m8xx.scc1.sccm = 0;     /* No interrupts unmasked till necessary */
     345  m8xx.cimr |= (1UL << 30);       /* Enable SCC1 interrupt */
    347346 
    348347  /*
     
    350349   * Ethernet configuration
    351350   */
    352   m860.scc1.gsmr_h = 0x0;
    353   m860.scc1.gsmr_l = 0x1088000c;
     351  m8xx.scc1.gsmr_h = 0x0;
     352  m8xx.scc1.gsmr_l = 0x1088000c;
    354353 
    355354  /*
     
    357356   * Ethernet synchronization pattern
    358357   */
    359   m860.scc1.dsr = 0xd555;
     358  m8xx.scc1.dsr = 0xd555;
    360359 
    361360  /*
     
    375374   *      Disable full-duplex operation
    376375   */
    377   m860.scc1.psmr = 0x080A | (sc->acceptBroadcast ? 0 : 0x100);
     376  m8xx.scc1.psmr = 0x080A | (sc->acceptBroadcast ? 0 : 0x100);
    378377 
    379378  /*
    380379   * Enable the TENA (RTS1*) pin
    381380   */
    382   m860.pcpar |=  0x1;
    383   m860.pcdir &= ~0x1;
     381  m8xx.pcpar |=  0x1;
     382  m8xx.pcdir &= ~0x1;
    384383 
    385384 
     
    395394   *   Put this comment in each module that sets these 2 registers
    396395   */
    397   m860.cicr = 0x00e43e80;   /* SCaP=SCC1, SCbP=SCC2, SCcP=SCC3,
     396  m8xx.cicr = 0x00e43e80;   /* SCaP=SCC1, SCbP=SCC2, SCcP=SCC3,
    398397                               SCdP=SCC4, IRL=1, HP=SCC1, IEN=1 */
    399   m860.simask |= M860_SIMASK_LVM1;
     398  m8xx.simask |= M8xx_SIMASK_LVM1;
    400399 
    401400  /*
    402401   * Enable receiver and transmitter
    403402   */
    404   m860.scc1.gsmr_l = 0x1088003c;
     403  m8xx.scc1.gsmr_l = 0x1088003c;
    405404}
    406405
     
    416415   * Issue reset to FEC
    417416   */
    418   m860.fec.ecntrl=0x1;
     417  m8xx.fec.ecntrl=0x1;
    419418
    420419  /*
    421420   * Put ethernet transciever in reset
    422421   */
    423   m860.pgcra |= 0x80;
     422  m8xx.pgcra |= 0x80;
    424423
    425424  /*
    426425   * Configure I/O ports
    427426   */
    428   m860.pdpar = 0x1fff;
    429   m860.pddir = 0x1c58;
     427  m8xx.pdpar = 0x1fff;
     428  m8xx.pddir = 0x1c58;
    430429
    431430  /*
    432431   * Take ethernet transciever out of reset
    433432   */
    434   m860.pgcra &= ~0x80;
     433  m8xx.pgcra &= ~0x80;
    435434
    436435
     
    439438   * 
    440439   */
    441   m860.fec.ivec = 0x02 << 29;
     440  m8xx.fec.ivec = 0x02 << 29;
    442441 
    443442  /*
     
    445444   */
    446445  /* If you uncomment these, the FEC will not work right.
    447   m860.fec.r_fstart = ((m860.fec.r_bound & 0x3ff) >> 2) & 0x3ff;
    448   m860.fec.x_fstart = 0;
     446  m8xx.fec.r_fstart = ((m8xx.fec.r_bound & 0x3ff) >> 2) & 0x3ff;
     447  m8xx.fec.x_fstart = 0;
    449448  */
    450449
     
    454453  hwaddr = sc->arpcom.ac_enaddr;
    455454 
    456   m860.fec.addr_low = (hwaddr[0] << 24) | (hwaddr[1] << 16) |
     455  m8xx.fec.addr_low = (hwaddr[0] << 24) | (hwaddr[1] << 16) |
    457456                      (hwaddr[2] << 8)  | (hwaddr[3] << 0);
    458   m860.fec.addr_high = (hwaddr[4] << 24) | (hwaddr[5] << 16);
     457  m8xx.fec.addr_high = (hwaddr[4] << 24) | (hwaddr[5] << 16);
    459458
    460459  /*
    461460   * Clear the hash table
    462461   */
    463   m860.fec.hash_table_high = 0;
    464   m860.fec.hash_table_low  = 0;
     462  m8xx.fec.hash_table_high = 0;
     463  m8xx.fec.hash_table_low  = 0;
    465464
    466465  /*
    467466   * Set up receive buffer size
    468467   */
    469   m860.fec.r_buf_size = 0x5f0; /* set to 1520 */
     468  m8xx.fec.r_buf_size = 0x5f0; /* set to 1520 */
    470469
    471470  /*
     
    482481   * Set receiver and transmitter buffer descriptor bases
    483482   */
    484   sc->rxBdBase = M860AllocateBufferDescriptors(sc->rxBdCount);
    485   sc->txBdBase = M860AllocateBufferDescriptors(sc->txBdCount);
    486   m860.fec.r_des_start = (int)sc->rxBdBase;
    487   m860.fec.x_des_start = (int)sc->txBdBase;
     483  sc->rxBdBase = m8xx_bd_allocate(sc->rxBdCount);
     484  sc->txBdBase = m8xx_bd_allocate(sc->txBdCount);
     485  m8xx.fec.r_des_start = (int)sc->rxBdBase;
     486  m8xx.fec.x_des_start = (int)sc->txBdBase;
    488487 
    489488  /*
     
    494493   *   No loopback
    495494   */
    496   m860.fec.r_cntrl = 0x00000006;
     495  m8xx.fec.r_cntrl = 0x00000006;
    497496
    498497  /*
     
    501500   *   No heartbeat
    502501   */
    503   m860.fec.x_cntrl = 0x00000000;
     502  m8xx.fec.x_cntrl = 0x00000000;
    504503
    505504  /*
     
    508507   *   DMA functino code = 0
    509508   */
    510   m860.fec.fun_code = 0x78000000;
     509  m8xx.fec.fun_code = 0x78000000;
    511510
    512511  /*
     
    517516   *   RISC arbitration ID = 1 => U-bus arbitration = 5
    518517   */
    519   m860.sdcr = 1;
     518  m8xx.sdcr = 1;
    520519
    521520  /*
    522521   * Set MII speed to 2.5 MHz for 25 Mhz system clock 
    523522   */
    524   m860.fec.mii_speed = 0x0a;
    525   m860.fec.mii_data = 0x58021000;
     523  m8xx.fec.mii_speed = 0x0a;
     524  m8xx.fec.mii_data = 0x58021000;
    526525 
    527526  /*
     
    546545   * Mask all FEC interrupts and clear events
    547546   */
    548   m860.fec.imask = M860_FEC_IEVENT_TFINT |
    549                    M860_FEC_IEVENT_RFINT;
    550   m860.fec.ievent = ~0;
     547  m8xx.fec.imask = M8xx_FEC_IEVENT_TFINT |
     548                   M8xx_FEC_IEVENT_RFINT;
     549  m8xx.fec.ievent = ~0;
    551550
    552551  /*
     
    560559                 rtems_status_text (status));
    561560
    562   m860.simask |= M860_SIMASK_LVM2;
     561  m8xx.simask |= M8xx_SIMASK_LVM2;
    563562
    564563}
     
    584583  nRetired = 0;
    585584  while ((sc->txBdActiveCount != 0)
    586          &&  (((status = (sc->txBdBase + i)->status) & M860_BD_READY) == 0)) {
     585         &&  (((status = (sc->txBdBase + i)->status) & M8xx_BD_READY) == 0)) {
    587586    /*
    588587     * See if anything went wrong
    589588     */
    590     if (status & (M860_BD_DEFER |
    591                   M860_BD_HEARTBEAT |
    592                   M860_BD_LATE_COLLISION |
    593                   M860_BD_RETRY_LIMIT |
    594                   M860_BD_UNDERRUN |
    595                   M860_BD_CARRIER_LOST)) {
     589    if (status & (M8xx_BD_DEFER |
     590                  M8xx_BD_HEARTBEAT |
     591                  M8xx_BD_LATE_COLLISION |
     592                  M8xx_BD_RETRY_LIMIT |
     593                  M8xx_BD_UNDERRUN |
     594                  M8xx_BD_CARRIER_LOST)) {
    596595      /*
    597596       * Check for errors which stop the transmitter.
    598597       */
    599       if (status & (M860_BD_LATE_COLLISION |
    600                     M860_BD_RETRY_LIMIT |
    601                     M860_BD_UNDERRUN)) {
    602         if (status & M860_BD_LATE_COLLISION)
     598      if (status & (M8xx_BD_LATE_COLLISION |
     599                    M8xx_BD_RETRY_LIMIT |
     600                    M8xx_BD_UNDERRUN)) {
     601        if (status & M8xx_BD_LATE_COLLISION)
    603602          enet_driver[0].txLateCollision++;
    604         if (status & M860_BD_RETRY_LIMIT)
     603        if (status & M8xx_BD_RETRY_LIMIT)
    605604          enet_driver[0].txRetryLimit++;
    606         if (status & M860_BD_UNDERRUN)
     605        if (status & M8xx_BD_UNDERRUN)
    607606          enet_driver[0].txUnderrun++;
    608607       
     
    611610         */
    612611        /* FIXME: this should get executed only if using the SCC */
    613         M860ExecuteRISC (M860_CR_OP_RESTART_TX | M860_CR_CHAN_SCC1);
     612        m8xx_cp_execute_cmd (M8xx_CR_OP_RESTART_TX | M8xx_CR_CHAN_SCC1);
    614613      }
    615       if (status & M860_BD_DEFER)
     614      if (status & M8xx_BD_DEFER)
    616615        enet_driver[0].txDeferred++;
    617       if (status & M860_BD_HEARTBEAT)
     616      if (status & M8xx_BD_HEARTBEAT)
    618617        enet_driver[0].txHeartbeat++;
    619       if (status & M860_BD_CARRIER_LOST)
     618      if (status & M8xx_BD_CARRIER_LOST)
    620619        enet_driver[0].txLostCarrier++;
    621620    }
    622621    nRetired++;
    623     if (status & M860_BD_LAST) {
     622    if (status & M8xx_BD_LAST) {
    624623      /*
    625624       * A full frame has been transmitted.
     
    650649  struct mbuf *m;
    651650  rtems_unsigned16 status;
    652   m860BufferDescriptor_t *rxBd;
     651  m8xxBufferDescriptor_t *rxBd;
    653652  int rxBdIndex;
    654653 
     
    663662    sc->rxMbuf[rxBdIndex] = m;
    664663    rxBd->buffer = mtod (m, void *);
    665     rxBd->status = M860_BD_EMPTY | M860_BD_INTERRUPT;
     664    rxBd->status = M8xx_BD_EMPTY | M8xx_BD_INTERRUPT;
    666665    if (++rxBdIndex == sc->rxBdCount) {
    667       rxBd->status |= M860_BD_WRAP;
     666      rxBd->status |= M8xx_BD_WRAP;
    668667      break;
    669668    }
     
    680679     * Wait for packet if there's not one ready
    681680     */
    682     if ((status = rxBd->status) & M860_BD_EMPTY) {
     681    if ((status = rxBd->status) & M8xx_BD_EMPTY) {
    683682      /*
    684683       * Clear old events
    685684       */
    686       m860.scc1.scce = 0x8;
     685      m8xx.scc1.scce = 0x8;
    687686     
    688687      /*
     
    693692       * `if' above, and the clearing of the event register.
    694693       */
    695       while ((status = rxBd->status) & M860_BD_EMPTY) {
     694      while ((status = rxBd->status) & M8xx_BD_EMPTY) {
    696695        rtems_event_set events;
    697696       
     
    699698         * Unmask RXF (Full frame received) event
    700699         */
    701         m860.scc1.sccm |= 0x8;
     700        m8xx.scc1.sccm |= 0x8;
    702701       
    703702        rtems_bsdnet_event_receive (INTERRUPT_EVENT,
     
    711710     * Check that packet is valid
    712711     */
    713     if ((status & (M860_BD_LAST |
    714                    M860_BD_FIRST_IN_FRAME |
    715                    M860_BD_LONG |
    716                    M860_BD_NONALIGNED |
    717                    M860_BD_SHORT |
    718                    M860_BD_CRC_ERROR |
    719                    M860_BD_OVERRUN |
    720                    M860_BD_COLLISION)) ==
    721         (M860_BD_LAST |
    722          M860_BD_FIRST_IN_FRAME)) {
     712    if ((status & (M8xx_BD_LAST |
     713                   M8xx_BD_FIRST_IN_FRAME |
     714                   M8xx_BD_LONG |
     715                   M8xx_BD_NONALIGNED |
     716                   M8xx_BD_SHORT |
     717                   M8xx_BD_CRC_ERROR |
     718                   M8xx_BD_OVERRUN |
     719                   M8xx_BD_COLLISION)) ==
     720        (M8xx_BD_LAST |
     721         M8xx_BD_FIRST_IN_FRAME)) {
    723722      /*
    724723       * Pass the packet up the chain.
     
    748747       * Something went wrong with the reception
    749748       */
    750       if (!(status & M860_BD_LAST))
     749      if (!(status & M8xx_BD_LAST))
    751750        sc->rxNotLast++;
    752       if (!(status & M860_BD_FIRST_IN_FRAME))
     751      if (!(status & M8xx_BD_FIRST_IN_FRAME))
    753752        sc->rxNotFirst++;
    754       if (status & M860_BD_LONG)
     753      if (status & M8xx_BD_LONG)
    755754        sc->rxGiant++;
    756       if (status & M860_BD_NONALIGNED)
     755      if (status & M8xx_BD_NONALIGNED)
    757756        sc->rxNonOctet++;
    758       if (status & M860_BD_SHORT)
     757      if (status & M8xx_BD_SHORT)
    759758        sc->rxRunt++;
    760       if (status & M860_BD_CRC_ERROR)
     759      if (status & M8xx_BD_CRC_ERROR)
    761760        sc->rxBadCRC++;
    762       if (status & M860_BD_OVERRUN)
     761      if (status & M8xx_BD_OVERRUN)
    763762        sc->rxOverrun++;
    764       if (status & M860_BD_COLLISION)
     763      if (status & M8xx_BD_COLLISION)
    765764        sc->rxCollision++;
    766765    }
     
    769768     * Reenable the buffer descriptor
    770769     */
    771     rxBd->status = (status & (M860_BD_WRAP | M860_BD_INTERRUPT)) |
    772                     M860_BD_EMPTY;
     770    rxBd->status = (status & (M8xx_BD_WRAP | M8xx_BD_INTERRUPT)) |
     771                    M8xx_BD_EMPTY;
    773772   
    774773    /*
     
    787786  struct mbuf *m;
    788787  rtems_unsigned16 status;
    789   m860BufferDescriptor_t *rxBd;
     788  m8xxBufferDescriptor_t *rxBd;
    790789  int rxBdIndex;
    791790 
     
    800799    sc->rxMbuf[rxBdIndex] = m;
    801800    rxBd->buffer = mtod (m, void *);
    802     rxBd->status = M860_BD_EMPTY;
    803     m860.fec.r_des_active = 0x1000000;
     801    rxBd->status = M8xx_BD_EMPTY;
     802    m8xx.fec.r_des_active = 0x1000000;
    804803    if (++rxBdIndex == sc->rxBdCount) {
    805       rxBd->status |= M860_BD_WRAP;
     804      rxBd->status |= M8xx_BD_WRAP;
    806805      break;
    807806    }
     
    818817     * Wait for packet if there's not one ready
    819818     */
    820     if ((status = rxBd->status) & M860_BD_EMPTY) {
     819    if ((status = rxBd->status) & M8xx_BD_EMPTY) {
    821820      /*
    822821       * Clear old events
    823822       */
    824       m860.fec.ievent = M860_FEC_IEVENT_RFINT;
     823      m8xx.fec.ievent = M8xx_FEC_IEVENT_RFINT;
    825824     
    826825      /*
     
    831830       * `if' above, and the clearing of the event register.
    832831       */
    833       while ((status = rxBd->status) & M860_BD_EMPTY) {
     832      while ((status = rxBd->status) & M8xx_BD_EMPTY) {
    834833        rtems_event_set events;
    835834       
     
    837836         * Unmask RXF (Full frame received) event
    838837         */
    839         m860.fec.ievent |= M860_FEC_IEVENT_RFINT;
     838        m8xx.fec.ievent |= M8xx_FEC_IEVENT_RFINT;
    840839       
    841840        rtems_bsdnet_event_receive (INTERRUPT_EVENT,
     
    849848     * Check that packet is valid
    850849     */
    851     if (status & M860_BD_LAST) {
     850    if (status & M8xx_BD_LAST) {
    852851      /*
    853852       * Pass the packet up the chain.
     
    877876       * Something went wrong with the reception
    878877       */
    879       if (!(status & M860_BD_LAST))
     878      if (!(status & M8xx_BD_LAST))
    880879        sc->rxNotLast++;
    881       if (status & M860_BD_LONG)
     880      if (status & M8xx_BD_LONG)
    882881        sc->rxGiant++;
    883       if (status & M860_BD_NONALIGNED)
     882      if (status & M8xx_BD_NONALIGNED)
    884883        sc->rxNonOctet++;
    885       if (status & M860_BD_SHORT)
     884      if (status & M8xx_BD_SHORT)
    886885        sc->rxRunt++;
    887       if (status & M860_BD_CRC_ERROR)
     886      if (status & M8xx_BD_CRC_ERROR)
    888887        sc->rxBadCRC++;
    889       if (status & M860_BD_OVERRUN)
     888      if (status & M8xx_BD_OVERRUN)
    890889        sc->rxOverrun++;
    891       if (status & M860_BD_COLLISION)
     890      if (status & M8xx_BD_COLLISION)
    892891        sc->rxCollision++;
    893892    }
     
    895894     * Reenable the buffer descriptor
    896895     */
    897     rxBd->status = (status & M860_BD_WRAP) |
    898                     M860_BD_EMPTY;
    899     m860.fec.r_des_active = 0x1000000;
     896    rxBd->status = (status & M8xx_BD_WRAP) |
     897                    M8xx_BD_EMPTY;
     898    m8xx.fec.r_des_active = 0x1000000;
    900899    /*
    901900     * Move to next buffer descriptor
     
    910909{
    911910  struct m860_enet_struct *sc = ifp->if_softc;
    912   volatile m860BufferDescriptor_t *firstTxBd, *txBd;
     911  volatile m8xxBufferDescriptor_t *firstTxBd, *txBd;
    913912  struct mbuf *l = NULL;
    914913  rtems_unsigned16 status;
     
    937936       * Clear old events
    938937       */
    939       m860.scc1.scce = 0x12;
     938      m8xx.scc1.scce = 0x12;
    940939     
    941940      /*
     
    959958                                 * TXE (transmitter error) events.
    960959                                 */
    961         m860.scc1.sccm |= 0x12;
     960        m8xx.scc1.sccm |= 0x12;
    962961        rtems_bsdnet_event_receive (INTERRUPT_EVENT,
    963962                                    RTEMS_WAIT|RTEMS_EVENT_ANY,
     
    972971     * whole packet has been readied.
    973972     */
    974     status = nAdded ? M860_BD_READY : 0;
     973    status = nAdded ? M8xx_BD_READY : 0;
    975974   
    976975    /*
     
    991990      nAdded++;
    992991      if (++sc->txBdHead == sc->txBdCount) {
    993         status |= M860_BD_WRAP;
     992        status |= M8xx_BD_WRAP;
    994993        sc->txBdHead = 0;
    995994      }
     
    10141013    if (m == NULL) {
    10151014      if (nAdded) {
    1016         status |= M860_BD_PAD | M860_BD_LAST | M860_BD_TX_CRC | M860_BD_INTERRUPT;
     1015        status |= M8xx_BD_PAD | M8xx_BD_LAST | M8xx_BD_TX_CRC | M8xx_BD_INTERRUPT;
    10171016        txBd->status = status;
    1018         firstTxBd->status |= M860_BD_READY;
     1017        firstTxBd->status |= M8xx_BD_READY;
    10191018        sc->txBdActiveCount += nAdded;
    10201019      }
     
    10301029{
    10311030  struct m860_enet_struct *sc = ifp->if_softc;
    1032   volatile m860BufferDescriptor_t *firstTxBd, *txBd;
     1031  volatile m8xxBufferDescriptor_t *firstTxBd, *txBd;
    10331032  /*  struct mbuf *l = NULL; */
    10341033  rtems_unsigned16 status;
     
    10381037   * Free up buffer descriptors
    10391038   */
    1040   m860Enet_retire_tx_bd (sc);
     1039  m8xxEnet_retire_tx_bd (sc);
    10411040 
    10421041  /*
     
    10571056       * Clear old events
    10581057       */
    1059       m860.fec.ievent = M860_FEC_IEVENT_TFINT;
     1058      m8xx.fec.ievent = M8xx_FEC_IEVENT_TFINT;
    10601059     
    10611060      /*
     
    10791078         * TXE (transmitter error) events.
    10801079         */
    1081         m860.fec.ievent |= M860_FEC_IEVENT_TFINT;
     1080        m8xx.fec.ievent |= M8xx_FEC_IEVENT_TFINT;
    10821081        rtems_bsdnet_event_receive (INTERRUPT_EVENT,
    10831082                                    RTEMS_WAIT|RTEMS_EVENT_ANY,
     
    10921091     * whole packet has been readied.
    10931092     */
    1094     status = nAdded ? M860_BD_READY : 0;
     1093    status = nAdded ? M8xx_BD_READY : 0;
    10951094   
    10961095    /*
     
    11111110      nAdded++;
    11121111      if (++sc->txBdHead == sc->txBdCount) {
    1113         status |= M860_BD_WRAP;
     1112        status |= M8xx_BD_WRAP;
    11141113        sc->txBdHead = 0;
    11151114      }
     
    11361135    if (m == NULL) {
    11371136      if (nAdded) {
    1138         status |= M860_BD_LAST | M860_BD_TX_CRC;
     1137        status |= M8xx_BD_LAST | M8xx_BD_TX_CRC;
    11391138        txBd->status = status;
    1140         firstTxBd->status |= M860_BD_READY;
    1141         m860.fec.x_des_active = 0x1000000;
     1139        firstTxBd->status |= M8xx_BD_READY;
     1140        m8xx.fec.x_des_active = 0x1000000;
    11421141        sc->txBdActiveCount += nAdded;
    11431142      }
     
    12551254   */
    12561255  if (ifp->if_flags & IFF_PROMISC)
    1257     m860.scc1.psmr |= 0x200;
     1256    m8xx.scc1.psmr |= 0x200;
    12581257  else
    1259     m860.scc1.psmr &= ~0x200;
     1258    m8xx.scc1.psmr &= ~0x200;
    12601259 
    12611260  /*
     
    12671266   * Enable receiver and transmitter
    12681267   */
    1269   m860.scc1.gsmr_l |= 0x30;
     1268  m8xx.scc1.gsmr_l |= 0x30;
    12701269}
    12711270
     
    12951294   */
    12961295  if (ifp->if_flags & IFF_PROMISC)
    1297     m860.fec.r_cntrl |= 0x8;
     1296    m8xx.fec.r_cntrl |= 0x8;
    12981297  else
    1299     m860.fec.r_cntrl &= ~0x8;
     1298    m8xx.fec.r_cntrl &= ~0x8;
    13001299
    13011300 
     
    13081307   * Enable receiver and transmitter
    13091308   */
    1310   m860.fec.ecntrl = 0x2;
     1309  m8xx.fec.ecntrl = 0x2;
    13111310}
    13121311
     
    13251324   * Shut down receiver and transmitter
    13261325   */
    1327   m860.scc1.gsmr_l &= ~0x30;
     1326  m8xx.scc1.gsmr_l &= ~0x30;
    13281327}
    13291328
     
    13381337   * Shut down receiver and transmitter
    13391338   */
    1340   m860.fec.ecntrl = 0x0;
     1339  m8xx.fec.ecntrl = 0x0;
    13411340}
    13421341
     
    13561355  printf ("         Overrun:%-8lu", sc->rxOverrun);
    13571356  printf ("       Collision:%-8lu\n", sc->rxCollision);
    1358   printf ("          Discarded:%-8lu\n", (unsigned long)m860.scc1p.un.ethernet.disfc);
     1357  printf ("          Discarded:%-8lu\n", (unsigned long)m8xx.scc1p.un.ethernet.disfc);
    13591358 
    13601359  printf ("      Tx Interrupts:%-8lu", sc->txInterrupts);
     
    16111610  int i;
    16121611
    1613   if ((m860.fec.mii_data & 0xffff) == 0x2000) {
     1612  if ((m8xx.fec.mii_data & 0xffff) == 0x2000) {
    16141613/*    rtems_scc1_driver_attach(config);*/
    16151614    return rtems_fec_driver_attach(config);
  • c/src/lib/libbsp/powerpc/eth_comm/startup/bspstart.c

    rf481c39c r8ef3818  
    1919
    2020#include <bsp.h>
    21 #include <mpc860.h>
    2221#include <rtems/libio.h>
    2322 
     
    116115  rtems_unsigned32  heap_start;
    117116  rtems_unsigned32  ws_start;
     117
     118  cpu_init();
     119  mmu_init();
     120 
    118121  /*
    119122   *  Allocate the memory for the RTEMS Work Space.  This can come from
     
    167170   * we can attempt to read it later in rtems_enet_driver_attach()
    168171  */
    169   m860.fec.mii_speed = 0x0a;
    170   m860.fec.mii_data = 0x680a0000;
     172  m8xx.fec.mii_speed = 0x0a;
     173  m8xx.fec.mii_data = 0x680a0000;
    171174
    172175
    173   m860.scc2.sccm=0;
    174   m860.scc2p.rbase=0;
    175   m860.scc2p.tbase=0;
    176   M860ExecuteRISC(M860_CR_OP_STOP_TX | M860_CR_CHAN_SCC2);
    177 
    178   mmu_init();
     176  m8xx.scc2.sccm=0;
     177  m8xx.scc2p.rbase=0;
     178  m8xx.scc2p.tbase=0;
     179  m8xx_cp_execute_cmd( M8xx_CR_OP_STOP_TX | M8xx_CR_CHAN_SCC2 );
    179180}
    180181
  • c/src/lib/libbsp/powerpc/eth_comm/startup/linkcmds

    rf481c39c r8ef3818  
    129129        dpram :
    130130        {
    131           m860 = .;
    132           _m860 = .;
     131          m8xx = .;
     132          _m8xx = .;
    133133          . += (8 * 1024);
    134134        } >dpram
  • c/src/lib/libbsp/powerpc/support/old_exception_processing/Makefile.am

    rf481c39c r8ef3818  
    66
    77# C source names
    8 C_FILES = cpu.c ppccache.c
     8C_FILES = cpu.c
    99C_O_FILES = $(C_FILES:%.c=${ARCH}/%.o)
    1010
  • c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu.c

    rf481c39c r8ef3818  
    5151static void ppc_spurious(int, CPU_Interrupt_frame *);
    5252
     53int _CPU_spurious_count = 0;
     54int _CPU_last_spurious = 0;
     55
    5356void _CPU_Initialize(
    5457  rtems_cpu_table  *cpu_table,
     
    370373        }
    371374#endif
     375    ++_CPU_spurious_count;
     376    _CPU_last_spurious = v;
    372377}
    373378
     
    749754      Offset = 0x23c0;
    750755      break;
    751     case PPC_IRQ_CPM_RESERVED_0:
     756    case PPC_IRQ_CPM_ERROR:
    752757      Offset = 0x2400;
    753758      break;
  • c/src/lib/libbsp/powerpc/support/old_exception_processing/cpu.h

    rf481c39c r8ef3818  
    767767  } while (0)
    768768
     769#define _CPU_Data_Cache_Block_Invalidate( _address ) \
     770  do { register void *__address = (_address); \
     771       register unsigned32 _zero = 0; \
     772       asm volatile ( "dcbi %0,%1" : \
     773                      "=r" (_zero), "=r" (__address) : \
     774                      "0" (_zero), "1" (__address) \
     775       ); \
     776  } while (0)
     777
    769778
    770779/*
  • c/src/lib/libc/malloc.c

    rf481c39c r8ef3818  
    419419  free( ptr );
    420420}
    421 #endif
    422 
     421
     422
     423/*
     424 *  rtems_cache_aligned_malloc
     425 *
     426 *  DESCRIPTION:
     427 *
     428 *  This function is used to allocate storage that spans an
     429 *  integral number of cache blocks.
     430 */
     431RTEMS_INLINE_ROUTINE void * rtems_cache_aligned_malloc (
     432  size_t nbytes
     433)
     434{
     435  /*
     436   * Arrange to have the user storage start on the first cache
     437   * block beyond the header.
     438   */
     439  return (void *) ((((unsigned long) malloc( nbytes + _CPU_DATA_CACHE_ALIGNMENT - 1 ))
     440                                                                        + _CPU_DATA_CACHE_ALIGNMENT - 1 ) &(~(_CPU_DATA_CACHE_ALIGNMENT - 1)) );
     441}
     442
     443#endif
     444
  • c/src/lib/libc/termios.c

    rf481c39c r8ef3818  
    2424#include <termios.h>
    2525#include <unistd.h>
     26#include <sys/filio.h>
    2627
    2728/*
     
    244245                 * Set default parameters
    245246                 */
    246                 tty->termios.c_iflag = BRKINT | ICRNL | IMAXBEL;
     247                tty->termios.c_iflag = BRKINT | ICRNL | IXON | IMAXBEL;
    247248                tty->termios.c_oflag = OPOST | ONLCR | XTABS;
    248249                tty->termios.c_cflag = B9600 | CS8 | CREAD | CLOCAL;
     
    474475        case RTEMS_IO_TCDRAIN:
    475476                drainOutput (tty);
     477                break;
     478
     479        case FIONREAD:
     480                /* Half guess that this is the right operation */
     481                *(int *)args->buffer = tty->ccount - tty->cindex;
    476482                break;
    477483        }
  • c/src/lib/libcpu/i386/cpu.h

    rf481c39c r8ef3818  
    131131
    132132  return segment;
    133 }
    134 
    135 /*
    136  * Added for pagination management
    137  */
    138 
    139 static inline unsigned int i386_get_cr0()
    140 {
    141   register unsigned int segment = 0;
    142 
    143   asm volatile ( "movl %%cr0,%0" : "=r" (segment) : "0" (segment) );
    144 
    145   return segment;
    146 }
    147 
    148 static inline void i386_set_cr0(unsigned int segment)
    149 {
    150   asm volatile ( "movl %0,%%cr0" : "=r" (segment) : "0" (segment) );
    151 }
    152 
    153 static inline unsigned int i386_get_cr2()
    154 {
    155   register unsigned int segment = 0;
    156 
    157   asm volatile ( "movl %%cr2,%0" : "=r" (segment) : "0" (segment) );
    158 
    159   return segment;
    160 }
    161 
    162 static inline unsigned int i386_get_cr3()
    163 {
    164   register unsigned int segment = 0;
    165 
    166   asm volatile ( "movl %%cr3,%0" : "=r" (segment) : "0" (segment) );
    167 
    168   return segment;
    169 }
    170 
    171 static inline void i386_set_cr3(unsigned int segment)
    172 {
    173   asm volatile ( "movl %0,%%cr3" : "=r" (segment) : "0" (segment) );
    174133}
    175134
     
    479438  page_table_entry pageTableEntry[MAX_ENTRY];
    480439} page_table;
    481 
    482 static inline void flush_cache()
    483 {
    484   /* Would this be better as a macro? */
    485   asm ("wbinvd");  /* gcc did not like a volatile being on this */
    486 }
    487440
    488441
  • c/src/lib/libcpu/i386/page.c

    rf481c39c r8ef3818  
    4646  cr0 regCr0;
    4747
    48   flush_cache();
     48  rtems_flush_entire_data_cache();
    4949  regCr0.i = i386_get_cr0();
    5050  regCr0.cr0.paging = 0;
     
    6161  regCr0.cr0.paging = 1;
    6262  i386_set_cr0( regCr0.i );
    63   flush_cache();
     63  rtems_flush_entire_data_cache();
    6464}
    6565
     
    152152
    153153  return 0;
    154 }
    155 
    156 /*
    157  * Disable the entire cache
    158  */
    159 void _CPU_disable_cache() {
    160   cr0 regCr0;
    161 
    162   regCr0.i = i386_get_cr0();
    163   regCr0.cr0.page_level_cache_disable = 1;
    164   regCr0.cr0.no_write_through = 1;
    165   i386_set_cr0( regCr0.i );
    166   flush_cache();
    167 }
    168 
    169 /*
    170  * Disable the entire cache
    171  */
    172 void _CPU_enable_cache() {
    173   cr0 regCr0;
    174 
    175   regCr0.i = i386_get_cr0();
    176   regCr0.cr0.page_level_cache_disable = 0;
    177   regCr0.cr0.no_write_through = 0;
    178   i386_set_cr0( regCr0.i );
    179   /*flush_cache();*/
    180154}
    181155
  • c/src/lib/libcpu/powerpc/Makefile.am

    rf481c39c r8ef3818  
    1717CPU_SUBDIR = mpc6xx
    1818endif
    19 if mpc821
    20 CPU_SUBDIR = mpc821
    21 endif
    22 if mpc860
    23 CPU_SUBDIR = mpc860
     19if mpc8xx
     20CPU_SUBDIR = mpc8xx
    2421endif
    2522if ppc403
  • c/src/lib/libcpu/powerpc/configure.in

    rf481c39c r8ef3818  
    2727RTEMS_CHECK_BSP_CACHE(RTEMS_BSP)
    2828
    29 AM_CONDITIONAL(shared,
    30 test "$RTEMS_CPU_MODEL" = "mpc750" \
    31 || test "$RTEMS_CPU_MODEL" = "mpc604" )
     29AM_CONDITIONAL(shared, test "$RTEMS_CPU_MODEL" = "mpc750" \
     30|| test "$RTEMS_CPU_MODEL" = "mpc604" \
     31|| test "$RTEMS_CPU_MODEL" = "mpc6xx" \
     32|| test "$RTEMS_CPU_MODEL" = "mpc821" \
     33|| test "$RTEMS_CPU_MODEL" = "mpc860" \
     34|| test "$RTEMS_CPU_MODEL" = "mpc8xx" )
    3235
    3336AM_CONDITIONAL(mpc505, test "$RTEMS_CPU_MODEL" = "mpc505")
     
    3538|| test "$RTEMS_CPU_MODEL" = "mpc604" \
    3639|| test "$RTEMS_CPU_MODEL" = "mpc750" )
    37 AM_CONDITIONAL(mpc821, test "$RTEMS_CPU_MODEL" = "mpc821")
    38 AM_CONDITIONAL(mpc860, test "$RTEMS_CPU_MODEL" = "mpc860")
     40AM_CONDITIONAL(mpc8xx, test "$RTEMS_CPU_MODEL" = "mpc8xx" \
     41|| test "$RTEMS_CPU_MODEL" = "mpc821" \
     42|| test "$RTEMS_CPU_MODEL" = "mpc860" )
    3943AM_CONDITIONAL(ppc403, test "$RTEMS_CPU_MODEL" = "ppc403")
    4044
     
    4549mpc505/timer/Makefile
    4650mpc505/vectors/Makefile
    47 mpc821/Makefile
    48 mpc821/clock/Makefile
    49 mpc821/console-generic/Makefile
    50 mpc821/include/Makefile
    51 mpc821/timer/Makefile
    52 mpc821/vectors/Makefile
    53 mpc860/Makefile
    54 mpc860/clock/Makefile
    55 mpc860/console-generic/Makefile
    56 mpc860/include/Makefile
    57 mpc860/timer/Makefile
    58 mpc860/vectors/Makefile
     51mpc8xx/Makefile
     52mpc8xx/clock/Makefile
     53mpc8xx/console-generic/Makefile
     54mpc8xx/cpm/Makefile
     55mpc8xx/include/Makefile
     56mpc8xx/mmu/Makefile
     57mpc8xx/timer/Makefile
     58mpc8xx/vectors/Makefile
    5959ppc403/Makefile
    6060ppc403/clock/Makefile
  • c/src/lib/libcpu/powerpc/old-exceptions/cpu.c

    rf481c39c r8ef3818  
    5151static void ppc_spurious(int, CPU_Interrupt_frame *);
    5252
     53int _CPU_spurious_count = 0;
     54int _CPU_last_spurious = 0;
     55
    5356void _CPU_Initialize(
    5457  rtems_cpu_table  *cpu_table,
     
    370373        }
    371374#endif
     375    ++_CPU_spurious_count;
     376    _CPU_last_spurious = v;
    372377}
    373378
     
    749754      Offset = 0x23c0;
    750755      break;
    751     case PPC_IRQ_CPM_RESERVED_0:
     756    case PPC_IRQ_CPM_ERROR:
    752757      Offset = 0x2400;
    753758      break;
  • c/src/lib/libcpu/powerpc/old_exception_processing/Makefile.am

    rf481c39c r8ef3818  
    66
    77# C source names
    8 C_FILES = cpu.c ppccache.c
     8C_FILES = cpu.c
    99C_O_FILES = $(C_FILES:%.c=${ARCH}/%.o)
    1010
  • c/src/lib/libcpu/powerpc/old_exception_processing/cpu.c

    rf481c39c r8ef3818  
    5151static void ppc_spurious(int, CPU_Interrupt_frame *);
    5252
     53int _CPU_spurious_count = 0;
     54int _CPU_last_spurious = 0;
     55
    5356void _CPU_Initialize(
    5457  rtems_cpu_table  *cpu_table,
     
    370373        }
    371374#endif
     375    ++_CPU_spurious_count;
     376    _CPU_last_spurious = v;
    372377}
    373378
     
    749754      Offset = 0x23c0;
    750755      break;
    751     case PPC_IRQ_CPM_RESERVED_0:
     756    case PPC_IRQ_CPM_ERROR:
    752757      Offset = 0x2400;
    753758      break;
  • c/src/lib/libcpu/powerpc/old_exception_processing/cpu.h

    rf481c39c r8ef3818  
    767767  } while (0)
    768768
     769#define _CPU_Data_Cache_Block_Invalidate( _address ) \
     770  do { register void *__address = (_address); \
     771       register unsigned32 _zero = 0; \
     772       asm volatile ( "dcbi %0,%1" : \
     773                      "=r" (_zero), "=r" (__address) : \
     774                      "0" (_zero), "1" (__address) \
     775       ); \
     776  } while (0)
     777
    769778
    770779/*
  • c/src/lib/libcpu/powerpc/shared/cpu.h

    rf481c39c r8ef3818  
    22 * cpu.h
    33 *
    4  *          This file contains some powerpc MSR and registers access definitions.
     4 * This file contains some powerpc MSR and registers access definitions.
    55 *
    66 * It is a stripped down version of linux ppc processor.h file...
     
    1616 */
    1717
    18 #ifndef __ASM_PPC_PROCESSOR_H
    19 #define __ASM_PPC_PROCESSOR_H
    20 
    21 #include <bsp/residual.h>
     18#ifndef __PPC_CPU_H
     19#define __PPC_CPU_H
     20
     21#ifdef __cplusplus
     22extern "C" {
     23#endif
    2224
    2325/* Bit encodings for Machine State Register (MSR) */
     
    248250
    249251
    250 #define _CPU_Data_Cache_Block_Flush( _address ) \
    251   do { register void *__address = (_address); \
    252        register unsigned32 _zero = 0; \
    253        asm volatile ( "dcbf %0,%1" : \
    254                       "=r" (_zero), "=r" (__address) : \
    255                       "0" (_zero), "1" (__address) \
    256        ); \
    257   } while (0)
    258 
    259 
    260252/*
    261253 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
     
    326318  } while (0)
    327319
    328 #endif /* __ASM_PPC_PROCESSOR_H */
    329 
    330 
    331 
    332 
    333 
    334 
    335 
     320
     321#ifdef __cplusplus
     322}
     323#endif
     324
     325#endif /* __PPC_CPU_H */
     326
     327
     328
     329
     330
     331
     332
  • c/src/make/compilers/gcc-target-default.cfg

    rf481c39c r8ef3818  
    8989# debug flag;
    9090CFLAGS_DEBUG_V+=-Wno-unused
     91CXXFLAGS_DEBUG_V+=
    9192
    9293ifeq ($(RTEMS_USE_GCC272),no)
    9394CFLAGS_DEBUG_V+=-qrtems_debug
    94 endif
     95CXXFLAGS_DEBUG_V+=-qrtems_debug
     96endif
     97
     98# when debugging, optimize flag: typically empty
     99# some compilers do allow optimization with their "-g"
     100CFLAGS_DEBUG_OPTIMIZE_V=-g
     101CXXFLAGS_DEBUG_OPTIMIZE_V=-g
    95102
    96103# profile flag; use gprof(1)
    97104CFLAGS_PROFILE_V=-pg
     105CXXFLAGS_PROFILE_V=-pg
    98106
    99107ifndef AUTOMAKE
    100108# default is to optimize
    101 CFLAGS_OPTIMIZE=$(CFLAGS_OPTIMIZE_V)
     109CFLAGS_OPTIMIZE  =$(CFLAGS_OPTIMIZE_V)
     110CXXFLAGS_OPTIMIZE=$(CXXFLAGS_OPTIMIZE_V)
    102111endif
    103112
     
    107116
    108117ifndef AUTOMAKE
    109 CFLAGS += $(CFLAGS_OPTIMIZE) $(CFLAGS_DEBUG) $(CFLAGS_PROFILE)
     118CFLAGS   += $(CFLAGS_OPTIMIZE) $(CFLAGS_DEBUG) $(CFLAGS_PROFILE)
     119CXXFLAGS += $(CXXFLAGS_OPTIMIZE) $(CXXFLAGS_DEBUG) $(CXXFLAGS_PROFILE)
    110120endif
    111121
  • c/src/tests/configure.in

    rf481c39c r8ef3818  
    6868AC_CONFIG_SUBDIRS(support)
    6969AC_CONFIG_SUBDIRS(samples)
     70AC_CONFIG_SUBDIRS(libffi)
    7071AC_CONFIG_SUBDIRS($cfg_subdirs)
    7172
  • c/src/tests/libtests/termios/init.c

    rf481c39c r8ef3818  
    2424
    2525#include <bsp.h>
     26
    2627
    2728#define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
     
    588589void canonical_input( struct termios *tp )
    589590{
     591    char buffer[256];
    590592    char c, first_time = TRUE;
    591593   
     
    612614  printf( "\n\nCanonical input test done.\n" );
    613615}
     616
    614617
    615618/*
     
    708711Init (rtems_task_argument ignored)
    709712{
    710   char c;
     713  char c, done;
    711714  struct termios orig_termios, test_termios;
    712715 
  • c/src/tests/samples/cdtest/system.h

    rf481c39c r8ef3818  
    3535#define CONFIGURE_INIT_TASK_NAME          rtems_build_name( 'C', 'T', 'O', 'R' )
    3636
     37/* Guess at this one */
     38#define CONFIGURE_MAXIMUM_POSIX_MUTEXES 2
     39
    3740#include <confdefs.h>
    3841
  • c/src/tests/sptests/Makefile.am

    rf481c39c r8ef3818  
    99SUBDIRS = sp01 sp02 sp03 sp04 sp05 sp06 sp07 sp08 sp09 sp11 sp12 sp13 sp14 \
    1010    sp15 sp16 sp17 sp19 sp20 sp21 sp22 sp23 sp24 sp25 sp26 sp27 sp28 sp29 \
    11     spsize
     11    spsize threaditerate
    1212
    1313EXTRA_DIST = sptests.am spfatal
  • c/src/tests/sptests/configure.in

    rf481c39c r8ef3818  
    6868sp29/Makefile
    6969spsize/Makefile
     70threaditerate/Makefile
    7071)
    7172
  • cpukit/libcsupport/include/sys/termios.h

    rf481c39c r8ef3818  
    182182int     tcgetattr(int, struct termios *);
    183183int     tcsetattr(int, int, struct termios *);
     184int     tcdrain(int);
    184185pid_t   tcgetprgrp(int);
    185186int     tcsetprgrp(int, pid_t);
  • cpukit/libcsupport/src/malloc.c

    rf481c39c r8ef3818  
    419419  free( ptr );
    420420}
    421 #endif
    422 
     421
     422
     423/*
     424 *  rtems_cache_aligned_malloc
     425 *
     426 *  DESCRIPTION:
     427 *
     428 *  This function is used to allocate storage that spans an
     429 *  integral number of cache blocks.
     430 */
     431RTEMS_INLINE_ROUTINE void * rtems_cache_aligned_malloc (
     432  size_t nbytes
     433)
     434{
     435  /*
     436   * Arrange to have the user storage start on the first cache
     437   * block beyond the header.
     438   */
     439  return (void *) ((((unsigned long) malloc( nbytes + _CPU_DATA_CACHE_ALIGNMENT - 1 ))
     440                                                                        + _CPU_DATA_CACHE_ALIGNMENT - 1 ) &(~(_CPU_DATA_CACHE_ALIGNMENT - 1)) );
     441}
     442
     443#endif
     444
  • cpukit/libcsupport/src/termios.c

    rf481c39c r8ef3818  
    2424#include <termios.h>
    2525#include <unistd.h>
     26#include <sys/filio.h>
    2627
    2728/*
     
    244245                 * Set default parameters
    245246                 */
    246                 tty->termios.c_iflag = BRKINT | ICRNL | IMAXBEL;
     247                tty->termios.c_iflag = BRKINT | ICRNL | IXON | IMAXBEL;
    247248                tty->termios.c_oflag = OPOST | ONLCR | XTABS;
    248249                tty->termios.c_cflag = B9600 | CS8 | CREAD | CLOCAL;
     
    474475        case RTEMS_IO_TCDRAIN:
    475476                drainOutput (tty);
     477                break;
     478
     479        case FIONREAD:
     480                /* Half guess that this is the right operation */
     481                *(int *)args->buffer = tty->ccount - tty->cindex;
    476482                break;
    477483        }
  • cpukit/posix/src/waitpid.c

    rf481c39c r8ef3818  
    11/*
    2  *  wait() - POSIX 1003.1b 3.2.1
     2 *  waitpid() - POSIX 1003.1 3.2.1
    33 *
    44 *  $Id$
  • cpukit/rtems/src/Makefile.am

    rf481c39c r8ef3818  
    5151    dpmemident.c dpmeminternal2external.c
    5252
    53 STD_C_FILES = attr.c $(TASK_C_FILES) $(RATEMON_C_FILES) $(INTR_C_FILES) \
     53STD_C_FILES = attr.c cache.c $(TASK_C_FILES) $(RATEMON_C_FILES) $(INTR_C_FILES) \
    5454    $(CLOCK_C_FILES) $(TIMER_C_FILES) $(SEMAPHORE_C_FILES) \
    5555    $(MESSAGE_QUEUE_C_FILES) $(EVENT_C_FILES) $(SIGNAL_C_FILES) \
  • cpukit/score/cpu/i386/rtems/score/i386.h

    rf481c39c r8ef3818  
    145145
    146146
     147/*
     148 * Added for pagination management
     149 */
     150 
     151static inline unsigned int i386_get_cr0()
     152{
     153  register unsigned int segment = 0;
     154
     155  asm volatile ( "movl %%cr0,%0" : "=r" (segment) : "0" (segment) );
     156
     157  return segment;
     158}
     159
     160static inline void i386_set_cr0(unsigned int segment)
     161{
     162  asm volatile ( "movl %0,%%cr0" : "=r" (segment) : "0" (segment) );
     163}
     164
     165static inline unsigned int i386_get_cr2()
     166{
     167  register unsigned int segment = 0;
     168
     169  asm volatile ( "movl %%cr2,%0" : "=r" (segment) : "0" (segment) );
     170
     171  return segment;
     172}
     173
     174static inline unsigned int i386_get_cr3()
     175{
     176  register unsigned int segment = 0;
     177
     178  asm volatile ( "movl %%cr3,%0" : "=r" (segment) : "0" (segment) );
     179
     180  return segment;
     181}
     182
     183static inline void i386_set_cr3(unsigned int segment)
     184{
     185  asm volatile ( "movl %0,%%cr3" : "=r" (segment) : "0" (segment) );
     186}
     187
     188/*
     189 * Disable the entire cache
     190 */
     191void _CPU_disable_cache() {
     192  cr0 regCr0;
     193
     194  regCr0.i = i386_get_cr0();
     195  regCr0.cr0.page_level_cache_disable = 1;
     196  regCr0.cr0.no_write_through = 1;
     197  i386_set_cr0( regCr0.i );
     198  rtems_flush_entire_data_cache();
     199}
     200
     201/*
     202 * Enable the entire cache
     203 */
     204static inline void _CPU_enable_cache() {
     205  cr0 regCr0;
     206
     207  regCr0.i = i386_get_cr0();
     208  regCr0.cr0.page_level_cache_disable = 0;
     209  regCr0.cr0.no_write_through = 0;
     210  i386_set_cr0( regCr0.i );
     211  /*rtems_flush_entire_data_cache();*/
     212}
     213
     214/*
     215 * CACHE MANAGER: The following functions are CPU-specific.
     216 * They provide the basic implementation for the rtems_* cache
     217 * management routines. If a given function has no meaning for the CPU,
     218 * it does nothing by default.
     219 *
     220 * FIXME: Definitions for I386_CACHE_ALIGNMENT are missing above for
     221 *        each CPU. The routines below should be implemented per CPU,
     222 *        to accomodate the capabilities of each.
     223 */
     224
     225/* FIXME: I don't belong here. */
     226#define I386_CACHE_ALIGNMENT 16
     227
     228#if defined(I386_CACHE_ALIGNMENT)
     229#define _CPU_DATA_CACHE_ALIGNMENT I386_CACHE_ALIGNMENT
     230#define _CPU_INST_CACHE_ALIGNEMNT I386_CACHE_ALIGNMENT
     231
     232static inline void _CPU_flush_1_data_cache_line (const void * d_addr) {}
     233static inline void _CPU_invalidate_1_data_cache_line (const void * d_addr) {}
     234static inline void _CPU_freeze_data_cache (void) {}
     235static inline void _CPU_unfreeze_data_cache (void) {}
     236static inline void _CPU_invalidate_1_inst_cache_line const void * d_addr() {}
     237static inline void _CPU_freeze_inst_cache (void) {}
     238static inline void _CPU_unfreeze_inst_cache (void) {}
     239
     240static inline void _CPU_flush_entire_data_cache (
     241  const void * d_addr )
     242{
     243  asm ("wbinvd");
     244}
     245static inline void _CPU_invalidate_entire_data_cache (
     246  const void * d_addr )
     247{
     248  asm ("invd");
     249}
     250
     251static inline void _CPU_enable_data_cache (
     252        void )
     253{
     254        _CPU_enable_cache();
     255}
     256
     257static inline void _CPU_disable_data_cache (
     258        void )
     259{
     260        _CPU_disable_cache();
     261}
     262
     263static inline void _CPU_invalidate_entire_inst_cache (
     264  const void * i_addr )
     265{
     266  asm ("invd");
     267}
     268
     269static inline void _CPU_enable_inst_cache (
     270        void )
     271{
     272        _CPU_enable_cache();
     273}
     274
     275static inline void _CPU_disable_inst_cache (
     276        void )
     277{
     278        _CPU_disable_cache();
     279}
     280#endif
     281
     282
    147283/* routines */
    148284
  • cpukit/score/cpu/m68k/rtems/score/m68k.h

    rf481c39c r8ef3818  
    158158 
    159159#elif defined(__mc68302__)
     160
    160161#define CPU_MODEL_NAME          "m68302"
    161162#define M68K_HAS_VBR             0
     
    351352}
    352353
    353 /* XXX this is only valid for some m68k family members and should be fixed */
    354 
    355 #define m68k_enable_caching() \
    356   { register unsigned32 _ctl=0x01; \
    357     asm volatile ( "movec   %0,%%cacr" \
    358                        : "=d" (_ctl) : "0" (_ctl) ); \
    359   }
    360 
    361354#define CPU_swap_u32( value )  m68k_swap_u32( value )
    362355#define CPU_swap_u16( value )  m68k_swap_u16( value )
    363356
     357
     358/*
     359 *  _CPU_virtual_to_physical
     360 *
     361 *  DESCRIPTION:
     362 *
     363 *      This function is used to map virtual addresses to physical
     364 *      addresses.
     365 *
     366 *      FIXME: ASSUMES THAT VIRTUAL ADDRESSES ARE THE SAME AS THE
     367 *      PHYSICAL ADDRESSES
     368 */
     369static inline void * _CPU_virtual_to_physical (
     370  const void * d_addr )
     371{
     372  return (void *) d_addr;
     373}
     374
     375
     376/* 
     377 *  Since the cacr is common to all mc680x0, provide macros
     378 *  for masking values in that register.
     379 */
     380
     381/*
     382 *  Used to clear bits in the cacr.
     383 */
     384#define _CPU_CACR_AND(mask)                                        \
     385  {                                                                \
     386  register unsigned long _value = mask;                            \
     387  register unsigned long _ctl = 0;                                 \
     388  asm volatile ( "movec %%cacr, %0;           /* read the cacr */  \
     389                  andl %2, %0;                /* and with _val */  \
     390                  movec %1, %%cacr"           /* write the cacr */ \
     391   : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" );            \
     392  }
     393
     394
     395/* 
     396 *  Used to set bits in the cacr.
     397 */
     398#define _CPU_CACR_OR(mask)                                         \
     399        {                                                                \
     400  register unsigned long _value = mask;                            \
     401  register unsigned long _ctl = 0;                                 \
     402  asm volatile ( "movec %%cacr, %0;           /* read the cacr */  \
     403                  orl %2, %0;                 /* or with _val */   \
     404                  movec %1, %%cacr"           /* write the cacr */ \
     405   : "=d" (_ctl) : "0" (_ctl), "d" (_value) : "%%cc" );            \
     406  }
     407
     408   
     409/*
     410 * CACHE MANAGER: The following functions are CPU-specific.
     411 * They provide the basic implementation for the rtems_* cache
     412 * management routines. If a given function has no meaning for the CPU,
     413 * it does nothing by default.
     414 */
     415#if ( defined(__mc68020__) || defined(__mc68030__) )
     416#define M68K_INST_CACHE_ALIGNMENT 16
     417
     418#if defined(__mc68030__)
     419#define M68K_DATA_CACHE_ALIGNMENT 16
     420
     421/* Only the mc68030 has a data cache; it is writethrough only. */
     422
     423static inline void _CPU_flush_1_data_cache_line ( const void * d_addr ) {}
     424static inline void _CPU_flush_entire_data_cache ( const void * d_addr ) {}
     425
     426static inline void _CPU_invalidate_1_data_cache_line (
     427  const void * d_addr )
     428{
     429  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
     430  asm volatile ( "movec %0, %%caar" :: "a" (p_address) );      /* write caar */
     431  _CPU_CACR_OR(0x00000400);
     432}
     433
     434static inline void _CPU_invalidate_entire_data_cache (
     435        void )
     436{
     437  _CPU_CACR_OR( 0x00000800 );
     438}
     439
     440static inline void _CPU_freeze_data_cache (
     441        void )
     442{
     443  _CPU_CACR_OR( 0x00000200 );
     444}
     445
     446static inline void _CPU_unfreeze_data_cache (
     447        void )
     448{
     449  _CPU_CACR_AND( 0xFFFFFDFF );
     450}
     451
     452static inline void _CPU_enable_data_cache (     void )
     453{
     454  _CPU_CACR_OR( 0x00000100 );
     455}
     456static inline void _CPU_disable_data_cache (    void )
     457{
     458  _CPU_CACR_AND( 0xFFFFFEFF );
     459}
     460#endif
     461
     462
     463/* Both the 68020 and 68030 have instruction caches */
     464
     465static inline void _CPU_invalidate_1_inst_cache_line (
     466  const void * d_addr )
     467{
     468  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
     469  asm volatile ( "movec %0, %%caar" :: "a" (p_address) );      /* write caar */
     470  _CPU_CACR_OR( 0x00000004 );
     471}
     472
     473static inline void _CPU_invalidate_entire_inst_cache (
     474        void )
     475{
     476  _CPU_CACR_OR( 0x00000008 );
     477}
     478
     479static inline void _CPU_freeze_inst_cache (
     480        void )
     481{
     482  _CPU_CACR_OR( 0x00000002);
     483}
     484
     485static inline void _CPU_unfreeze_inst_cache (
     486        void )
     487{
     488  _CPU_CACR_AND( 0xFFFFFFFD );
     489}
     490
     491static inline void _CPU_enable_inst_cache (     void )
     492{
     493  _CPU_CACR_OR( 0x00000001 );
     494}
     495
     496static inline void _CPU_disable_inst_cache (    void )
     497{
     498  _CPU_CACR_AND( 0xFFFFFFFE );
     499}
     500
     501
     502#elif ( defined(__mc68040__) || defined (__mc68060__) )
     503
     504#define M68K_INST_CACHE_ALIGNMENT 16
     505#define M68K_DATA_CACHE_ALIGNMENT 16
     506
     507/* Cannot be frozen */
     508static inline void _CPU_freeze_data_cache ( void ) {}
     509static inline void _CPU_unfreeze_data_cache ( void ) {}
     510static inline void _CPU_freeze_inst_cache ( void ) {}
     511static inline void _CPU_unfreeze_inst_cache ( void ) {}
     512
     513static inline void _CPU_flush_1_data_cache_line (
     514  const void * d_addr )
     515{
     516  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
     517  asm volatile ( "cpushl %%dc,(%0)" :: "a" (p_address) );
     518}
     519
     520static inline void _CPU_invalidate_1_data_cache_line (
     521  const void * d_addr )
     522{
     523  void * p_address = (void *) _CPU_virtual_to_physical( d_addr );
     524  asm volatile ( "cinvl %%dc,(%0)" :: "a" (p_address) );
     525}
     526
     527static inline void _CPU_flush_entire_data_cache (
     528        void )
     529{
     530        asm volatile ( "cpusha %%dc" :: );
     531}
     532
     533static inline void _CPU_invalidate_entire_data_cache (
     534        void )
     535{
     536        asm volatile ( "cinva %%dc" :: );
     537}
     538
     539static inline void _CPU_enable_data_cache (
     540        void )
     541{
     542  _CPU_CACR_OR( 0x80000000 );
     543}
     544
     545static inline void _CPU_disable_data_cache (
     546        void )
     547{
     548  _CPU_CACR_AND( 0x7FFFFFFF );
     549}
     550
     551static inline void _CPU_invalidate_1_inst_cache_line (
     552  const void * i_addr )
     553{
     554  void * p_address = (void *)  _CPU_virtual_to_physical( i_addr );
     555  asm volatile ( "cinvl %%ic,(%0)" :: "a" (p_address) );
     556}
     557
     558static inline void _CPU_invalidate_entire_inst_cache (
     559        void )
     560{
     561                asm volatile ( "cinva %%ic" :: );
     562}
     563
     564static inline void _CPU_enable_inst_cache (
     565        void )
     566{
     567  _CPU_CACR_OR( 0x00008000 );
     568}
     569
     570static inline void _CPU_disable_inst_cache (
     571        void )
     572{
     573        _CPU_CACR_AND( 0xFFFF7FFF );
     574}
     575#endif
     576
     577
     578#if defined(M68K_DATA_CACHE_ALIGNMENT)
     579#define _CPU_DATA_CACHE_ALIGNMENT M68K_DATA_CACHE_ALIGNMENT
     580#endif
     581
     582#if defined(M68K_INST_CACHE_ALIGNMENT)
     583#define _CPU_INST_CACHE_ALIGNMENT M68K_INST_CACHE_ALIGNMENT
     584#endif
     585
     586
    364587#endif  /* !ASM */
    365588
     
    368591#endif
    369592
    370 #endif
     593#endif /* __M68K_h */
    371594/* end of include file */
  • cpukit/score/cpu/powerpc/asm.h

    rf481c39c r8ef3818  
    165165#define srr0    0x01a
    166166#define srr1    0x01b
     167#ifdef ppc403
    167168#define srr2    0x3de   /* IBM 400 series only */
    168169#define srr3    0x3df   /* IBM 400 series only */
     170#endif /* ppc403 */
     171
    169172#define sprg0   0x110
    170173#define sprg1   0x111
     
    172175#define sprg3   0x113
    173176
    174 
     177#define dar     0x013   /* Data Address Register */
     178#define dec             0x016   /* Decrementer Register */
     179
     180#if defined(ppc403)
    175181/* the following SPR/DCR registers exist only in IBM 400 series */
    176182#define dear    0x3d5   
     
    191197/* end of IBM400 series register definitions */
    192198
     199#elif defined(mpc860) || defined(mpc821)
    193200/* The following registers are for the MPC8x0 */
    194201#define der     0x095   /* Debug Enable Register */
     202#define ictrl   0x09E   /* Instruction Support Control Register */
     203#define immr    0x27E   /* Internal Memory Map Register */
    195204/* end of MPC8x0 registers */
     205#endif
    196206
    197207/*
  • cpukit/score/cpu/powerpc/rtems/asm.h

    rf481c39c r8ef3818  
    165165#define srr0    0x01a
    166166#define srr1    0x01b
     167#ifdef ppc403
    167168#define srr2    0x3de   /* IBM 400 series only */
    168169#define srr3    0x3df   /* IBM 400 series only */
     170#endif /* ppc403 */
     171
    169172#define sprg0   0x110
    170173#define sprg1   0x111
     
    172175#define sprg3   0x113
    173176
    174 
     177#define dar     0x013   /* Data Address Register */
     178#define dec             0x016   /* Decrementer Register */
     179
     180#if defined(ppc403)
    175181/* the following SPR/DCR registers exist only in IBM 400 series */
    176182#define dear    0x3d5   
     
    191197/* end of IBM400 series register definitions */
    192198
     199#elif defined(mpc860) || defined(mpc821)
    193200/* The following registers are for the MPC8x0 */
    194201#define der     0x095   /* Debug Enable Register */
     202#define ictrl   0x09E   /* Instruction Support Control Register */
     203#define immr    0x27E   /* Internal Memory Map Register */
    195204/* end of MPC8x0 registers */
     205#endif
    196206
    197207/*
  • cpukit/score/cpu/powerpc/rtems/score/ppc.h

    rf481c39c r8ef3818  
    4444extern "C" {
    4545#endif
     46
     47#include <rtems/score/ppctypes.h>
    4648
    4749/*
     
    221223/*
    222224 *  Added by Jay Monkman (jmonkman@frasca.com) 6/28/98
     225 *  with some changes by Darlene Stewart (Darlene.Stewart@iit.nrc.ca)
    223226 */
    224227#define CPU_MODEL_NAME  "PowerPC MPC860"
     
    232235#define PPC_HAS_DOUBLE          0
    233236#define PPC_USE_MULTIPLE        1
    234 #define PPC_USE_SPRG            1
    235237
    236238#define PPC_MSR_0               0x00009000
     
    382384#error "Undefined power of 2 for PPC_CACHE_ALIGNMENT"
    383385#endif
     386
     387#ifndef ASM
     388
     389/*
     390 * CACHE MANAGER: The following functions are CPU-specific.
     391 * They provide the basic implementation for the rtems_* cache
     392 * management routines. If a given function has no meaning for the CPU,
     393 * it does nothing by default.
     394 *
     395 * FIXME: Some functions simply have not been implemented.
     396 */
     397 
     398#if defined(ppc603)                     /* And possibly others */
     399#define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
     400#define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
     401
     402/* Helpful macros */
     403#define PPC_Get_HID0( _value ) \
     404  do { \
     405      _value = 0;        /* to avoid warnings */ \
     406      asm volatile( \
     407          "mfspr %0, 0x3f0;"     /* get HID0 */ \
     408          "isync" \
     409          : "=r" (_value) \
     410          : "0" (_value) \
     411      ); \
     412  } while (0)
     413
     414#define PPC_Set_HID0( _value ) \
     415  do { \
     416      asm volatile( \
     417          "isync;" \
     418          "mtspr 0x3f0, %0;"     /* load HID0 */ \
     419          "isync" \
     420          : "=r" (_value) \
     421          : "0" (_value) \
     422      ); \
     423  } while (0)
     424
     425static inline void _CPU_enable_data_cache (
     426        void )
     427{
     428  unsigned32 value;
     429  PPC_Get_HID0( value );
     430  value |= 0x00004000;        /* set DCE bit */
     431  PPC_Set_HID0( value );
     432}
     433
     434static inline void _CPU_disable_data_cache (
     435        void )
     436{
     437  unsigned32 value;
     438  PPC_Get_HID0( value );
     439  value &= 0xFFFFBFFF;        /* clear DCE bit */
     440  PPC_Set_HID0( value );
     441}
     442
     443static inline void _CPU_enable_inst_cache (
     444        void )
     445{
     446  unsigned32 value;
     447  PPC_Get_HID0( value );
     448  value |= 0x00008000;       /* Set ICE bit */
     449  PPC_Set_HID0( value );
     450}
     451
     452static inline void _CPU_disable_inst_cache (
     453        void )
     454{
     455  unsigned32 value;
     456  PPC_Get_HID0( value );
     457  value &= 0xFFFF7FFF;       /* Clear ICE bit */
     458  PPC_Set_HID0( value );
     459}
     460
     461#elif ( defined(mpc860) || defined(mpc821) )
     462
     463#define _CPU_DATA_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
     464#define _CPU_INST_CACHE_ALIGNMENT PPC_CACHE_ALIGNMENT
     465
     466#define mtspr(_spr,_reg)   __asm__ volatile ( "mtspr %0, %1\n" : : "i" ((_spr)), "r" ((_reg)) )
     467#define isync   __asm__ volatile ("isync\n"::)
     468
     469static inline void _CPU_flush_1_data_cache_line(
     470        const void * _address )
     471{
     472  register const void *__address = _address;
     473  asm volatile ( "dcbf 0,%0" :: "r" (__address) );
     474}
     475
     476static inline void _CPU_invalidate_1_data_cache_line(
     477        const void * _address )
     478{
     479  register const void *__address = _address;
     480  asm volatile ( "dcbi 0,%0" :: "r" (__address) );
     481}
     482
     483static inline void _CPU_flush_entire_data_cache ( void ) {}
     484static inline void _CPU_invalidate_entire_data_cache ( void ) {}
     485static inline void _CPU_freeze_data_cache ( void ) {}
     486static inline void _CPU_unfreeze_data_cache ( void ) {}
     487
     488static inline void _CPU_enable_data_cache (
     489        void )
     490{
     491  unsigned32 r1;
     492  r1 = (0x2<<24);
     493  mtspr( 568, r1 );
     494  isync;
     495}
     496
     497static inline void _CPU_disable_data_cache (
     498        void )
     499{
     500  unsigned32 r1;
     501  r1 = (0x4<<24);
     502  mtspr( 568, r1 );
     503  isync;
     504}
     505
     506static inline void _CPU_invalidate_1_inst_cache_line(
     507        const void * _address )
     508{
     509  register const void *__address = _address;
     510  asm volatile ( "icbi 0,%0" :: "r" (__address) );
     511}
     512
     513static inline void _CPU_invalidate_entire_inst_cache ( void ) {}
     514static inline void _CPU_freeze_inst_cache ( void ) {}
     515static inline void _CPU_unfreeze_inst_cache ( void ) {}
     516
     517static inline void _CPU_enable_inst_cache (
     518        void )
     519{
     520  unsigned32 r1;
     521  r1 = (0x2<<24);
     522  mtspr( 560, r1 );
     523  isync;
     524}
     525
     526static inline void _CPU_disable_inst_cache (
     527        void )
     528{
     529  unsigned32 r1;
     530  r1 = (0x4<<24);
     531  mtspr( 560, r1 );
     532  isync;
     533}
     534#endif
     535
     536#endif  /* !ASM */
    384537
    385538/*
     
    551704#define PPC_IRQ_IRQ7            (PPC_STD_IRQ_LAST + 24)
    552705#define PPC_IRQ_LVL7            (PPC_STD_IRQ_LAST + 25)
    553 #define PPC_IRQ_CPM_RESERVED_0  (PPC_STD_IRQ_LAST + 26)
     706#define PPC_IRQ_CPM_ERROR       (PPC_STD_IRQ_LAST + 26)
    554707#define PPC_IRQ_CPM_PC4         (PPC_STD_IRQ_LAST + 27)
    555708#define PPC_IRQ_CPM_PC5         (PPC_STD_IRQ_LAST + 28)
  • cpukit/score/include/rtems/score/object.h

    rf481c39c r8ef3818  
    445445
    446446/*
     447 * _Objects_Get_by_index
     448 *
     449 *  DESCRIPTION:
     450 *
     451 * This routine sets the object pointer for the given
     452 * object id based on the given object information structure.
     453 */
     454
     455Objects_Control *_Objects_Get_by_index(
     456  Objects_Information *information,
     457  unsigned32           index,
     458  Objects_Locations   *location
     459);
     460
     461/*
    447462 *  _Objects_Get_next
    448463 *
     
    461476
    462477/*
     478 *  _Objects_Local_iterate
     479 *
     480 *  DESCRIPTION:
     481 *
     482 *  This function invokes the callback function for each existing object
     483 *  of the type specified by the information block pointer. Iteration
     484 *  continues until either all objects have been processed, or, if
     485 *  break_on_error is TRUE, until an invocation of the callback returns
     486 *  something other than 0.
     487 */
     488
     489unsigned32 _Objects_Local_iterate(
     490  Objects_Information *information,
     491  unsigned32 (*callback)(Objects_Control *object, void * arg),
     492  void * arg,
     493  boolean break_on_error
     494);
     495
     496/*
    463497 *  Pieces of object.inl are promoted out to the user
    464498 */
  • cpukit/score/include/rtems/score/thread.h

    rf481c39c r8ef3818  
    735735
    736736/*
     737 *  _Thread_Local_iterate
     738 *
     739 *  DESCRIPTION:
     740 *
     741 *  This function invokes the callback function for each existing thread.
     742 *  Iteration continues until either all threads have been processed, or,
     743 *  if break_on_error is TRUE, until an invocation of the callback returns
     744 *  an integer value other than 0.
     745 */
     746
     747unsigned32 _Thread_Local_iterate(
     748  unsigned32 (*callback)(Thread_Control *the_thread, void * arg),
     749  void * arg,
     750  boolean break_on_error
     751);
     752
     753/*
    737754 *  _Thread_Idle_body
    738755 *
  • cpukit/score/src/Makefile.am

    rf481c39c r8ef3818  
    2828    objectcopynameraw.c objectcopynamestring.c objectextendinformation.c \
    2929    objectfree.c objectget.c objectgetbyindex.c objectgetnext.c \
    30     objectinitializeinformation.c objectnametoid.c objectshrinkinformation.c
     30    objectinitializeinformation.c objectlocaliterate.c objectnametoid.c \
     31    objectshrinkinformation.c
    3132
    3233THREAD_C_FILES = thread.c threadchangepriority.c threadclearstate.c \
    3334    threadclose.c threadcreateidle.c threaddelayended.c threaddispatch.c \
    3435    threadevaluatemode.c threadget.c threadhandler.c threadidlebody.c \
    35     threadinitialize.c threadloadenv.c threadready.c threadresettimeslice.c \
    36     threadreset.c threadrestart.c threadresume.c threadrotatequeue.c \
    37     threadsetpriority.c threadsetstate.c threadsettransient.c \
    38     threadstackallocate.c threadstackfree.c threadstart.c \
    39     threadstartmultitasking.c threadsuspend.c threadtickletimeslice.c \
    40     threadyieldprocessor.c
     36    threadinitialize.c threadloadenv.c threadlocaliterate.c threadready.c \
     37    threadresettimeslice.c threadreset.c threadrestart.c threadresume.c \
     38    threadrotatequeue.c threadsetpriority.c threadsetstate.c \
     39    threadsettransient.c threadstackallocate.c threadstackfree.c \
     40    threadstart.c threadstartmultitasking.c threadsuspend.c \
     41    threadtickletimeslice.c threadyieldprocessor.c
    4142
    4243THREADQ_C_FILES = threadq.c threadqdequeue.c threadqdequeuefifo.c \
     
    5455
    5556STD_C_FILES = apiext.c chain.c $(CORE_MESSAGE_QUEUE_C_FILES) \
    56     $(CORE_MUTEX_C_FILES) $(CORE_SEMAPHORE_C_FILES) $(HEAP_C_FILES) interr.c \
    57     isr.c $(OBJECT_C_FILES) $(THREAD_C_FILES) $(THREADQ_C_FILES) \
     57    $(CORE_MUTEX_C_FILES) $(CORE_SEMAPHORE_C_FILES) $(HEAP_C_FILES) \
     58    interr.c isr.c $(OBJECT_C_FILES) $(THREAD_C_FILES) $(THREADQ_C_FILES) \
    5859    $(TOD_C_FILES) userext.c $(WATCHDOG_C_FILES) wkspace.c
    5960
  • make/compilers/gcc-target-default.cfg

    rf481c39c r8ef3818  
    8989# debug flag;
    9090CFLAGS_DEBUG_V+=-Wno-unused
     91CXXFLAGS_DEBUG_V+=
    9192
    9293ifeq ($(RTEMS_USE_GCC272),no)
    9394CFLAGS_DEBUG_V+=-qrtems_debug
    94 endif
     95CXXFLAGS_DEBUG_V+=-qrtems_debug
     96endif
     97
     98# when debugging, optimize flag: typically empty
     99# some compilers do allow optimization with their "-g"
     100CFLAGS_DEBUG_OPTIMIZE_V=-g
     101CXXFLAGS_DEBUG_OPTIMIZE_V=-g
    95102
    96103# profile flag; use gprof(1)
    97104CFLAGS_PROFILE_V=-pg
     105CXXFLAGS_PROFILE_V=-pg
    98106
    99107ifndef AUTOMAKE
    100108# default is to optimize
    101 CFLAGS_OPTIMIZE=$(CFLAGS_OPTIMIZE_V)
     109CFLAGS_OPTIMIZE  =$(CFLAGS_OPTIMIZE_V)
     110CXXFLAGS_OPTIMIZE=$(CXXFLAGS_OPTIMIZE_V)
    102111endif
    103112
     
    107116
    108117ifndef AUTOMAKE
    109 CFLAGS += $(CFLAGS_OPTIMIZE) $(CFLAGS_DEBUG) $(CFLAGS_PROFILE)
     118CFLAGS   += $(CFLAGS_OPTIMIZE) $(CFLAGS_DEBUG) $(CFLAGS_PROFILE)
     119CXXFLAGS += $(CXXFLAGS_OPTIMIZE) $(CXXFLAGS_DEBUG) $(CXXFLAGS_PROFILE)
    110120endif
    111121
  • make/custom/eth_comm.cfg

    rf481c39c r8ef3818  
    88
    99RTEMS_CPU=powerpc
    10 RTEMS_CPU_MODEL=mpc860
     10RTEMS_CPU_MODEL=mpc8xx
     11CPU_TYPE=860
    1112
    1213# This is the actual bsp directory used during the build process.
     
    2627#  RTEMS_DEBUG (RTEMS)
    2728#     If defined, debug checks in RTEMS and support library code are enabled.
     29#       
     30#  PPC_VECTOR_FILE_BASE (PowerPC)
     31#     This defines the base address of the exception table.
     32#     NOTE: Vectors are actually at 0xFFF00000 but file starts at offset 0x0100
     33#       
     34#  PPC_ABI (PowerPC)
     35#     This defines the calling convention (Application Binary Interface)
     36#     used in this configuration.  EABI is the only one supported.
     37#     This BSP was initially developed using the PowerOpen ABI.
     38#
     39#  PPC_ASM (PowerPC)
     40#     This defines the assembly language format used in this configuration.
     41#     ELF is the only one supported.
     42#
     43#  PPC_USE_SPRG (RTEMS PowerPC port)
     44#     If defined (=1), then the PowerPC specific code in RTEMS will use some
     45#     of the special purpose registers to slightly optimize interrupt
     46#     response time.  The use of these registers can conflict with
     47#     other tools like debuggers.
    2848
    2949define make-target-options
     50        @echo "#ifdef mpc$(CPU_TYPE)"                       >>$@
     51        @echo "#undef mpc$(CPU_TYPE)"                       >>$@
     52        @echo "#endif"                                      >>$@
     53        @echo "#define mpc$(CPU_TYPE) 1"                    >>$@
     54        @echo                                               >>$@
    3055        @echo "/* #define NDEBUG 1 */ "                     >>$@
    3156        @echo "#define RTEMS_TEST_NO_PAUSE 1"               >>$@
    3257        @echo "/* #define RTEMS_DEBUG  1 */"                >>$@
     58        @echo "#define PPC_VECTOR_FILE_BASE 0x0000"         >>$@
     59        @echo "#define PPC_ABI PPC_ABI_EABI"                >>$@
     60        @echo "#define PPC_ASM PPC_ASM_ELF"                 >>$@
     61        @echo "#define PPC_USE_SPRG 1"                      >>$@
    3362endef
    3463
     
    3665#  and (hopefully) optimize for it.
    3766#
    38 CPU_CFLAGS = -mcpu=860
     67CPU_CFLAGS = -mcpu=$(CPU_TYPE)
    3968
    4069# optimize flag: typically -0, could use -O4 or -fast
  • make/custom/mvme167.cfg

    rf481c39c r8ef3818  
    8787        $(LD) $(LDFLAGS) -N -T $(LINKCMDS) -o $(basename $@).exe \
    8888            $(START_FILE) $(LINK_OBJS) --start-group $(LINK_LIBS) --end-group
    89         $(NM) -g -n $(basename $@).exe > $(basename $@).num
     89        $(NM) -g -n $(basename $@).exe > $(basename $@).nm
     90        $(STRIP) -o $(basename $@) $@
    9091        $(SIZE) $(basename $@).exe
    9192endef
     
    9495        $(LINK.c) $(AM_CFLAGS) $(AM_LDFLAGS) -o $@ \
    9596            $(LINK_OBJS) $(LINK_LIBS)
    96         $(NM) -g -n $@ > $(basename $@).nm
     97        $(NM) -g -n $(basename $@).exe > $(basename $@).nm
    9798        $(STRIP) -o $(basename $@) $@
    9899        $(SIZE) $(basename $@).exe
  • make/leaf.cfg

    rf481c39c r8ef3818  
    5050        $(MAKE) -f $(MAKEFILE) MAKEFILE=$(MAKEFILE) "ARCH=o-debug" \
    5151      "CFLAGS_DEBUG=$(CFLAGS_DEBUG_V)" \
    52       "CFLAGS_OPTIMIZE=$(CFLAGS_OPTIMIZE_V)" \
     52      "CXXFLAGS_DEBUG=$(CXXFLAGS_DEBUG_V)" \
     53      "CFLAGS_OPTIMIZE=$(CFLAGS_DEBUG_OPTIMIZE_V)" \
    5354      "LDFLAGS_DEBUG=$(LDFLAGS_DEBUG_V)" $(TARGET_VA)
    5455
     
    5758      MAKEFILE=$(MAKEFILE) "ARCH=o-profile" \
    5859      "CFLAGS_PROFILE=$(CFLAGS_PROFILE_V)" \
     60      "CXXFLAGS_PROFILE=$(CXXFLAGS_PROFILE_V)" \
    5961      "LDFLAGS_PROFILE=$(LDFLAGS_PROFILE_V)" $(TARGET_VA)
    6062endif
  • testsuites/libtests/termios/init.c

    rf481c39c r8ef3818  
    2424
    2525#include <bsp.h>
     26
    2627
    2728#define CONFIGURE_APPLICATION_NEEDS_CLOCK_DRIVER
     
    588589void canonical_input( struct termios *tp )
    589590{
     591    char buffer[256];
    590592    char c, first_time = TRUE;
    591593   
     
    612614  printf( "\n\nCanonical input test done.\n" );
    613615}
     616
    614617
    615618/*
     
    708711Init (rtems_task_argument ignored)
    709712{
    710   char c;
     713  char c, done;
    711714  struct termios orig_termios, test_termios;
    712715 
  • testsuites/samples/cdtest/system.h

    rf481c39c r8ef3818  
    3535#define CONFIGURE_INIT_TASK_NAME          rtems_build_name( 'C', 'T', 'O', 'R' )
    3636
     37/* Guess at this one */
     38#define CONFIGURE_MAXIMUM_POSIX_MUTEXES 2
     39
    3740#include <confdefs.h>
    3841
  • testsuites/sptests/Makefile.am

    rf481c39c r8ef3818  
    99SUBDIRS = sp01 sp02 sp03 sp04 sp05 sp06 sp07 sp08 sp09 sp11 sp12 sp13 sp14 \
    1010    sp15 sp16 sp17 sp19 sp20 sp21 sp22 sp23 sp24 sp25 sp26 sp27 sp28 sp29 \
    11     spsize
     11    spsize threaditerate
    1212
    1313EXTRA_DIST = sptests.am spfatal
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