Changeset 8e6cfcc in rtems
- Timestamp:
- Aug 6, 2018, 8:29:14 AM (2 years ago)
- Branches:
- 5, master
- Children:
- aac36d15
- Parents:
- 71948f76
- git-author:
- Christian Mauderer <christian.mauderer@…> (08/06/18 08:29:14)
- git-committer:
- Christian Mauderer <christian.mauderer@…> (08/09/18 06:37:38)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
bsps/arm/atsam/spi/atsam_spi_bus.c
r71948f76 r8e6cfcc 86 86 } 87 87 88 static uint32_t atsam_calculate_scbr(uint32_t speed_hz) 89 { 90 uint32_t scbr; 91 92 scbr = BOARD_MCK / speed_hz; 93 if (scbr > 0x0FF) { 94 /* Best estimation we can offer with the hardware. */ 95 scbr = 0x0FF; 96 } 97 if (scbr == 0) { 98 /* SCBR = 0 isn't allowed. */ 99 scbr = 1; 100 } 101 102 return scbr; 103 } 104 88 105 static void atsam_set_phase_and_polarity(uint32_t mode, uint32_t *csr) 89 106 { … … 110 127 { 111 128 uint8_t delay_cs; 129 uint32_t scbr; 112 130 uint32_t csr = 0; 113 131 uint32_t mode = 0; … … 115 133 116 134 delay_cs = atsam_calculate_dlybcs(bus->base.delay_usecs); 135 scbr = atsam_calculate_scbr(bus->base.speed_hz); 117 136 118 137 mode |= SPI_MR_DLYBCS(delay_cs); … … 138 157 SPI_DLYBCT(1000, BOARD_MCK) | 139 158 SPI_DLYBS(1000, BOARD_MCK) | 140 SPI_ SCBR(bus->base.speed_hz, BOARD_MCK) |159 SPI_CSR_SCBR(scbr) | 141 160 SPI_CSR_BITS(bus->base.bits_per_word - 8); 142 161
Note: See TracChangeset
for help on using the changeset viewer.