Ignore:
Timestamp:
Jul 19, 2018, 10:11:19 AM (11 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
7fe4855
Parents:
5694b0c
git-author:
Sebastian Huber <sebastian.huber@…> (07/19/18 10:11:19)
git-committer:
Sebastian Huber <sebastian.huber@…> (07/25/18 08:07:43)
Message:

riscv: Rework exception handling

Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector()
functions. Applications can install an exception handler via the fatal
error handler to handle synchronous exceptions.

Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must
be provided by the BSP.

Update #3433.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/riscv/riscv-exception-handler.S

    r5694b0c r8db3f0e  
    4242#include <rtems/score/percpu.h>
    4343
    44 EXTERN(bsp_start_vector_table_begin)
    45 EXTERN(_Thread_Dispatch)
    46 PUBLIC(ISR_Handler)
     44PUBLIC(_RISCV_Exception_handler)
    4745
    4846        .section        .text, "ax", @progbits
    4947        .align  2
    5048
    51 TYPE_FUNC(ISR_Handler)
    52 SYM(ISR_Handler):
     49TYPE_FUNC(_RISCV_Exception_handler)
     50SYM(_RISCV_Exception_handler):
    5351        addi    sp, sp, -CPU_INTERRUPT_FRAME_SIZE
    5452
     
    105103#endif
    106104
    107         /* FIXME Only handle interrupts for now (MSB = 1) */
    108         andi    a0, a0, 0xf
     105        /* Check if this is a synchronous or interrupt exception */
     106        bgez    a0, .Lsynchronous_exception
    109107
    110108        /* Increment interrupt nest and thread dispatch disable level */
     
    118116        CLEAR_RESERVATIONS      s0
    119117
    120         /* Keep sp (Exception frame address) in s1 */
     118        /*
     119         * Remember current stack pointer in non-volatile register s1.  Switch
     120         * to interrupt stack if necessary.
     121         */
    121122        mv      s1, sp
    122 
    123         /* Call the exception handler from vector table */
    124 
    125         /* First function arg for C handler is vector number,
    126                 * and the second is a pointer to exception frame.
    127                 * a0/mcause/vector number is already loaded above */
    128         mv      a1, sp
    129 
    130         /* calculate the offset */
    131         LADDR   t5, bsp_start_vector_table_begin
    132 #if     __riscv_xlen == 32
    133         slli    t6, a0, 2
    134 #else   /* xlen = 64 */
    135         slli    t6, a0, 3
    136 #endif
    137         add     t5, t5, t6
    138         LREG    t5, (t5)
    139 
    140         /* Switch to interrupt stack if necessary */
    141123        bnez    t0, .Linterrupt_stack_switch_done
    142124        LREG    sp, PER_CPU_INTERRUPT_STACK_HIGH(s0)
    143125.Linterrupt_stack_switch_done:
    144126
    145         jalr    t5
     127        mv      a1, s0
     128        call    _RISCV_Interrupt_dispatch
    146129
    147130        /* Load some per-CPU variables */
     
    250233
    251234        mret
     235
     236.Lsynchronous_exception:
     237
     238        SREG    a0, RISCV_EXCEPTION_FRAME_MCAUSE(sp)
     239        addi    a0, sp, CPU_INTERRUPT_FRAME_SIZE
     240        SREG    a0, RISCV_EXCEPTION_FRAME_SP(sp)
     241        SREG    gp, RISCV_EXCEPTION_FRAME_GP(sp)
     242        SREG    tp, RISCV_EXCEPTION_FRAME_TP(sp)
     243        SREG    s2, RISCV_EXCEPTION_FRAME_S2(sp)
     244        SREG    s3, RISCV_EXCEPTION_FRAME_S3(sp)
     245        SREG    s4, RISCV_EXCEPTION_FRAME_S4(sp)
     246        SREG    s5, RISCV_EXCEPTION_FRAME_S5(sp)
     247        SREG    s6, RISCV_EXCEPTION_FRAME_S6(sp)
     248        SREG    s7, RISCV_EXCEPTION_FRAME_S7(sp)
     249        SREG    s8, RISCV_EXCEPTION_FRAME_S8(sp)
     250        SREG    s9, RISCV_EXCEPTION_FRAME_S9(sp)
     251        SREG    s10, RISCV_EXCEPTION_FRAME_S10(sp)
     252        SREG    s11, RISCV_EXCEPTION_FRAME_S11(sp)
     253#if __riscv_flen > 0
     254        FSREG   fs0, RISCV_EXCEPTION_FRAME_FS0(sp)
     255        FSREG   fs1, RISCV_EXCEPTION_FRAME_FS1(sp)
     256        FSREG   fs2, RISCV_EXCEPTION_FRAME_FS2(sp)
     257        FSREG   fs3, RISCV_EXCEPTION_FRAME_FS3(sp)
     258        FSREG   fs4, RISCV_EXCEPTION_FRAME_FS4(sp)
     259        FSREG   fs5, RISCV_EXCEPTION_FRAME_FS5(sp)
     260        FSREG   fs6, RISCV_EXCEPTION_FRAME_FS6(sp)
     261        FSREG   fs7, RISCV_EXCEPTION_FRAME_FS7(sp)
     262        FSREG   fs8, RISCV_EXCEPTION_FRAME_FS8(sp)
     263        FSREG   fs9, RISCV_EXCEPTION_FRAME_FS9(sp)
     264        FSREG   fs10, RISCV_EXCEPTION_FRAME_FS10(sp)
     265        FSREG   fs11, RISCV_EXCEPTION_FRAME_FS11(sp)
     266#endif
     267
     268        li      a0, 9
     269        mv      a1, sp
     270        call    _Terminate
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