Changeset 8db3f0e in rtems for bsps/riscv/riscv/start/start.S


Ignore:
Timestamp:
Jul 19, 2018, 10:11:19 AM (15 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
7fe4855
Parents:
5694b0c
git-author:
Sebastian Huber <sebastian.huber@…> (07/19/18 10:11:19)
git-committer:
Sebastian Huber <sebastian.huber@…> (07/25/18 08:07:43)
Message:

riscv: Rework exception handling

Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector()
functions. Applications can install an exception handler via the fatal
error handler to handle synchronous exceptions.

Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must
be provided by the BSP.

Update #3433.

File:
1 edited

Legend:

Unmodified
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Removed
  • bsps/riscv/riscv/start/start.S

    r5694b0c r8db3f0e  
    11/*
     2 * Copyright (c) 2018 embedded brains GmbH
     3
    24 * Copyright (c) 2015 University of York.
    35 * Hesham Almatary <hesham@alumni.york.ac.uk>
     
    3436#include <bspopts.h>
    3537
    36 EXTERN(bsp_section_bss_begin)
    37 EXTERN(bsp_section_bss_end)
    38 EXTERN(ISR_Handler)
    39 EXTERN(bsp_section_stack_begin)
    40 
    41 PUBLIC(bsp_start_vector_table_begin)
    42 PUBLIC(bsp_start_vector_table_end)
    4338PUBLIC(_start)
    4439
     
    7166#endif
    7267
    73         LADDR   t0, ISR_Handler
     68        LADDR   t0, _RISCV_Exception_handler
    7469        csrw    mtvec, t0
    7570
     
    108103        .word   0xdeadbeef
    109104#endif
    110 
    111 #if __riscv_xlen == 32
    112 #define ADDR .word
    113 #elif __riscv_xlen == 64
    114 #define ADDR .quad
    115 #endif
    116 
    117         .align  4
    118 bsp_start_vector_table_begin:
    119         ADDR    _RISCV_Exception_default /* User int */
    120         ADDR    _RISCV_Exception_default /* Supervisor int */
    121         ADDR    _RISCV_Exception_default /* Reserved */
    122         ADDR    _RISCV_Exception_default /* Machine int */
    123         ADDR    _RISCV_Exception_default /* User timer int */
    124         ADDR    _RISCV_Exception_default /* Supervisor Timer int */
    125         ADDR    _RISCV_Exception_default /* Reserved */
    126         ADDR    _RISCV_Exception_default /* Machine Timer int */
    127         ADDR    _RISCV_Exception_default /* User external int */
    128         ADDR    _RISCV_Exception_default /* Supervisor external int */
    129         ADDR    _RISCV_Exception_default /* Reserved */
    130         ADDR    _RISCV_Exception_default /* Machine external int */
    131         ADDR    _RISCV_Exception_default
    132         ADDR    _RISCV_Exception_default
    133         ADDR    _RISCV_Exception_default
    134         ADDR    _RISCV_Exception_default
    135 bsp_start_vector_table_end:
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