Changeset 8db3f0e in rtems


Ignore:
Timestamp:
Jul 19, 2018, 10:11:19 AM (10 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
7fe4855
Parents:
5694b0c
git-author:
Sebastian Huber <sebastian.huber@…> (07/19/18 10:11:19)
git-committer:
Sebastian Huber <sebastian.huber@…> (07/25/18 08:07:43)
Message:

riscv: Rework exception handling

Remove _CPU_ISR_install_raw_handler() and _CPU_ISR_install_vector()
functions. Applications can install an exception handler via the fatal
error handler to handle synchronous exceptions.

Handle interrupt exceptions via _RISCV_Interrupt_dispatch() which must
be provided by the BSP.

Update #3433.

Files:
14 edited
1 moved

Legend:

Unmodified
Added
Removed
  • bsps/include/bsp/fatal.h

    r5694b0c r8db3f0e  
    143143  RISCV_FATAL_NO_TIMEBASE_FREQUENCY_IN_DEVICE_TREE = BSP_FATAL_CODE_BLOCK(13),
    144144  RISCV_FATAL_NO_NS16550_REG_IN_DEVICE_TREE,
    145   RISCV_FATAL_NO_NS16550_CLOCK_FREQUENCY_IN_DEVICE_TREE
     145  RISCV_FATAL_NO_NS16550_CLOCK_FREQUENCY_IN_DEVICE_TREE,
     146  RISCV_FATAL_UNEXPECTED_INTERRUPT_EXCEPTION,
     147  RISCV_FATAL_CLOCK_IRQ_INSTALL
    146148} bsp_fatal_code;
    147149
  • bsps/riscv/include/bsp/linker-symbols.h

    r5694b0c r8db3f0e  
    6464LINKER_SYMBOL(bsp_vector_table_size)
    6565
    66 LINKER_SYMBOL(bsp_start_vector_table_begin)
    67 LINKER_SYMBOL(bsp_start_vector_table_end)
    68 LINKER_SYMBOL(bsp_start_vector_table_size)
    69 
    7066LINKER_SYMBOL(bsp_translation_table_base)
    7167LINKER_SYMBOL(bsp_translation_table_end)
  • bsps/riscv/riscv/btimer/btimer.c

    r5694b0c r8db3f0e  
    2929#include <rtems/btimer.h>
    3030#include <rtems/score/riscv-utility.h>
    31 
    32 extern char bsp_start_vector_table_begin[];
    3331
    3432bool benchmark_timer_find_average_overhead;
  • bsps/riscv/riscv/clock/clockdrv.c

    r5694b0c r8db3f0e  
    7373}
    7474
    75 static void riscv_clock_handler_install(proc_ptr new_isr)
     75static void riscv_clock_handler_install(void)
    7676{
    77   _CPU_ISR_install_vector(RISCV_MACHINE_TIMER_INTERRUPT,
    78                           new_isr,
    79                           NULL);
     77  rtems_status_code sc;
     78
     79  sc = rtems_interrupt_handler_install(
     80    RISCV_INTERRUPT_VECTOR_TIMER,
     81    "Clock",
     82    RTEMS_INTERRUPT_UNIQUE,
     83    (rtems_interrupt_handler) Clock_isr,
     84    NULL
     85  );
     86  if (sc != RTEMS_SUCCESSFUL) {
     87    bsp_fatal(RISCV_FATAL_CLOCK_IRQ_INSTALL);
     88  }
    8089}
    8190
     
    137146
    138147#define Clock_driver_support_install_isr(isr) \
    139   riscv_clock_handler_install(isr)
     148  riscv_clock_handler_install()
    140149
    141150#include "../../../shared/dev/clock/clockimpl.h"
  • bsps/riscv/riscv/include/bsp/irq.h

    r5694b0c r8db3f0e  
    88
    99/*
     10 * Copyright (c) 2018 embedded brains GmbH
    1011 *
    1112 * Copyright (c) 2015 University of York.
     
    3940#ifndef ASM
    4041
    41 #include <rtems.h>
     42#include <bsp.h>
    4243#include <rtems/irq.h>
    4344#include <rtems/irq-extension.h>
    4445
    45 #define BSP_INTERRUPT_VECTOR_MIN  0x0
    46 #define BSP_INTERRUPT_VECTOR_MAX  0x24
     46#define RISCV_INTERRUPT_VECTOR_SOFTWARE 0
     47
     48#define RISCV_INTERRUPT_VECTOR_TIMER 1
     49
     50#define RISCV_INTERRUPT_VECTOR_EXTERNAL(x) ((x) + 2)
     51
     52#define BSP_INTERRUPT_VECTOR_MIN 0
     53
     54#define BSP_INTERRUPT_VECTOR_MAX RISCV_INTERRUPT_VECTOR_EXTERNAL(RISCV_MAXIMUM_EXTERNAL_INTERRUPTS - 1)
    4755
    4856#endif /* ASM */
     57
    4958#endif /* LIBBSP_GENERIC_RISCV_IRQ_H */
  • bsps/riscv/riscv/irq/irq.c

    r5694b0c r8db3f0e  
    88
    99/*
    10  * RISCV CPU Dependent Source
     10 * Copyright (c) 2018 embedded brains GmbH
    1111 *
    1212 * Copyright (c) 2015 University of York.
     
    3636
    3737#include <bsp/irq.h>
     38#include <bsp/fatal.h>
    3839#include <bsp/irq-generic.h>
    3940
    40 rtems_status_code bsp_interrupt_facility_initialize()
     41#include <rtems/score/percpu.h>
     42
     43void _RISCV_Interrupt_dispatch(uintptr_t mcause, Per_CPU_Control *cpu_self)
    4144{
    42   return RTEMS_NOT_IMPLEMENTED;
     45  /*
     46   * Get rid of the most significant bit which indicates if the exception was
     47   * caused by an interrupt or not.
     48   */
     49  mcause <<= 1;
     50
     51  if (mcause == (RISCV_INTERRUPT_TIMER_MACHINE << 1)) {
     52    bsp_interrupt_handler_dispatch(RISCV_INTERRUPT_VECTOR_TIMER);
     53  } else if (mcause == (RISCV_INTERRUPT_EXTERNAL_MACHINE << 1)) {
     54    /* TODO: Handle PLIC interrupt */
     55  } else if (mcause == (RISCV_INTERRUPT_SOFTWARE_MACHINE << 1)) {
     56    bsp_interrupt_handler_dispatch(RISCV_INTERRUPT_VECTOR_SOFTWARE);
     57  } else {
     58    bsp_fatal(RISCV_FATAL_UNEXPECTED_INTERRUPT_EXCEPTION);
     59  }
     60}
     61
     62rtems_status_code bsp_interrupt_facility_initialize(void)
     63{
     64  return RTEMS_SUCCESSFUL;
    4365}
    4466
  • bsps/riscv/riscv/start/bspstart.c

    r5694b0c r8db3f0e  
    11/*
    2  * Copyright (c) 2014 Hesham Almatary <heshamelmatary@gmail.com>
     2 * Copyright (c) 2018 embedded brains GmbH
    33 *
    44 * Redistribution and use in source and binary forms, with or without
     
    2424 */
    2525
    26 #ifdef HAVE_CONFIG_H
    27 #include "config.h"
    28 #endif
     26#include <bsp/bootcard.h>
     27#include <bsp/irq-generic.h>
    2928
    30 #include <rtems/score/cpu.h>
    31 #include <rtems/fatal.h>
    32 #include <stdio.h>
    33 
    34 void _RISCV_Exception_default(uint32_t vector, CPU_Exception_frame *frame);
    35 
    36 void _RISCV_Exception_default(uint32_t vector, CPU_Exception_frame *frame)
     29void bsp_start(void)
    3730{
    38   rtems_fatal( RTEMS_FATAL_SOURCE_EXCEPTION, (rtems_fatal_code) frame );
     31  bsp_interrupt_initialize();
    3932}
  • bsps/riscv/riscv/start/start.S

    r5694b0c r8db3f0e  
    11/*
     2 * Copyright (c) 2018 embedded brains GmbH
     3
    24 * Copyright (c) 2015 University of York.
    35 * Hesham Almatary <hesham@alumni.york.ac.uk>
     
    3436#include <bspopts.h>
    3537
    36 EXTERN(bsp_section_bss_begin)
    37 EXTERN(bsp_section_bss_end)
    38 EXTERN(ISR_Handler)
    39 EXTERN(bsp_section_stack_begin)
    40 
    41 PUBLIC(bsp_start_vector_table_begin)
    42 PUBLIC(bsp_start_vector_table_end)
    4338PUBLIC(_start)
    4439
     
    7166#endif
    7267
    73         LADDR   t0, ISR_Handler
     68        LADDR   t0, _RISCV_Exception_handler
    7469        csrw    mtvec, t0
    7570
     
    108103        .word   0xdeadbeef
    109104#endif
    110 
    111 #if __riscv_xlen == 32
    112 #define ADDR .word
    113 #elif __riscv_xlen == 64
    114 #define ADDR .quad
    115 #endif
    116 
    117         .align  4
    118 bsp_start_vector_table_begin:
    119         ADDR    _RISCV_Exception_default /* User int */
    120         ADDR    _RISCV_Exception_default /* Supervisor int */
    121         ADDR    _RISCV_Exception_default /* Reserved */
    122         ADDR    _RISCV_Exception_default /* Machine int */
    123         ADDR    _RISCV_Exception_default /* User timer int */
    124         ADDR    _RISCV_Exception_default /* Supervisor Timer int */
    125         ADDR    _RISCV_Exception_default /* Reserved */
    126         ADDR    _RISCV_Exception_default /* Machine Timer int */
    127         ADDR    _RISCV_Exception_default /* User external int */
    128         ADDR    _RISCV_Exception_default /* Supervisor external int */
    129         ADDR    _RISCV_Exception_default /* Reserved */
    130         ADDR    _RISCV_Exception_default /* Machine external int */
    131         ADDR    _RISCV_Exception_default
    132         ADDR    _RISCV_Exception_default
    133         ADDR    _RISCV_Exception_default
    134         ADDR    _RISCV_Exception_default
    135 bsp_start_vector_table_end:
  • c/src/lib/libbsp/riscv/riscv/Makefile.am

    r5694b0c r8db3f0e  
    3434# Startup
    3535librtemsbsp_a_SOURCES = ../../../../../../bsps/shared/start/bspreset-empty.c
    36 librtemsbsp_a_SOURCES += ../../../../../../bsps/shared/start/bspstart-empty.c
     36librtemsbsp_a_SOURCES += ../../../../../../bsps/riscv/riscv/start/bspstart.c
    3737librtemsbsp_a_SOURCES += ../../../../../../bsps/riscv/riscv/start/bsp_fatal_halt.c
    3838
  • c/src/lib/libbsp/riscv/riscv/configure.ac

    r5694b0c r8db3f0e  
    3030RTEMS_BSPOPTS_SET([BSP_CONSOLE_BAUD],[*],[115200])
    3131RTEMS_BSPOPTS_HELP([BSP_CONSOLE_BAUD],[default baud for console driver devices (default 115200)])
     32
     33RTEMS_BSPOPTS_SET([RISCV_MAXIMUM_EXTERNAL_INTERRUPTS],[*],[64])
     34RTEMS_BSPOPTS_HELP([RISCV_MAXIMUM_EXTERNAL_INTERRUPTS],[maximum number of external interrupts supported by the BSP (default 64)])
    3235
    3336RTEMS_BSPOPTS_SET([RISCV_ENABLE_HTIF_SUPPORT],[*],[1])
  • cpukit/score/cpu/riscv/Makefile.am

    r5694b0c r8db3f0e  
    44libscorecpu_a_SOURCES  = cpu.c
    55libscorecpu_a_SOURCES += riscv-exception-handler.S
    6 libscorecpu_a_SOURCES += riscv-exception-default.c
    76libscorecpu_a_SOURCES += riscv-exception-frame-print.c
    87libscorecpu_a_SOURCES += riscv-context-switch.S
  • cpukit/score/cpu/riscv/cpu.c

    r5694b0c r8db3f0e  
    174174);
    175175
    176 /* bsp_start_vector_table_begin is the start address of the vector table
    177  * containing addresses to ISR Handlers. It's defined at the BSP linkcmds
    178  * and may differ from one BSP to another.
    179  */
    180 extern char bsp_start_vector_table_begin[];
    181 
    182176void _init(void);
    183177
     
    209203}
    210204
    211 void _CPU_ISR_install_raw_handler(
    212   uint32_t   vector,
    213   proc_ptr    new_handler,
    214   proc_ptr   *old_handler
    215 )
    216 {
    217   /* Do nothing */
    218 }
    219 
    220 void _CPU_ISR_install_vector(
    221   unsigned long    vector,
    222   proc_ptr    new_handler,
    223   proc_ptr   *old_handler
    224 )
    225 {
    226   proc_ptr *table =
    227     (proc_ptr *) bsp_start_vector_table_begin;
    228   proc_ptr current_handler;
    229 
    230   ISR_Level level;
    231 
    232   _ISR_Local_disable( level );
    233 
    234   current_handler = table [vector];
    235 
    236   /* The current handler is now the old one */
    237   if (old_handler != NULL) {
    238     *old_handler = (proc_ptr) current_handler;
    239   }
    240 
    241   /* Write only if necessary to avoid writes to a maybe read-only
    242    * memory */
    243   if (current_handler != new_handler) {
    244     table [vector] = new_handler;
    245   }
    246 
    247   _ISR_Local_enable( level );
    248 
    249 }
    250 
    251205void *_CPU_Thread_Idle_body( uintptr_t ignored )
    252206{
  • cpukit/score/cpu/riscv/include/rtems/score/cpu.h

    r5694b0c r8db3f0e  
    362362
    363363/*
    364  *  _CPU_ISR_install_raw_handler
    365  *
    366  *  This routine installs a "raw" interrupt handler directly into the
    367  *  processor's vector table.
    368  *
    369  */
    370 
    371 void _CPU_ISR_install_raw_handler(
    372   uint32_t    vector,
    373   proc_ptr    new_handler,
    374   proc_ptr   *old_handler
    375 );
    376 
    377 /*
    378  *  _CPU_ISR_install_vector
    379  *
    380  *  This routine installs an interrupt vector.
    381  *
    382  *  NO_CPU Specific Information:
    383  *
    384  *  XXX document implementation including references if appropriate
    385  */
    386 
    387 void _CPU_ISR_install_vector(
    388   unsigned long    vector,
    389   proc_ptr   new_handler,
    390   proc_ptr   *old_handler
    391 );
    392 
    393 /*
    394364 *  _CPU_Thread_Idle_body
    395365 *
  • cpukit/score/cpu/riscv/include/rtems/score/cpuimpl.h

    r5694b0c r8db3f0e  
    290290#endif
    291291
     292struct Per_CPU_Control;
     293
     294void _RISCV_Interrupt_dispatch(
     295  uintptr_t               mcause,
     296  struct Per_CPU_Control *cpu_self
     297);
     298
    292299static inline uint32_t _RISCV_Read_FCSR( void )
    293300{
  • cpukit/score/cpu/riscv/riscv-exception-handler.S

    r5694b0c r8db3f0e  
    4242#include <rtems/score/percpu.h>
    4343
    44 EXTERN(bsp_start_vector_table_begin)
    45 EXTERN(_Thread_Dispatch)
    46 PUBLIC(ISR_Handler)
     44PUBLIC(_RISCV_Exception_handler)
    4745
    4846        .section        .text, "ax", @progbits
    4947        .align  2
    5048
    51 TYPE_FUNC(ISR_Handler)
    52 SYM(ISR_Handler):
     49TYPE_FUNC(_RISCV_Exception_handler)
     50SYM(_RISCV_Exception_handler):
    5351        addi    sp, sp, -CPU_INTERRUPT_FRAME_SIZE
    5452
     
    105103#endif
    106104
    107         /* FIXME Only handle interrupts for now (MSB = 1) */
    108         andi    a0, a0, 0xf
     105        /* Check if this is a synchronous or interrupt exception */
     106        bgez    a0, .Lsynchronous_exception
    109107
    110108        /* Increment interrupt nest and thread dispatch disable level */
     
    118116        CLEAR_RESERVATIONS      s0
    119117
    120         /* Keep sp (Exception frame address) in s1 */
     118        /*
     119         * Remember current stack pointer in non-volatile register s1.  Switch
     120         * to interrupt stack if necessary.
     121         */
    121122        mv      s1, sp
    122 
    123         /* Call the exception handler from vector table */
    124 
    125         /* First function arg for C handler is vector number,
    126                 * and the second is a pointer to exception frame.
    127                 * a0/mcause/vector number is already loaded above */
    128         mv      a1, sp
    129 
    130         /* calculate the offset */
    131         LADDR   t5, bsp_start_vector_table_begin
    132 #if     __riscv_xlen == 32
    133         slli    t6, a0, 2
    134 #else   /* xlen = 64 */
    135         slli    t6, a0, 3
    136 #endif
    137         add     t5, t5, t6
    138         LREG    t5, (t5)
    139 
    140         /* Switch to interrupt stack if necessary */
    141123        bnez    t0, .Linterrupt_stack_switch_done
    142124        LREG    sp, PER_CPU_INTERRUPT_STACK_HIGH(s0)
    143125.Linterrupt_stack_switch_done:
    144126
    145         jalr    t5
     127        mv      a1, s0
     128        call    _RISCV_Interrupt_dispatch
    146129
    147130        /* Load some per-CPU variables */
     
    250233
    251234        mret
     235
     236.Lsynchronous_exception:
     237
     238        SREG    a0, RISCV_EXCEPTION_FRAME_MCAUSE(sp)
     239        addi    a0, sp, CPU_INTERRUPT_FRAME_SIZE
     240        SREG    a0, RISCV_EXCEPTION_FRAME_SP(sp)
     241        SREG    gp, RISCV_EXCEPTION_FRAME_GP(sp)
     242        SREG    tp, RISCV_EXCEPTION_FRAME_TP(sp)
     243        SREG    s2, RISCV_EXCEPTION_FRAME_S2(sp)
     244        SREG    s3, RISCV_EXCEPTION_FRAME_S3(sp)
     245        SREG    s4, RISCV_EXCEPTION_FRAME_S4(sp)
     246        SREG    s5, RISCV_EXCEPTION_FRAME_S5(sp)
     247        SREG    s6, RISCV_EXCEPTION_FRAME_S6(sp)
     248        SREG    s7, RISCV_EXCEPTION_FRAME_S7(sp)
     249        SREG    s8, RISCV_EXCEPTION_FRAME_S8(sp)
     250        SREG    s9, RISCV_EXCEPTION_FRAME_S9(sp)
     251        SREG    s10, RISCV_EXCEPTION_FRAME_S10(sp)
     252        SREG    s11, RISCV_EXCEPTION_FRAME_S11(sp)
     253#if __riscv_flen > 0
     254        FSREG   fs0, RISCV_EXCEPTION_FRAME_FS0(sp)
     255        FSREG   fs1, RISCV_EXCEPTION_FRAME_FS1(sp)
     256        FSREG   fs2, RISCV_EXCEPTION_FRAME_FS2(sp)
     257        FSREG   fs3, RISCV_EXCEPTION_FRAME_FS3(sp)
     258        FSREG   fs4, RISCV_EXCEPTION_FRAME_FS4(sp)
     259        FSREG   fs5, RISCV_EXCEPTION_FRAME_FS5(sp)
     260        FSREG   fs6, RISCV_EXCEPTION_FRAME_FS6(sp)
     261        FSREG   fs7, RISCV_EXCEPTION_FRAME_FS7(sp)
     262        FSREG   fs8, RISCV_EXCEPTION_FRAME_FS8(sp)
     263        FSREG   fs9, RISCV_EXCEPTION_FRAME_FS9(sp)
     264        FSREG   fs10, RISCV_EXCEPTION_FRAME_FS10(sp)
     265        FSREG   fs11, RISCV_EXCEPTION_FRAME_FS11(sp)
     266#endif
     267
     268        li      a0, 9
     269        mv      a1, sp
     270        call    _Terminate
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