Changeset 8c5c8b27 in rtems
- Timestamp:
- Jul 17, 2016, 5:31:33 PM (5 years ago)
- Branches:
- 4.11
- Children:
- d3a428c
- Parents:
- ae3578a2
- git-author:
- Pavel Pisa <pisa@…> (07/17/16 17:31:33)
- git-committer:
- Pavel Pisa <pisa@…> (10/02/16 08:40:34)
- Location:
- c/src/lib
- Files:
-
- 3 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h
rae3578a2 r8c5c8b27 50 50 { 51 51 _ARM_Data_synchronization_barrier(); 52 arm_cp15_drain_write_buffer();53 52 arm_cache_l1_flush_data_range( 54 53 d_addr, 55 54 n_bytes 56 55 ); 56 #if !defined(__ARM_ARCH_7A__) 57 arm_cp15_drain_write_buffer(); 58 #endif 59 _ARM_Data_synchronization_barrier(); 57 60 } 58 61 … … 93 96 { 94 97 arm_cache_l1_invalidate_instruction_range( i_addr, n_bytes ); 98 _ARM_Instruction_synchronization_barrier(); 95 99 } 96 100 … … 107 111 static inline void _CPU_cache_flush_entire_data(void) 108 112 { 109 arm_cp15_data_cache_test_and_clean(); 113 _ARM_Data_synchronization_barrier(); 114 #if defined(__ARM_ARCH_7A__) 115 arm_cp15_data_cache_clean_all_levels(); 116 #else 117 arm_cp15_data_cache_clean_and_invalidate(); 118 arm_cp15_drain_write_buffer(); 119 #endif 120 _ARM_Data_synchronization_barrier(); 110 121 } 111 122 112 123 static inline void _CPU_cache_invalidate_entire_data(void) 113 124 { 125 #if defined(__ARM_ARCH_7A__) 126 arm_cp15_data_cache_invalidate_all_levels(); 127 #else 114 128 arm_cp15_data_cache_invalidate(); 129 #endif 115 130 } 116 131 … … 142 157 static inline void _CPU_cache_invalidate_entire_instruction(void) 143 158 { 144 arm_cp15_instruction_cache_invalidate(); 159 arm_cache_l1_invalidate_entire_instruction(); 160 _ARM_Instruction_synchronization_barrier(); 145 161 } 146 162 -
c/src/lib/libbsp/arm/shared/include/arm-cache-l1.h
rae3578a2 r8c5c8b27 330 330 #endif /* RTEMS_SMP */ 331 331 332 if ( ( ctrl & ARM_CP15_CTRL_Z ) == 0 ) { 332 if ( ( ctrl & ARM_CP15_CTRL_Z ) != 0 ) { 333 #if defined(__ARM_ARCH_7A__) 333 334 arm_cp15_branch_predictor_inner_shareable_invalidate_all(); 335 #endif 336 #if defined(__ARM_ARCH_6KZ__) || defined(__ARM_ARCH_7A__) 334 337 arm_cp15_branch_predictor_invalidate_all(); 338 #endif 335 339 } 336 340 } -
c/src/lib/libcpu/arm/shared/include/arm-cp15.h
rae3578a2 r8c5c8b27 1072 1072 uint32_t ctype = arm_clidr_get_cache_type(clidr, level); 1073 1073 1074 /* Check if this level has a data cache */1075 if (( ctype & 0x2) != 0) {1074 /* Check if this level has a data cache or unified cache */ 1075 if (((ctype & (0x6)) == 2) || (ctype == 4)) { 1076 1076 uint32_t ccsidr; 1077 1077 uint32_t line_power; … … 1132 1132 : "memory" 1133 1133 ); 1134 } 1135 1136 ARM_CP15_TEXT_SECTION static inline void 1137 arm_cp15_data_cache_clean_all_levels(void) 1138 { 1139 uint32_t clidr = arm_cp15_get_cache_level_id(); 1140 uint32_t loc = arm_clidr_get_level_of_coherency(clidr); 1141 uint32_t level = 0; 1142 1143 for (level = 0; level < loc; ++level) { 1144 uint32_t ctype = arm_clidr_get_cache_type(clidr, level); 1145 1146 /* Check if this level has a data cache or unified cache */ 1147 if (((ctype & (0x6)) == 2) || (ctype == 4)) { 1148 uint32_t ccsidr; 1149 uint32_t line_power; 1150 uint32_t associativity; 1151 uint32_t way; 1152 uint32_t way_shift; 1153 1154 ccsidr = arm_cp15_get_cache_size_id_for_level(level << 1); 1155 1156 line_power = arm_ccsidr_get_line_power(ccsidr); 1157 associativity = arm_ccsidr_get_associativity(ccsidr); 1158 way_shift = __builtin_clz(associativity - 1); 1159 1160 for (way = 0; way < associativity; ++way) { 1161 uint32_t num_sets = arm_ccsidr_get_num_sets(ccsidr); 1162 uint32_t set; 1163 1164 for (set = 0; set < num_sets; ++set) { 1165 uint32_t set_way = (way << way_shift) 1166 | (set << line_power) 1167 | (level << 1); 1168 1169 arm_cp15_data_cache_clean_line_by_set_and_way(set_way); 1170 } 1171 } 1172 } 1173 } 1134 1174 } 1135 1175
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