Changeset 8bac485 in rtems


Ignore:
Timestamp:
Jul 10, 2008, 9:31:06 PM (11 years ago)
Author:
Till Straumann <strauman@…>
Branches:
4.10, 4.11, 4.9, master
Children:
d71e95a
Parents:
38f5e61
Message:

2008-07-10 Till Straumann <strauman@…>

  • new-exceptions/bspsupport/ppc_exc_asm_macros.S, new-exceptions/bspsupport/ppc_exc_bspsupp.h, new-exceptions/bspsupport/ppc_exc_hdl.c, new-exceptions/bspsupport/vectors_init.c: fixed and enabled stack-switching algorithm which figures out if we already run on the ISR stack rather than relying on the _ISR_Nest_level.

Added 'ppc_exc_crit_always_enabled' variable which defines
the semantics of critical interrupts. Added a test to
TEST_LOCK_crit so that calling ppc_exc_wrapup() (and
possibly the dispatcher) is always skipped if the BSP/user
wants to leave critical interrupts always enabled (at the
expense of having no OS support).

changed TEST_LOCK_mchk so that asynchronous machine-check
handlers never call ppc_exc_wrapup() (and the dispatcher).
We don't want to disable MSR_ME ever (to avoid checkstops)
and hence asynchronous MEs must not use OS services anyways.

added and commented new variables 'ppc_exc_intr_stack_size'
'ppc_exc_crit_always_enabled'.

Location:
c/src/lib/libcpu/powerpc/new-exceptions/bspsupport
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_asm_macros.h

    r38f5e61 r8bac485  
    8585 *     them while the stack is switched).
    8686 */
    87 #if 0
     87#if 1
    8888        .macro  SWITCH_STACK RA RB FLVR
    8989        mfspr   \RB, SPRG1
     
    9191        bgt             do_r1_reload_\FLVR
    9292        lwz     \RA, ppc_exc_intr_stack_size@sdarel(r13)
    93         subf    \RB, \RB, \RA
     93        subf    \RB, \RA, \RB
    9494        cmplw   cr0, r1, \RB
    9595        bge             no_r1_reload_\FLVR
     
    9797        mfspr   r1, SPRG1
    9898no_r1_reload_\FLVR:
     99        lwz             \RA, _ISR_Nest_level@sdarel(r13)
     100        addi    \RA, \RA, 1
     101        stw             \RA, _ISR_Nest_level@sdarel(r13)
    99102        .endm
    100103#else
     
    270273 *
    271274 */
    272         .macro TEST_LOCK_std _SRR0
     275        .macro TEST_LOCK_std _SRR0 _FLVR
    273276        /* 'std' is lowest level, i.e., can not be locked -> EQ(cr4) = 1 */
    274277        creqv EQ(cr4), EQ(cr4), EQ(cr4)
     
    286289 *
    287290 * Return cr4 = (   ppc_std_lock == 0
    288  *               && * _SRR0 != <write std lock instruction> )
    289  *
    290  */
    291         .macro TEST_LOCK_crit _SRR0
     291 *               && * _SRR0 != <write std lock instruction>
     292 *               && ppc_exc_crit_always_enabled == 0 )
     293 *
     294 */
     295        .macro TEST_LOCK_crit _SRR0 _FLVR
     296        /* Are critical exceptions always enabled ? */
     297        lwz     r4, ppc_exc_crit_always_enabled@sdarel(r13)
     298        cmpwi cr4, r4, 0
     299        bne  cr4, TEST_LOCK_crit_done_\_FLVR
     300
    292301        /* STD interrupt could have been interrupted before
    293302         * executing the 1st instruction which sets the lock;
     
    312321         */
    313322        crandc  EQ(cr4), EQ(cr0), EQ(cr4)
    314         .endm
    315 
     323TEST_LOCK_crit_done_\_FLVR:
     324        .endm
     325
     326#if 0
    316327/*
    317328 **********************************************************************
     
    329340 *               && ppc_crit_lock == 0 )
    330341 */
    331         .macro TEST_LOCK_mchk _SRR0
     342        .macro TEST_LOCK_mchk _SRR0 _FLVR
    332343        TEST_1ST_OPCODE_mchk _REG=r4 _SRR0=\_SRR0
    333344        /* cr4 set if 1st opcode matches writing either lock */
     
    344355        crandc  EQ(cr4), EQ(cr0), EQ(cr4)
    345356        .endm
     357#else
     358/*
     359 **********************************************************************
     360 * MACRO: TEST_LOCK_mchk
     361 **********************************************************************
     362 *
     363 * USES:    cr4
     364 * ON EXIT: cr4 is cleared.
     365 *
     366 * We never want to disable machine-check exceptions to avoid
     367 * a checkstop. This means that we cannot use enabling/disabling
     368 * this type of exception for protection of critical OS data structures.
     369 * Therefore, calling OS primitives from a machine-check handler
     370 * is ILLEGAL. Since machine-checks can happen anytime it is not
     371 * legal to perform a context switch (since the exception could
     372 * hit a IRQ protected section of code).
     373 * We simply let this test return 0 so that ppc_exc_wrapup is
     374 * never called after handling a machine-check.
     375 */
     376        .macro TEST_LOCK_mchk _SRR0 _FLVR
     377        crxor   EQ(cr4), EQ(cr4), EQ(cr4)
     378        .endm
     379#endif
    346380
    347381
     
    410444
    411445        /* test lower-priority locks; result in (non-volatile) cr4 */
    412         TEST_LOCK_\_PRI _SRR0=\_SRR0
     446        TEST_LOCK_\_PRI _SRR0=\_SRR0 _FLVR=\_FLVR
    413447
    414448        /* Peform stack switch if necessary */
  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_bspsupp.h

    r38f5e61 r8bac485  
    5656 */
    5757extern uint32_t ppc_exc_msr_irq_mask;
     58
     59/*
     60 * Cache size of the interrupt stack in a SDA variable
     61 */
     62extern uint32_t ppc_exc_intr_stack_size;
     63
     64/*
     65 * This variable defines the semantics of asynchronous
     66 * critical exceptions ("critical interrupts")
     67 * on BookE-style CPUs.
     68 *
     69 * There are the following ways of using these interrupts
     70 *
     71 *  1) permanently disabled; no support
     72 *  2) permanently enabled; handlers for critical interrupts
     73 *     MUST NOT use any RTEMS primitives at all. They cannot
     74 *     directly e.g., release a semaphore.
     75 *  3) enabled/disabled by the OS during critical sections.
     76 *     In this scenario critical interrupts are not much
     77 *     different from 'normal' interrupts but handlers may
     78 *     safely use RTEMS primitives (i.e., the subset which
     79 *     is OK to use from ISR context).
     80 *
     81 * The BSP (or application) may initialize this
     82 * variable PRIOR to calling 'initialize_exceptions'
     83 * to any of the following values:
     84 *
     85 * NOTE: so far, OS_SUPPORT is not supported by the cpukit
     86 *       yet since the IRQ/enabling-disabling primitives
     87 *       do not mask MSR_CE yet.
     88 */
     89#define PPC_EXC_CRIT_NO_OS_SUPPORT       1
     90#define PPC_EXC_CRIT_OS_SUPPORT      0
     91#define PPC_EXC_CRIT_DISABLED      (-1)
     92
     93extern int32_t ppc_exc_crit_always_enabled;
    5894
    5995/* (See README under CAVEATS). During initialization
  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/ppc_exc_hdl.c

    r38f5e61 r8bac485  
    5353 */
    5454uint32_t ppc_exc_msr_bits     = MSR_IR | MSR_DR | MSR_RI;
     55
     56uint32_t ppc_exc_intr_stack_size = 0;
     57
     58int32_t ppc_exc_crit_always_enabled = PPC_EXC_CRIT_NO_OS_SUPPORT;
    5559
    5660
  • c/src/lib/libcpu/powerpc/new-exceptions/bspsupport/vectors_init.c

    r38f5e61 r8bac485  
    338338        ppc_exc_msr_bits = _read_MSR() & ( MSR_DR | MSR_IR | MSR_RI );
    339339
     340        /* Cache size of the interrupt stack in a SDA variable */
     341        ppc_exc_intr_stack_size = rtems_configuration_get_interrupt_stack_size();
     342
    340343        /* Copy into a SDA variable that is easy to access from
    341344         * assembly code
     
    343346        if ( ppc_cpu_is_bookE() ) {
    344347                ppc_exc_msr_irq_mask = MSR_EE | MSR_CE | MSR_DE ;
     348                switch (ppc_exc_crit_always_enabled) {
     349                        case PPC_EXC_CRIT_NO_OS_SUPPORT:
     350                                _write_MSR(_read_MSR() | (MSR_CE | MSR_DE));
     351                        break;
     352
     353                        case PPC_EXC_CRIT_OS_SUPPORT:
     354                                printk("ppc_exc: PPC_EXC_CRIT_OS_SUPPORT not yet implemented\n");
     355                                /* fall thru */
     356
     357                        case PPC_EXC_CRIT_DISABLED:
     358                        default:
     359                                ppc_exc_crit_always_enabled = PPC_EXC_CRIT_DISABLED;
     360                                _write_MSR(_read_MSR() & ~(MSR_CE | MSR_DE));
     361                        break;
     362                }
    345363        } else {
    346364                ppc_exc_msr_irq_mask = MSR_EE ;
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