Ignore:
Timestamp:
Dec 21, 1999, 2:27:52 PM (21 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
db3e0108
Parents:
3ad7602e
Message:

Patch rtems-rc-19991203-5.diff from Ralf Corsepius <corsepiu@…>
which cleans up and merges some Hitachi SH-2 modifications from
John Mills <jmills@…>.

Location:
c/src/lib/libcpu/sh/sh7045/include
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/sh/sh7045/include/io_types.h

    r3ad7602e r8b91282  
    1717 *  http://www.OARcorp.com/rtems/license.html.
    1818 *
    19  *      John M. Mills (jmills@tga.com)
    20  *      TGA Technologies, Inc.
    21  *  100 Pinnacle Way, Suite 140
    22  *      Norcross, GA 30071 U.S.A.
     19 *      John M. Mills (jmills@tga.com)
     20 *      TGA Technologies, Inc.
     21 *      100 Pinnacle Way, Suite 140
     22 *      Norcross, GA 30071 U.S.A.
    2323 *
    24  *      This modified file may be copied and distributed in accordance
    25  *      the above-referenced license. It is provided for critique and
    26  *      developmental purposes without any warranty nor representation
    27  *      by the authors or by TGA Technologies.
     24 *      This modified file may be copied and distributed in accordance
     25 *      the above-referenced license. It is provided for critique and
     26 *      developmental purposes without any warranty nor representation
     27 *      by the authors or by TGA Technologies.
    2828 *
    2929 *  $Id$
     
    4444
    4545typedef struct {
    46         portNo          line;
    47         int                             speed_ix;
    48         dataBits        dBits;
    49         int                             parEn; 
    50         parity          par;
    51         int                             mulPro;
    52         stopBits        sBits;
     46  portNo   line;
     47  int      speed_ix;
     48  dataBits dBits;
     49  int      parEn;       
     50  parity   par;
     51  int      mulPro;
     52  stopBits sBits;
    5353} sci_setup_t;
    5454
  • c/src/lib/libcpu/sh/sh7045/include/iosh7045.h

    r3ad7602e r8b91282  
    308308#define PFC_PECR1  (REG_BASE + 0x03B8) /* Port E Ctr. Reg. 1 */
    309309#define PFC_PECR2  (REG_BASE + 0x03BA) /* Port E Ctr. Reg. 2 */
    310 #define PFC_IFCR        (REG_BASE + 0x03C8) /* short */
     310#define PFC_IFCR   (REG_BASE + 0x03C8) /* short */
    311311
    312312/*Compare/Match Timer*/
  • c/src/lib/libcpu/sh/sh7045/include/sh7_pfc.h

    r3ad7602e r8b91282  
    3131
    3232/*
     33 * Port A IO Registers (PAIORH, PAIORL)
     34 *    1 => OUTPUT
     35 *    0 => INPUT
     36 */
     37#define PAIORH     PFC_PAIORH
     38#define PAIORL     PFC_PAIORL
     39
     40/* PAIORH */
     41#define PA23IOR    0x0080
     42#define PA22IOR    0x0040
     43#define PA21IOR    0x0020
     44#define PA20IOR    0x0010
     45#define PA19IOR    0x0008
     46#define PA18IOR    0x0004
     47#define PA17IOR    0x0002
     48#define PA16IOR    0x0001
     49
     50/* PAIORL */
     51#define PA15IOR    0x8000
     52#define PA14IOR    0x4000
     53#define PA13IOR    0x2000
     54#define PA12IOR    0x1000
     55#define PA11IOR    0x0800
     56#define PA10IOR    0x0400
     57#define PA9IOR     0x0200
     58#define PA8IOR     0x0100
     59#define PA7IOR     0x0080
     60#define PA6IOR     0x0040
     61#define PA5IOR     0x0020
     62#define PA4IOR     0x0010
     63#define PA3IOR     0x0008
     64#define PA2IOR     0x0004
     65#define PA1IOR     0x0002
     66#define PA0IOR     0x0001
     67
     68/*
     69 * Port A Control Registers (PACRH, PACRL1, PACRL2)
     70 * and mode bits
     71 */
     72#define PACRH      PFC_PACRH
     73#define PACRL1     PFC_PACRL1
     74#define PACRL2     PFC_PACRL2
     75
     76/* PACRH */
     77#define PA23MD0    0x4000
     78#define PA22MD0    0x1000
     79#define PA21MD0    0x0400
     80#define PA20MD0    0x0100
     81#define PA19MD1    0x0080
     82#define PA19MD0    0x0040
     83#define PA18MD1    0x0020
     84#define PA18MD0    0x0010
     85#define PA17MD0    0x0004
     86#define PA16MD0    0x0001
     87
     88/* PACRL1 */
     89#define PA15MD0    0x4000
     90#define PA14MD0    0x1000
     91#define PA13MD0    0x0400
     92#define PA12MD0    0x0100
     93#define PA11MD0    0x0040
     94#define PA10MD0    0x0010
     95#define PA9MD1     0x0008
     96#define PA9MD0     0x0004
     97#define PA8MD1     0x0002
     98#define PA8MD0     0x0001
     99
     100/* PACRL2 */
     101#define PA7MD1     0x8000
     102#define PA7MD0     0x4000
     103#define PA6MD1     0x2000
     104#define PA6MD0     0x1000
     105#define PA5MD1     0x0800
     106#define PA5MD0     0x0400
     107#define PA4MD0     0x0100
     108#define PA3MD0     0x0040
     109#define PA2MD1     0x0020
     110#define PA2MD0     0x0010
     111#define PA1MD0     0x0004
     112#define PA0MD0     0x0001
     113
     114#define PA_TXD1    PA4MD0
     115#define PA_RXD1    PA3MD0
     116#define PA_TXD0    PA1MD0
     117#define PA_RXD0    PA0MD0
     118
     119/*
    33120 * Port B IO Register (PBIOR)
    34121 */
    35 #define PBIOR           PFC_PBIOR
    36 #define PB15IOR         0x8000
    37 #define PB14IOR         0x4000
    38 #define PB13IOR         0x2000
    39 #define PB12IOR         0x1000
    40 #define PB11IOR         0x0800
    41 #define PB10IOR         0x0400
    42 #define PB9IOR          0x0200
    43 #define PB8IOR          0x0100
    44 #define PB7IOR          0x0080
    45 #define PB6IOR          0x0040
    46 #define PB5IOR          0x0020
    47 #define PB4IOR          0x0010
    48 #define PB3IOR          0x0008
    49 #define PB2IOR          0x0004
    50 #define PB1IOR          0x0002
    51 #define PB0IOR          0x0001
     122#define PBIOR      PFC_PBIOR
     123#define PB15IOR    0x8000
     124#define PB14IOR    0x4000
     125#define PB13IOR    0x2000
     126#define PB12IOR    0x1000
     127#define PB11IOR    0x0800
     128#define PB10IOR    0x0400
     129#define PB9IOR     0x0200
     130#define PB8IOR     0x0100
     131#define PB7IOR     0x0080
     132#define PB6IOR     0x0040
     133#define PB5IOR     0x0020
     134#define PB4IOR     0x0010
     135#define PB3IOR     0x0008
     136#define PB2IOR     0x0004
     137#define PB1IOR     0x0002
     138#define PB0IOR     0x0001
    52139
    53140/*
    54141 * Port B Control Register (PBCR1)
    55142 */
    56 #define PBCR1           PFC_PBCR1
    57 #define PB15MD1         0x8000
    58 #define PB15MD0         0x4000
    59 #define PB14MD1         0x2000
    60 #define PB14MD0         0x1000
    61 #define PB13MD1         0x0800
    62 #define PB13MD0         0x0400
    63 #define PB12MD1         0x0200
    64 #define PB12MD0         0x0100
    65 #define PB11MD1         0x0080
    66 #define PB11MD0         0x0040
    67 #define PB10MD1         0x0020
    68 #define PB10MD0         0x0010
    69 #define PB9MD1          0x0008
    70 #define PB9MD0          0x0004
    71 #define PB8MD1          0x0002
    72 #define PB8MD0          0x0001
    73 
    74 #define PB15MD          PB15MD1|PB14MD0
    75 #define PB14MD          PB14MD1|PB14MD0
    76 #define PB13MD          PB13MD1|PB13MD0
    77 #define PB12MD          PB12MD1|PB12MD0
    78 #define PB11MD          PB11MD1|PB11MD0
    79 #define PB10MD          PB10MD1|PB10MD0
    80 #define PB9MD           PB9MD1|PB9MD0
    81 #define PB8MD           PB8MD1|PB8MD0
    82 
    83 #define PB_TXD1         PB11MD1
    84 #define PB_RXD1         PB10MD1
    85 #define PB_TXD0         PB9MD1
    86 #define PB_RXD0         PB8MD1
     143#define PBCR1      PFC_PBCR1
     144#define PB15MD1    0x8000
     145#define PB15MD0    0x4000
     146#define PB14MD1    0x2000
     147#define PB14MD0    0x1000
     148#define PB13MD1    0x0800
     149#define PB13MD0    0x0400
     150#define PB12MD1    0x0200
     151#define PB12MD0    0x0100
     152#define PB11MD1    0x0080
     153#define PB11MD0    0x0040
     154#define PB10MD1    0x0020
     155#define PB10MD0    0x0010
     156#define PB9MD1     0x0008
     157#define PB9MD0     0x0004
     158#define PB8MD1     0x0002
     159#define PB8MD0     0x0001
     160
     161#define PB15MD     PB15MD1|PB14MD0
     162#define PB14MD     PB14MD1|PB14MD0
     163#define PB13MD     PB13MD1|PB13MD0
     164#define PB12MD     PB12MD1|PB12MD0
     165#define PB11MD     PB11MD1|PB11MD0
     166#define PB10MD     PB10MD1|PB10MD0
     167#define PB9MD      PB9MD1|PB9MD0
     168#define PB8MD      PB8MD1|PB8MD0
     169
     170#define PB_TXD1    PB11MD1
     171#define PB_RXD1    PB10MD1
     172#define PB_TXD0    PB9MD1
     173#define PB_RXD0    PB8MD1
    87174
    88175/*
    89176 * Port B Control Register (PBCR2)
    90177 */
    91 #define PBCR2   PFC_PBCR2
    92 #define PB7MD1  0x8000
    93 #define PB7MD0  0x4000
    94 #define PB6MD1  0x2000
    95 #define PB6MD0  0x1000
    96 #define PB5MD1  0x0800
    97 #define PB5MD0  0x0400
    98 #define PB4MD1  0x0200
    99 #define PB4MD0  0x0100
    100 #define PB3MD1  0x0080
    101 #define PB3MD0  0x0040
    102 #define PB2MD1  0x0020
    103 #define PB2MD0  0x0010
    104 #define PB1MD1  0x0008
    105 #define PB1MD0  0x0004
    106 #define PB0MD1  0x0002
    107 #define PB0MD0  0x0001
     178#define PBCR2      PFC_PBCR2
     179#define PB7MD1     0x8000
     180#define PB7MD0     0x4000
     181#define PB6MD1     0x2000
     182#define PB6MD0     0x1000
     183#define PB5MD1     0x0800
     184#define PB5MD0     0x0400
     185#define PB4MD1     0x0200
     186#define PB4MD0     0x0100
     187#define PB3MD1     0x0080
     188#define PB3MD0     0x0040
     189#define PB2MD1     0x0020
     190#define PB2MD0     0x0010
     191#define PB1MD1     0x0008
     192#define PB1MD0     0x0004
     193#define PB0MD1     0x0002
     194#define PB0MD0     0x0001
    108195       
    109 #define PB7MD   PB7MD1|PB7MD0
    110 #define PB6MD   PB6MD1|PB6MD0
    111 #define PB5MD   PB5MD1|PB5MD0
    112 #define PB4MD   PB4MD1|PB4MD0
    113 #define PB3MD   PB3MD1|PB3MD0
    114 #define PB2MD   PB2MD1|PB2MD0
    115 #define PB1MD   PB1MD1|PB1MD0
    116 #define PB0MD   PB0MD1|PB0MD0
     196#define PB7MD      PB7MD1|PB7MD0
     197#define PB6MD      PB6MD1|PB6MD0
     198#define PB5MD      PB5MD1|PB5MD0
     199#define PB4MD      PB4MD1|PB4MD0
     200#define PB3MD      PB3MD1|PB3MD0
     201#define PB2MD      PB2MD1|PB2MD0
     202#define PB1MD      PB1MD1|PB1MD0
     203#define PB0MD      PB0MD1|PB0MD0
    117204
    118205#endif /* _sh7_pfc_h */
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