Changeset 8b91282 in rtems


Ignore:
Timestamp:
Dec 21, 1999, 2:27:52 PM (20 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
db3e0108
Parents:
3ad7602e
Message:

Patch rtems-rc-19991203-5.diff from Ralf Corsepius <corsepiu@…>
which cleans up and merges some Hitachi SH-2 modifications from
John Mills <jmills@…>.

Files:
8 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/sh/rtems/score/iosh7045.h

    r3ad7602e r8b91282  
    308308#define PFC_PECR1  (REG_BASE + 0x03B8) /* Port E Ctr. Reg. 1 */
    309309#define PFC_PECR2  (REG_BASE + 0x03BA) /* Port E Ctr. Reg. 2 */
    310 #define PFC_IFCR        (REG_BASE + 0x03C8) /* short */
     310#define PFC_IFCR   (REG_BASE + 0x03C8) /* short */
    311311
    312312/*Compare/Match Timer*/
  • c/src/lib/libbsp/sh/gensh2/startup/bspstart.c

    r3ad7602e r8b91282  
    9292     startup code, rtems startup code or here.
    9393   */
     94
     95#ifndef START_HW_INIT
     96  /* board hardware setup here, or from 'start.S' */
    9497  hw_initialize();
     98#endif
    9599
    96100  /*
  • c/src/lib/libbsp/sh/gensh2/startup/hw_init.c

    r3ad7602e r8b91282  
    11/*
    22 *  hw_init.c: set up sh7045F internal subunits
     3 *             Pin and memory assignments assume
     4 *             target is Hitachi SH7045F EVB ("lcevb")
    35 *
    46 *  Author: John M. Mills (jmills@tga.com)
     
    7072
    7173#ifdef STANDALONE_EVB
     74        /* FIXME: replace 'magic numbers' */
     75
    7276        write16(0x2020, BSC_BCR1);  /* Bus width access - 32-bit on CS1 */
    7377        write16(0xF3DD, BSC_BCR2);  /* Idle cycles CS3-CS0 - 0 idle cycles*/
     
    9094        write16(0x0005, PFC_PACRL2); /* Pin function controller - Tx0, Rx0 */
    9195
    92         /* SCI0 */
    93 /* FIXME: This doesn't belong here */
    94         write8(0x00, SCI_SCR0);     /* Clear SCR */
    95         write8(0x00, SCI_SMR0);     /* Clear SMR */
    96         write8(0x5F, SCI_BRR0);     /* Default 9600 baud rate */
    97 #if 0
    98         write8(0x1F, SCI_BRR0);    /* 28800 baud */
    99 #endif
    100 /* FIXME: Will get optimized away */
    101         for(a=0;a<00000L;a++);      /* One bit delay */
    102         write8(0x30, SCI_SCR0);     /* Enable clock output */
    103         temp8 = read8(SCI_RDR0);    /* Clear out old input */
    104 
     96        write16(0x00, PFC_PACRL2); /* default disconnects all I/O */
     97                                   /* pins; connected by DEVICE_open() */
    10598#endif
    10699
    107         /* default hardware setup */
     100        /* default hardware setup for SH7045F EVB */
    108101
    109102        /* PFC: General I/O except pin 13 (reset): */
     
    114107        write16(0x00, PFC_PECR2);
    115108
    116         /* P5 out, all other pins in: */
     109        /* P5 (LED) out, all other pins in: */
    117110        temp16 = read16(PFC_PEIOR) | 0x0020;
    118111        write16(temp16, PFC_PEIOR);
    119112
    120         /* PFC - pins for Tx0-1, Rx0-1: */
    121         temp16 = read16(PFC_PACRL2) | 0x0145;
    122         write16(temp16, PFC_PACRL2);
    123 
    124         /* SCI1 - Default RTEMS console */
    125 #if FIXME
    126         /* write8(0x00, SCI_SCR1);      /* Clear SCR */
    127         /* write8(0x00, SCI_SMR1);      /* Clear SMR */
    128         /* write8(0x5F, SCI_BRR1);      /* Default 9600 baud rate */
    129         /* write8(0x1F, SCI_BRR1);    /* 28800 baud */
    130 /* FIXME: Will get optimized away */
    131         /* for(a=0;a<10000L;a++);       /* One bit delay */
    132         /* write8(0x30, SCI_SCR1);      /* Enable clock output */
    133         /* temp8 = read8(SCI_RDR1);      /* Clear out old input */
    134 
    135         /* INTC setup */
    136         /* set_interrupt_mask(0);       /* enable interrupts */
    137         /* INTC_IPRF &= ~(SCI1_IPMSK);  /* set SIO1 priority at INTC */
    138         /* INTC_IPRF |= SCI1_LOWIP;     */
    139 #endif
    140113}
  • c/src/lib/libcpu/sh/sh7045/include/io_types.h

    r3ad7602e r8b91282  
    1717 *  http://www.OARcorp.com/rtems/license.html.
    1818 *
    19  *      John M. Mills (jmills@tga.com)
    20  *      TGA Technologies, Inc.
    21  *  100 Pinnacle Way, Suite 140
    22  *      Norcross, GA 30071 U.S.A.
     19 *      John M. Mills (jmills@tga.com)
     20 *      TGA Technologies, Inc.
     21 *      100 Pinnacle Way, Suite 140
     22 *      Norcross, GA 30071 U.S.A.
    2323 *
    24  *      This modified file may be copied and distributed in accordance
    25  *      the above-referenced license. It is provided for critique and
    26  *      developmental purposes without any warranty nor representation
    27  *      by the authors or by TGA Technologies.
     24 *      This modified file may be copied and distributed in accordance
     25 *      the above-referenced license. It is provided for critique and
     26 *      developmental purposes without any warranty nor representation
     27 *      by the authors or by TGA Technologies.
    2828 *
    2929 *  $Id$
     
    4444
    4545typedef struct {
    46         portNo          line;
    47         int                             speed_ix;
    48         dataBits        dBits;
    49         int                             parEn; 
    50         parity          par;
    51         int                             mulPro;
    52         stopBits        sBits;
     46  portNo   line;
     47  int      speed_ix;
     48  dataBits dBits;
     49  int      parEn;       
     50  parity   par;
     51  int      mulPro;
     52  stopBits sBits;
    5353} sci_setup_t;
    5454
  • c/src/lib/libcpu/sh/sh7045/include/iosh7045.h

    r3ad7602e r8b91282  
    308308#define PFC_PECR1  (REG_BASE + 0x03B8) /* Port E Ctr. Reg. 1 */
    309309#define PFC_PECR2  (REG_BASE + 0x03BA) /* Port E Ctr. Reg. 2 */
    310 #define PFC_IFCR        (REG_BASE + 0x03C8) /* short */
     310#define PFC_IFCR   (REG_BASE + 0x03C8) /* short */
    311311
    312312/*Compare/Match Timer*/
  • c/src/lib/libcpu/sh/sh7045/include/sh7_pfc.h

    r3ad7602e r8b91282  
    3131
    3232/*
     33 * Port A IO Registers (PAIORH, PAIORL)
     34 *    1 => OUTPUT
     35 *    0 => INPUT
     36 */
     37#define PAIORH     PFC_PAIORH
     38#define PAIORL     PFC_PAIORL
     39
     40/* PAIORH */
     41#define PA23IOR    0x0080
     42#define PA22IOR    0x0040
     43#define PA21IOR    0x0020
     44#define PA20IOR    0x0010
     45#define PA19IOR    0x0008
     46#define PA18IOR    0x0004
     47#define PA17IOR    0x0002
     48#define PA16IOR    0x0001
     49
     50/* PAIORL */
     51#define PA15IOR    0x8000
     52#define PA14IOR    0x4000
     53#define PA13IOR    0x2000
     54#define PA12IOR    0x1000
     55#define PA11IOR    0x0800
     56#define PA10IOR    0x0400
     57#define PA9IOR     0x0200
     58#define PA8IOR     0x0100
     59#define PA7IOR     0x0080
     60#define PA6IOR     0x0040
     61#define PA5IOR     0x0020
     62#define PA4IOR     0x0010
     63#define PA3IOR     0x0008
     64#define PA2IOR     0x0004
     65#define PA1IOR     0x0002
     66#define PA0IOR     0x0001
     67
     68/*
     69 * Port A Control Registers (PACRH, PACRL1, PACRL2)
     70 * and mode bits
     71 */
     72#define PACRH      PFC_PACRH
     73#define PACRL1     PFC_PACRL1
     74#define PACRL2     PFC_PACRL2
     75
     76/* PACRH */
     77#define PA23MD0    0x4000
     78#define PA22MD0    0x1000
     79#define PA21MD0    0x0400
     80#define PA20MD0    0x0100
     81#define PA19MD1    0x0080
     82#define PA19MD0    0x0040
     83#define PA18MD1    0x0020
     84#define PA18MD0    0x0010
     85#define PA17MD0    0x0004
     86#define PA16MD0    0x0001
     87
     88/* PACRL1 */
     89#define PA15MD0    0x4000
     90#define PA14MD0    0x1000
     91#define PA13MD0    0x0400
     92#define PA12MD0    0x0100
     93#define PA11MD0    0x0040
     94#define PA10MD0    0x0010
     95#define PA9MD1     0x0008
     96#define PA9MD0     0x0004
     97#define PA8MD1     0x0002
     98#define PA8MD0     0x0001
     99
     100/* PACRL2 */
     101#define PA7MD1     0x8000
     102#define PA7MD0     0x4000
     103#define PA6MD1     0x2000
     104#define PA6MD0     0x1000
     105#define PA5MD1     0x0800
     106#define PA5MD0     0x0400
     107#define PA4MD0     0x0100
     108#define PA3MD0     0x0040
     109#define PA2MD1     0x0020
     110#define PA2MD0     0x0010
     111#define PA1MD0     0x0004
     112#define PA0MD0     0x0001
     113
     114#define PA_TXD1    PA4MD0
     115#define PA_RXD1    PA3MD0
     116#define PA_TXD0    PA1MD0
     117#define PA_RXD0    PA0MD0
     118
     119/*
    33120 * Port B IO Register (PBIOR)
    34121 */
    35 #define PBIOR           PFC_PBIOR
    36 #define PB15IOR         0x8000
    37 #define PB14IOR         0x4000
    38 #define PB13IOR         0x2000
    39 #define PB12IOR         0x1000
    40 #define PB11IOR         0x0800
    41 #define PB10IOR         0x0400
    42 #define PB9IOR          0x0200
    43 #define PB8IOR          0x0100
    44 #define PB7IOR          0x0080
    45 #define PB6IOR          0x0040
    46 #define PB5IOR          0x0020
    47 #define PB4IOR          0x0010
    48 #define PB3IOR          0x0008
    49 #define PB2IOR          0x0004
    50 #define PB1IOR          0x0002
    51 #define PB0IOR          0x0001
     122#define PBIOR      PFC_PBIOR
     123#define PB15IOR    0x8000
     124#define PB14IOR    0x4000
     125#define PB13IOR    0x2000
     126#define PB12IOR    0x1000
     127#define PB11IOR    0x0800
     128#define PB10IOR    0x0400
     129#define PB9IOR     0x0200
     130#define PB8IOR     0x0100
     131#define PB7IOR     0x0080
     132#define PB6IOR     0x0040
     133#define PB5IOR     0x0020
     134#define PB4IOR     0x0010
     135#define PB3IOR     0x0008
     136#define PB2IOR     0x0004
     137#define PB1IOR     0x0002
     138#define PB0IOR     0x0001
    52139
    53140/*
    54141 * Port B Control Register (PBCR1)
    55142 */
    56 #define PBCR1           PFC_PBCR1
    57 #define PB15MD1         0x8000
    58 #define PB15MD0         0x4000
    59 #define PB14MD1         0x2000
    60 #define PB14MD0         0x1000
    61 #define PB13MD1         0x0800
    62 #define PB13MD0         0x0400
    63 #define PB12MD1         0x0200
    64 #define PB12MD0         0x0100
    65 #define PB11MD1         0x0080
    66 #define PB11MD0         0x0040
    67 #define PB10MD1         0x0020
    68 #define PB10MD0         0x0010
    69 #define PB9MD1          0x0008
    70 #define PB9MD0          0x0004
    71 #define PB8MD1          0x0002
    72 #define PB8MD0          0x0001
    73 
    74 #define PB15MD          PB15MD1|PB14MD0
    75 #define PB14MD          PB14MD1|PB14MD0
    76 #define PB13MD          PB13MD1|PB13MD0
    77 #define PB12MD          PB12MD1|PB12MD0
    78 #define PB11MD          PB11MD1|PB11MD0
    79 #define PB10MD          PB10MD1|PB10MD0
    80 #define PB9MD           PB9MD1|PB9MD0
    81 #define PB8MD           PB8MD1|PB8MD0
    82 
    83 #define PB_TXD1         PB11MD1
    84 #define PB_RXD1         PB10MD1
    85 #define PB_TXD0         PB9MD1
    86 #define PB_RXD0         PB8MD1
     143#define PBCR1      PFC_PBCR1
     144#define PB15MD1    0x8000
     145#define PB15MD0    0x4000
     146#define PB14MD1    0x2000
     147#define PB14MD0    0x1000
     148#define PB13MD1    0x0800
     149#define PB13MD0    0x0400
     150#define PB12MD1    0x0200
     151#define PB12MD0    0x0100
     152#define PB11MD1    0x0080
     153#define PB11MD0    0x0040
     154#define PB10MD1    0x0020
     155#define PB10MD0    0x0010
     156#define PB9MD1     0x0008
     157#define PB9MD0     0x0004
     158#define PB8MD1     0x0002
     159#define PB8MD0     0x0001
     160
     161#define PB15MD     PB15MD1|PB14MD0
     162#define PB14MD     PB14MD1|PB14MD0
     163#define PB13MD     PB13MD1|PB13MD0
     164#define PB12MD     PB12MD1|PB12MD0
     165#define PB11MD     PB11MD1|PB11MD0
     166#define PB10MD     PB10MD1|PB10MD0
     167#define PB9MD      PB9MD1|PB9MD0
     168#define PB8MD      PB8MD1|PB8MD0
     169
     170#define PB_TXD1    PB11MD1
     171#define PB_RXD1    PB10MD1
     172#define PB_TXD0    PB9MD1
     173#define PB_RXD0    PB8MD1
    87174
    88175/*
    89176 * Port B Control Register (PBCR2)
    90177 */
    91 #define PBCR2   PFC_PBCR2
    92 #define PB7MD1  0x8000
    93 #define PB7MD0  0x4000
    94 #define PB6MD1  0x2000
    95 #define PB6MD0  0x1000
    96 #define PB5MD1  0x0800
    97 #define PB5MD0  0x0400
    98 #define PB4MD1  0x0200
    99 #define PB4MD0  0x0100
    100 #define PB3MD1  0x0080
    101 #define PB3MD0  0x0040
    102 #define PB2MD1  0x0020
    103 #define PB2MD0  0x0010
    104 #define PB1MD1  0x0008
    105 #define PB1MD0  0x0004
    106 #define PB0MD1  0x0002
    107 #define PB0MD0  0x0001
     178#define PBCR2      PFC_PBCR2
     179#define PB7MD1     0x8000
     180#define PB7MD0     0x4000
     181#define PB6MD1     0x2000
     182#define PB6MD0     0x1000
     183#define PB5MD1     0x0800
     184#define PB5MD0     0x0400
     185#define PB4MD1     0x0200
     186#define PB4MD0     0x0100
     187#define PB3MD1     0x0080
     188#define PB3MD0     0x0040
     189#define PB2MD1     0x0020
     190#define PB2MD0     0x0010
     191#define PB1MD1     0x0008
     192#define PB1MD0     0x0004
     193#define PB0MD1     0x0002
     194#define PB0MD0     0x0001
    108195       
    109 #define PB7MD   PB7MD1|PB7MD0
    110 #define PB6MD   PB6MD1|PB6MD0
    111 #define PB5MD   PB5MD1|PB5MD0
    112 #define PB4MD   PB4MD1|PB4MD0
    113 #define PB3MD   PB3MD1|PB3MD0
    114 #define PB2MD   PB2MD1|PB2MD0
    115 #define PB1MD   PB1MD1|PB1MD0
    116 #define PB0MD   PB0MD1|PB0MD0
     196#define PB7MD      PB7MD1|PB7MD0
     197#define PB6MD      PB6MD1|PB6MD0
     198#define PB5MD      PB5MD1|PB5MD0
     199#define PB4MD      PB4MD1|PB4MD0
     200#define PB3MD      PB3MD1|PB3MD0
     201#define PB2MD      PB2MD1|PB2MD0
     202#define PB1MD      PB1MD1|PB1MD0
     203#define PB0MD      PB0MD1|PB0MD0
    117204
    118205#endif /* _sh7_pfc_h */
  • c/src/lib/libcpu/sh/sh7045/sci/sci.c

    r3ad7602e r8b91282  
    120120} /* sh_sci_outbyte_polled */
    121121
    122 /* Initial version calls polled output driver and blocks */
     122/*
     123 * Initial version calls polled output driver and blocks
     124 */
    123125void outbyte(
    124126  rtems_device_minor_number  minor,
     
    187189/*  sh_sci_initialize
    188190 *
    189  *  This routine initializes the sh_sci IO driver.
    190  *
    191  *  Input parameters: NONE
     191 *  This routine initializes (registers) the sh_sci IO drivers.
     192 *
     193 *  Input parameters: ignored
    192194 *
    193195 *  Output parameters:  NONE
    194196 *
    195  *  Return values:
     197 *  Return values: RTEMS_SUCCESSFUL
     198 *   if all sci[...] register, else calls
     199 *   rtems_fatal_error_occurred(status)
     200 *
    196201 */
    197202
     
    201206  void                      *arg )
    202207{
    203   int a;
    204   unsigned16 temp16;
    205208  rtems_device_driver status ;
    206 
    207   /* register devices */ 
    208   for ( a = 0 ; a < 2 ; a++ )
     209  rtems_device_minor_number     i;
     210 
     211  /*
     212   * register all possible devices.
     213   * the initialization of the hardware is done by sci_open
     214   */
     215
     216  for ( i = 0 ; i < SCI_MINOR_DEVICES ; i++ )
    209217  {
    210218    status = rtems_io_register_name(
    211       sci_device[a].name,
     219      sci_device[i].name,
    212220      major,
    213       sci_device[a].minor );
     221      sci_device[i].minor );
    214222    if (status != RTEMS_SUCCESSFUL)
    215223      rtems_fatal_error_occurred(status);
    216224  }
    217225
    218   /* default hardware setup */
    219 
    220   /* general setup */
    221   temp16 = read16(PFC_PECR1) | 0x0800;  /* General I/O except pin 13 (reset) */
    222   write16(temp16, PFC_PECR1);
    223   write16(0x00, PFC_PECR2);     /* All I/O lines bits 7-0 */
    224   temp16 = read16(PFC_PEIOR) | 0x0020;  /* P5 to out, all other pins in */
    225   write16(temp16, PFC_PEIOR);
    226 
    227   temp16 = read16(PFC_PACRL2) | 0x0145;  /* PFC - pins for Tx0-1, Rx0-1 */
    228   write16(temp16, PFC_PACRL2);
    229  
     226  /* non-default hardware setup occurs in sh_sci_open() */
     227
    230228  return RTEMS_SUCCESSFUL;
    231229}
     
    234232/*
    235233 *  Open entry point
     234 *   Sets up port and pins for selected sci.
     235 *   SCI0 setup is conditional on STANDALONE_EVB == 1
    236236 */
    237237
     
    242242{
    243243  unsigned8 temp8;
     244  unsigned16 temp16;
    244245  unsigned char smr ;
    245246  unsigned char brr ;
     
    247248  unsigned      a ;
    248249 
     250 /* check for valid minor number */
     251   if(( minor > ( SCI_MINOR_DEVICES -1 )) || ( minor < 0 ))
     252   {
     253     return RTEMS_INVALID_NUMBER;
     254   }
     255 
    249256  /* device already opened */
    250257  if ( sci_device[minor].opened > 0 )
    251258  {
    252259    sci_device[minor].opened++ ;
    253 
    254260    return RTEMS_SUCCESSFUL ;
    255261  }
    256262   
    257   /* retrieve brr and smr values */
    258   _sci_get_brparms( sci_device[minor].cflags, &smr, &brr );
    259  
    260   if (minor == 0) {
    261     write8(0x00, SCI_SCR0);     /* Clear SCR */
    262     write8(smr, SCI_SMR0);      /* Clear SMR */
    263     write8(brr, SCI_BRR0);      /* Default 9600 baud rate */
    264 #if 0
    265     write8(0x1F, SCI_BRR0);    /* 28800 baud */
    266 #endif
    267 /* FIXME: Will get optimized away */
    268     for(a=0;a<10000L;a++);      /* One bit delay */
    269     write8(0x30, SCI_SCR0);     /* Enable clock output */
    270     temp8 = read8(SCI_RDR0);      /* Clear out old input */
    271 
    272   } else {
    273     write8(0x00, SCI_SCR1);     /* Clear SCR */
    274     write8(smr, SCI_SMR1);      /* Clear SMR */
    275     write8(brr, SCI_BRR1);      /* Default 9600 baud rate */
    276 #if 0
    277     write8(0x1F, SCI_BRR1);    /* 28800 baud */
    278 #endif
    279 /* FIXME: Will get optimized away */
    280     for(a=0;a<10000L;a++);      /* One bit delay */
    281     write8(0x30, SCI_SCR1);     /* Enable clock output */
    282     temp8 = read8(SCI_RDR1);      /* Clear out old input */
    283   } 
     263  /* enable I/O pins */
     264
     265  if ((minor == 0) && (STANDALONE_EVB == 1)) {
     266    temp16 = read16(PFC_PACRL2) &          /* disable SCK0, Tx0, Rx0 */
     267      ~(PA2MD1 | PA2MD0 | PA1MD0 | PA0MD0);
     268    temp16 |= (PA_TXD0 | PA_RXD0);       /* assign pins for Tx0, Rx0 */
     269    write16(temp16, PFC_PACRL2);
     270   
     271  } else if (minor == 1) { 
     272    temp16 = read16(PFC_PACRL2) &           /* disable SCK1, Tx1, Rx1 */
     273      ~(PA5MD1 | PA5MD0 | PA4MD0 | PA3MD0);
     274    temp16 |= (PA_TXD1 | PA_RXD1);        /* assign pins for Tx1, Rx1 */
     275    write16(temp16, PFC_PACRL2);
     276
     277  } /* add other devices and pins as req'd. */
     278
     279  /* set up SCI registers */
     280  if ((minor != 0) || (STANDALONE_EVB == 1)) {
     281    write8(0x00, sci_device[minor].addr + SCI_SCR);      /* Clear SCR */
     282                                                   /* set SCR and BRR */
     283    _sci_set_cflags( &sci_device[minor], sci_device[minor].cflags );
     284
     285    for(a=0; a < 10000L; a++) {                      /* One-bit delay */
     286      asm volatile ("nop");
     287    }
     288
     289    write8((SCI_RE | SCI_TE),              /* enable async. Tx and Rx */
     290           sci_device[minor].addr + SCI_SCR);
     291    temp8 = read8(sci_device[minor].addr + SCI_RDR);   /* flush input */
     292   
     293    /* add interrupt setup if required */
     294
     295  }
    284296
    285297  sci_device[minor].opened++ ;
  • make/custom/gensh2.cfg

    r3ad7602e r8b91282  
    3030
    3131# debug flags: typically none, but we use -O1 as it produces better code
     32
    3233CFLAGS_DEBUG_V = -O1
    3334
     
    5152#     This switch compiles code to jump-start from FLASH, without a monitor
    5253#
     54#  START_HW_INIT
     55#     This switch selects whether 'hw_initialize()' is called from
     56#     'start.S' or from 'bsp_start()'
     57#
    5358
    5459define make-target-options
     
    5762        @echo "#define RTEMS_TEST_IO_STREAM 1"              >>$@
    5863        @echo "/* #define STANDALONE_EVB 1 */"              >>$@
     64        @echo "/* #define START_HW_INIT 1 */"               >>$@
    5965        @echo "/* #define RTEMS_DEBUG  1 */"                >>$@
    6066endef
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