Changeset 8b2ee37c in rtems


Ignore:
Timestamp:
Aug 19, 1998, 8:09:59 PM (21 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
26b5c77f
Parents:
7549e14
Message:

Patch from Eric Valette <valette@…>:

  • Use the "hlt" instruction for the Idle thread,
  • Optimise interrupt PATH leadding to thread wakeup,
  • Preparation for Intel exception management that should come before the end of the week...
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/i386/cpu.c

    r7549e14 r8b2ee37c  
    7676  return level;
    7777}
    78  
     78
     79void _CPU_Thread_Idle_body ()
     80{
     81  while(1){
     82    asm volatile ("hlt");
     83  }
     84}
     85     
  • c/src/exec/score/cpu/i386/cpu.h

    r7549e14 r8b2ee37c  
    6565#define CPU_USE_DEFERRED_FP_SWITCH       TRUE
    6666
    67 #define CPU_PROVIDES_IDLE_THREAD_BODY    FALSE
     67#define CPU_PROVIDES_IDLE_THREAD_BODY    YES
    6868#define CPU_STACK_GROWS_UP               FALSE
    6969#define CPU_STRUCTURE_ALIGNMENT
     
    102102} Context_Control_fp;
    103103
     104
    104105/*
    105106 *  The following structure defines the set of information saved
    106  *  on the current stack by RTEMS upon receipt of each interrupt.
     107 *  on the current stack by RTEMS upon receipt of execptions.
     108 *
     109 * idtIndex is either the interrupt number or the trap/exception number.
     110 * faultCode is the code pushed by the processor on some exceptions.
    107111 */
    108112
    109113typedef struct {
    110   unsigned32   TBD;   /* XXX Fix for this CPU */
    111 } CPU_Interrupt_frame;
     114
     115    unsigned32      edi,
     116                    esi,
     117                    ebp,
     118                    esp0,
     119                    ebx,
     120                    edx,
     121                    ecx,
     122                    eax,
     123                    idtIndex,
     124                    faultCode,
     125                    eip,
     126                    cs,
     127                    eflags;
     128}CPU_Exception_frame;
     129
     130/*
     131 *  The following structure defines the set of information saved
     132 *  on the current stack by RTEMS upon receipt of each interrupt
     133 *  that will lead to re-enter the kernel to signal the thread.
     134 */
     135
     136typedef CPU_Exception_frame CPU_Interrupt_frame;
    112137
    113138/*
  • c/src/lib/libbsp/i386/shared/irq/irq.c

    r7549e14 r8b2ee37c  
    357357    return 0;
    358358}   
     359
     360void _ThreadProcessSignalsFromIrq (CPU_Exception_frame* ctx)
     361{
     362  /*
     363   * If I understand the _Thread_Dispatch routine correctly
     364   * I do not see how this routine can be called given the
     365   * actual code. I plan to use this so far unused feature
     366   * to implement remote debugger ptrace("attach", ...)
     367   * command.
     368   */
     369  printk(" _ThreadProcessSignalsFromIrq called! mail valette@crf.canon.fr\n");
     370}
  • c/src/lib/libbsp/i386/shared/irq/irq_asm.s

    r7549e14 r8b2ee37c  
    1515#include <irq_asm.h>
    1616
    17 .set SAVED_REGS     , 32                   # space consumed by saved regs
    18 .set EIP_OFFSET     , SAVED_REGS           # offset of tasks eip
    19 .set CS_OFFSET      , EIP_OFFSET+4         # offset of tasks code segment
    20 .set EFLAGS_OFFSET  , CS_OFFSET+4          # offset of tasks eflags
    21        
    22 
    23 /*PAGE
    24  *  void _New_ISR_Displatch()
    25  *
    26  *  Entry point from the outermost interrupt service routine exit.
    27  *  The current stack is the supervisor mode stack.
    28  */
    29 
    30         PUBLIC (_New_ISR_Displatch)
    31 SYM (_New_ISR_Displatch):
    32 
    33         call      SYM (_Thread_Dispatch)   # invoke Dispatcher
    34 
    35        /*
    36         * BEGINNING OF DE-ESTABLISH SEGMENTS
    37         *
    38         *  NOTE:  Make sure there is code here if code is added to
    39         *         load the segment registers.
    40         *
    41         */
    42 
    43        /***** DE-ESTABLISH SEGMENTS CODE GOES HERE ****/
    44 
    45        /*
    46         * END OF DE-ESTABLISH SEGMENTS
    47         */
    48 
    49         popa                                # restore general registers
    50         iret                                # return to interrupted thread
    51 
    52                
    53 SYM (_New_ISR_Handler):
     17SYM (_ISR_Handler):     
    5418       /*
    5519        *  Before this was point is reached the vectors unique
    5620        *  entry point did the following:
    5721        *
    58         *     1. saved sctach registers registers eax edx ecx"
     22        *     1. saved scratch registers registers eax edx ecx"
    5923        *     2. put the vector number in ecx.
    6024        *
     
    177141        cmpl      $0, SYM (_Context_Switch_necessary)
    178142                                            # Is task switch necessary?
    179         jne       bframe                    # Yes, then build stack
     143        jne       .schedule                 # Yes, then call the scheduler
    180144
    181145        cmpl      $0, SYM (_ISR_Signals_to_thread_executing)
     
    184148        je        .exit                     # No, exit
    185149
    186 bframe:
     150       
     151.bframe:
    187152        movl      $0, SYM (_ISR_Signals_to_thread_executing)
    188153        /*
    189          * complete code as if a pusha had been executed on entry
    190          */
    191         pushl     ebx
    192         pushl     esp
    193         pushl     ebp
    194         pushl     esi
    195         pushl     edi
    196                                             # push the isf for Isr_dispatch
    197         pushl     EFLAGS_OFFSET(esp)        # push tasks eflags
    198         push      cs                        # cs of Isr_dispatch
    199         pushl     $ SYM (_New_ISR_Displatch)# entry point
    200         iret
    201 
     154         * This code is the less critical path. In order to have a single
     155         * Thread Context, we take the same frame than the one pushed on
     156         * exceptions. This makes sense because Signal is a software
     157         * exception.
     158         */
     159        popl    edx
     160        popl    ecx
     161        popl    eax
     162
     163        pushl   $0      # fake fault code
     164        pushl   $0      # fake exception number
     165
     166        pusha
     167        pushl   esp
     168        call    _ThreadProcessSignalsFromIrq
     169        addl    $4, esp
     170        popa
     171        addl    $8, esp
     172        iret
     173                       
     174.schedule:
     175        /*
     176         * the scratch registers have already been saved and we are already
     177         * back on the thread system stack. So we can call _Thread_Displatch
     178         * directly
     179         */
     180        call _Thread_Dispatch
     181        /*
     182         * fall through exit to restore complete contex (scratch registers
     183         * eip, CS, Flags).
     184         */
    202185.exit:
    203186       /*
     
    218201        popl    eax
    219202        iret
    220                
     203
     204                               
    221205#define DISTINCT_INTERRUPT_ENTRY(_vector) \
    222206        .p2align 4                         ; \
     
    227211        pushl   edx             ; \
    228212        movl    $ _vector, ecx  ; \
    229         jmp   SYM (_New_ISR_Handler) ;
     213        jmp   SYM (_ISR_Handler) ;
    230214
    231215DISTINCT_INTERRUPT_ENTRY(0)
  • cpukit/score/cpu/i386/cpu.c

    r7549e14 r8b2ee37c  
    7676  return level;
    7777}
    78  
     78
     79void _CPU_Thread_Idle_body ()
     80{
     81  while(1){
     82    asm volatile ("hlt");
     83  }
     84}
     85     
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