Changeset 8ae37323 in rtems


Ignore:
Timestamp:
Aug 10, 2014, 4:36:30 PM (5 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
6cdc090
Parents:
81329f9
git-author:
Sebastian Huber <sebastian.huber@…> (08/10/14 16:36:30)
git-committer:
Sebastian Huber <sebastian.huber@…> (08/12/14 17:08:19)
Message:

arm: Add support for FPv4-SP floating point unit

This floating point unit is available in Cortex-M4 processors and
defined by ARMv7-M. This adds basic support for other VFP-D16 variants.

Files:
13 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/shared/start/start.S

    r81329f9 r8ae37323  
    267267#elif defined(ARM_MULTILIB_ARCH_V7M)
    268268
     269#include <rtems/score/armv7m.h>
     270
    269271        .syntax unified
    270272
     
    301303_start:
    302304
     305#ifdef ARM_MULTILIB_VFP
     306        /*
     307         * Enable CP10 and CP11 coprocessors for privileged and user mode in
     308         * CPACR (bits 20-23).  Ensure that write to register completes.
     309         */
     310        ldr     r0, =ARMV7M_CPACR
     311        ldr     r1, [r0]
     312        orr     r1, r1, #(0xf << 20)
     313        str     r1, [r0]
     314        dsb
     315        isb
     316#endif
     317
    303318        ldr     sp, =bsp_stack_main_end
    304319        ldr     lr, =bsp_start_hook_0_done + 1
  • cpukit/score/cpu/arm/arm-context-validate.S

    r81329f9 r8ae37323  
    11/*
    2  * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
     2 * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
    33 *
    44 *  embedded brains GmbH
     
    3030#define FRAME_OFFSET_LR 32
    3131
    32 #ifdef ARM_MULTILIB_VFP_D32
     32#ifdef ARM_MULTILIB_VFP
    3333  #define FRAME_OFFSET_D8 40
    3434  #define FRAME_OFFSET_D9 48
     
    7272        str     r1, [sp, #FRAME_OFFSET_LR]
    7373
    74 #ifdef ARM_MULTILIB_VFP_D32
     74#ifdef ARM_MULTILIB_VFP
    7575        vstr    d8, [sp, #FRAME_OFFSET_D8]
    7676        vstr    d9, [sp, #FRAME_OFFSET_D9]
     
    9797
    9898
    99 #ifdef ARM_MULTILIB_VFP_D32
     99#ifdef ARM_MULTILIB_VFP
    100100        /* R3 contains the FPSCR */
    101101        vmrs    r3, FPSCR
    102102        movs    r4, #0x001f
     103#ifdef ARM_MULTILIB_ARCH_V7M
     104        movt    r4, #0xf000
     105#else
    103106        movt    r4, #0xf800
     107#endif
    104108        bic     r3, r3, r4
    105109        and     r4, r4, r0
     
    121125        fill_register   lr
    122126
    123 #ifdef ARM_MULTILIB_VFP_D32
     127#ifdef ARM_MULTILIB_VFP
    124128.macro fill_vfp_register reg
    125129        add     r1, r1, #1
     
    143147        fill_vfp_register       d14
    144148        fill_vfp_register       d15
     149#ifdef ARM_MULTILIB_VFP_D32
    145150        fill_vfp_register       d16
    146151        fill_vfp_register       d17
     
    159164        fill_vfp_register       d30
    160165        fill_vfp_register       d31
    161 #endif
     166#endif /* ARM_MULTILIB_VFP_D32 */
     167#endif /* ARM_MULTILIB_VFP */
    162168
    163169        /* Check */
     
    175181        mov     r1, r0
    176182
    177 #ifndef ARM_MULTILIB_VFP_D32
     183#ifndef ARM_MULTILIB_VFP
    178184        check_register  r3
    179185#endif
     
    190196        check_register  lr
    191197
    192 #ifdef ARM_MULTILIB_VFP_D32
     198#ifdef ARM_MULTILIB_VFP
    193199        b       check_vfp
    194200#endif
     
    218224        mov     lr, r1
    219225
    220 #ifdef ARM_MULTILIB_VFP_D32
     226#ifdef ARM_MULTILIB_VFP
    221227        vldr    d8, [sp, #FRAME_OFFSET_D8]
    222228        vldr    d9, [sp, #FRAME_OFFSET_D9]
     
    235241FUNCTION_END(_CPU_Context_validate)
    236242
    237 #ifdef ARM_MULTILIB_VFP_D32
     243#ifdef ARM_MULTILIB_VFP
    238244check_vfp:
    239245
     
    271277        check_vfp_register      d14
    272278        check_vfp_register      d15
     279#ifdef ARM_MULTILIB_VFP_D32
    273280        check_vfp_register      d16
    274281        check_vfp_register      d17
     
    287294        check_vfp_register      d30
    288295        check_vfp_register      d31
     296#endif /* ARM_MULTILIB_VFP_D32 */
    289297
    290298        /* Restore r4 and r5 */
     
    294302
    295303        b       check
    296 
    297 #endif
     304#endif /* ARM_MULTILIB_VFP */
  • cpukit/score/cpu/arm/arm-context-volatile-clobber.S

    r81329f9 r8ae37323  
    11/*
    2  * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
     2 * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
    33 *
    44 *  embedded brains GmbH
     
    2828.endm
    2929
    30 #ifdef ARM_MULTILIB_VFP_D32
     30#ifdef ARM_MULTILIB_VFP
    3131        vmrs    r1, FPSCR
    3232        movs    r2, #0x001f
     
    5050        clobber_vfp_register    d6
    5151        clobber_vfp_register    d7
     52#ifdef ARM_MULTILIB_VFP_D32
    5253        clobber_vfp_register    d16
    5354        clobber_vfp_register    d17
     
    6667        clobber_vfp_register    d30
    6768        clobber_vfp_register    d31
    68 #endif
     69#endif /* ARM_MULTILIB_VFP_D32 */
     70#endif /* ARM_MULTILIB_VFP */
    6971
    7072        clobber_register        r1
  • cpukit/score/cpu/arm/arm_exc_interrupt.S

    r81329f9 r8ae37323  
    7676        stmdb   sp!, {SP_OF_INTERRUPTED_CONTEXT, lr}
    7777
    78 #ifdef ARM_MULTILIB_VFP_D32
     78#ifdef ARM_MULTILIB_VFP
    7979        /* Save VFP context */
    8080        vmrs    r0, FPSCR
    8181        vstmdb  sp!, {d0-d7}
     82#ifdef ARM_MULTILIB_VFP_D32
    8283        vstmdb  sp!, {d16-d31}
     84#endif
    8385        stmdb   sp!, {r0, r1}
    84 #endif
     86#endif /* ARM_MULTILIB_VFP */
    8587
    8688        /* Get per-CPU control of current processor */
     
    167169        SWITCH_FROM_THUMB_TO_ARM
    168170
    169 #ifdef ARM_MULTILIB_VFP_D32
     171#ifdef ARM_MULTILIB_VFP
    170172        /* Restore VFP context */
    171173        ldmia   sp!, {r0, r1}
     174#ifdef ARM_MULTILIB_VFP_D32
    172175        vldmia  sp!, {d16-d31}
     176#endif
    173177        vldmia  sp!, {d0-d7}
    174178        vmsr    FPSCR, r0
    175 #endif
     179#endif /* ARM_MULTILIB_VFP */
    176180
    177181        /* Restore SP_OF_INTERRUPTED_CONTEXT register and link register */
  • cpukit/score/cpu/arm/armv4-exception-default.S

    r81329f9 r8ae37323  
    119119        mov     r0, sp
    120120
    121 #ifdef ARM_MULTILIB_VFP_D32
     121        /* Clear VFP context pointer */
     122        add     r3, sp, #ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET
     123        mov     r1, #0
     124        str     r1, [r3]
     125
     126#ifdef ARM_MULTILIB_VFP
    122127        /* Ensure that the FPU is enabled */
    123128        vmrs    r1, FPEXC
    124129        tst     r1, #(1 << 30)
    125         beq     fpu_save_done
     130        beq     1f
    126131
    127         add     r3, sp, #ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET
     132        /* Save VFP context */
    128133        sub     sp, #(ARM_VFP_CONTEXT_SIZE + 4)
    129134        add     r4, sp, #4
     
    133138        stmia   r4!, {r1-r2}
    134139        vstmia  r4!, {d0-d15}
     140#ifdef ARM_MULTILIB_VFP_D32
    135141        vstmia  r4!, {d16-d31}
    136 
    137 fpu_save_done:
     142#else
     143        mov     r1, #0
     144        mov     r2, #0
     145        adds    r3, r4, #128
     1462:
     147        stmia   r4!, {r1-r2}
     148        cmp     r4, r3
     149        bne     2b
    138150#endif
     1511:
     152#endif /* ARM_MULTILIB_VFP */
    139153
    140154        /* Call high level handler */
  • cpukit/score/cpu/arm/armv7m-context-switch.c

    r81329f9 r8ae37323  
    66
    77/*
    8  * Copyright (c) 2011 Sebastian Huber.  All rights reserved.
     8 * Copyright (c) 2011-2014 Sebastian Huber.  All rights reserved.
    99 *
    1010 *  embedded brains GmbH
     
    3838    "ldr r3, [r2, %[isrpcpuoff]]\n"
    3939    "stm r0, {r4-r11, lr}\n"
     40#ifdef ARM_MULTILIB_VFP
     41    "add r4, r0, %[d8off]\n"
     42    "vstm r4, {d8-d15}\n"
     43#endif
    4044    "str sp, [r0, %[spctxoff]]\n"
    4145    "str r3, [r0, %[isrctxoff]]\n"
    4246    "ldr r3, [r1, %[isrctxoff]]\n"
    4347    "ldr sp, [r1, %[spctxoff]]\n"
     48#ifdef ARM_MULTILIB_VFP
     49    "add r4, r1, %[d8off]\n"
     50    "vldm r4, {d8-d15}\n"
     51#endif
    4452    "ldm r1, {r4-r11, lr}\n"
    4553    "str r3, [r2, %[isrpcpuoff]]\n"
     
    4856    : [spctxoff] "J" (offsetof(Context_Control, register_sp)),
    4957      [isrctxoff] "J" (offsetof(Context_Control, isr_nest_level)),
    50       [isrpcpuoff] "J" (offsetof(Per_CPU_Control, isr_nest_level))
     58      [isrpcpuoff] "J" (offsetof(Per_CPU_Control, isr_nest_level)),
     59      [d8off] "J" (ARM_CONTEXT_CONTROL_D8_OFFSET)
    5160  );
    5261}
  • cpukit/score/cpu/arm/armv7m-exception-default.c

    r81329f9 r8ae37323  
    3939    "mrs r1, ipsr\n"
    4040    "str r1, [sp, %[cpuvecoff]]\n"
     41
     42    /* Argument for high level handler */
    4143    "mov r0, sp\n"
     44
     45    /* Clear VFP context pointer */
     46    "add r3, sp, %[cpuvfpoff]\n"
     47    "mov r1, #0\n"
     48    "str r1, [r3]\n"
     49
     50#ifdef ARM_MULTILIB_VFP
     51    /* Ensure that the FPU is enabled */
     52    "ldr r4, =%[cpacr]\n"
     53    "tst r4, #(0xf << 20)\n"
     54    "bne 1f\n"
     55
     56    /* Save VFP context */
     57    "sub sp, %[vfpsz]\n"
     58    "add r4, sp, #4\n"
     59    "bic r4, r4, #7\n"
     60    "str r4, [r3]\n"
     61    "vmrs r2, FPSCR\n"
     62    "stmia r4!, {r1-r2}\n"
     63    "vstmia r4!, {d0-d15}\n"
     64    "mov r1, #0\n"
     65    "mov r2, #0\n"
     66    "adds r3, r4, #128\n"
     67    "2:\n"
     68    "stmia r4!, {r1-r2}\n"
     69    "cmp r4, r3\n"
     70    "bne 2b\n"
     71    "1:\n"
     72#endif
     73
    4274    "b _ARM_Exception_default\n"
    4375    :
    4476    : [cpufsz] "i" (sizeof(CPU_Exception_frame)),
    4577      [v7mfsz] "i" (sizeof(ARMV7M_Exception_frame)),
    46       [cpuspoff] "J" (offsetof(CPU_Exception_frame, register_sp)),
    4778      [cpulroff] "i" (offsetof(CPU_Exception_frame, register_lr)),
    4879      [v7mlroff] "i" (offsetof(ARMV7M_Exception_frame, register_lr)),
    49       [cpuvecoff] "J" (offsetof(CPU_Exception_frame, vector))
     80      [cpuvecoff] "J" (offsetof(CPU_Exception_frame, vector)),
     81      [cpuvfpoff] "i" (ARM_EXCEPTION_FRAME_VFP_CONTEXT_OFFSET),
     82      [cpacr] "i" (ARMV7M_CPACR),
     83      [vfpsz] "i" (ARM_VFP_CONTEXT_SIZE)
    5084  );
    5185}
  • cpukit/score/cpu/arm/armv7m-isr-dispatch.c

    r81329f9 r8ae37323  
    66
    77/*
    8  * Copyright (c) 2011 Sebastian Huber.  All rights reserved.
     8 * Copyright (c) 2011-2014 Sebastian Huber.  All rights reserved.
    99 *
    1010 *  embedded brains GmbH
     
    3838}
    3939
     40static void _ARMV7M_Trigger_lazy_floating_point_context_save( void )
     41{
     42#ifdef ARM_MULTILIB_VFP
     43  __asm__ volatile (
     44    "vmov.f32 s0, s0\n"
     45  );
     46#endif
     47}
     48
    4049void _ARMV7M_Pendable_service_call( void )
    4150{
     51  ARMV7M_Exception_frame *ef;
     52
    4253  _ISR_Nest_level = 1;
     54
    4355  _ARMV7M_SCB->icsr = ARMV7M_SCB_ICSR_PENDSVCLR;
    44   ARMV7M_Exception_frame *ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP();
     56  _ARMV7M_Trigger_lazy_floating_point_context_save();
     57
     58  ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP();
    4559  --ef;
    46   _ARMV7M_Set_PSP((uint32_t) ef);
     60  _ARMV7M_Set_PSP( (uint32_t) ef );
    4761
    4862  /*
     
    5872void _ARMV7M_Supervisor_call( void )
    5973{
    60   ARMV7M_Exception_frame *ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP();
     74  ARMV7M_Exception_frame *ef;
     75
     76  _ARMV7M_Trigger_lazy_floating_point_context_save();
     77
     78  ef = (ARMV7M_Exception_frame *) _ARMV7M_Get_PSP();
    6179  ++ef;
    62   _ARMV7M_Set_PSP((uint32_t) ef);
     80  _ARMV7M_Set_PSP( (uint32_t) ef );
     81
    6382  _ISR_Nest_level = 0;
    6483  RTEMS_COMPILER_MEMORY_BARRIER();
     84
    6585  if ( _Thread_Dispatch_necessary ) {
    6686    _ARMV7M_Pendable_service_call();
  • cpukit/score/cpu/arm/cpu.c

    r81329f9 r8ae37323  
    3636#include <rtems/score/cpu.h>
    3737
    38 #ifdef ARM_MULTILIB_VFP_D32
     38#ifdef ARM_MULTILIB_VFP
    3939  RTEMS_STATIC_ASSERT(
    4040    offsetof( Context_Control, register_d8 ) == ARM_CONTEXT_CONTROL_D8_OFFSET,
  • cpukit/score/cpu/arm/cpu_asm.S

    r81329f9 r8ae37323  
    5959        stmia   r0,  {r2, r4, r5, r6, r7, r8, r9, r10, r11, r13, r14}
    6060
    61 #ifdef ARM_MULTILIB_VFP_D32
     61#ifdef ARM_MULTILIB_VFP
    6262        add     r3, r0, #ARM_CONTEXT_CONTROL_D8_OFFSET
    6363        vstm    r3, {d8-d15}
     
    102102#endif
    103103
    104 #ifdef ARM_MULTILIB_VFP_D32
     104#ifdef ARM_MULTILIB_VFP
    105105        add     r3, r1, #ARM_CONTEXT_CONTROL_D8_OFFSET
    106106        vldm    r3, {d8-d15}
  • cpukit/score/cpu/arm/rtems/score/arm.h

    r81329f9 r8ae37323  
    5151#endif
    5252
    53 #if defined(__ARM_NEON__)
    54   #define ARM_MULTILIB_VFP_D32
    55 #elif !defined(__SOFTFP__)
    56   #error "FPU support not implemented"
     53#if !defined(__SOFTFP__)
     54  #if defined(__ARM_NEON__)
     55    #define ARM_MULTILIB_VFP_D32
     56  #elif defined(__VFP_FP__)
     57    #define ARM_MULTILIB_VFP_D16
     58  #else
     59    #error "FPU support not implemented"
     60  #endif
     61#endif
     62
     63#if defined(ARM_MULTILIB_VFP_D16) \
     64  || defined(ARM_MULTILIB_VFP_D32)
     65  #define ARM_MULTILIB_VFP
    5766#endif
    5867
  • cpukit/score/cpu/arm/rtems/score/armv7m.h

    r81329f9 r8ae37323  
    66
    77/*
    8  * Copyright (c) 2011 Sebastian Huber.  All rights reserved.
     8 * Copyright (c) 2011-2014 Sebastian Huber.  All rights reserved.
    99 *
    1010 *  embedded brains GmbH
     
    3030#ifdef ARM_MULTILIB_ARCH_V7M
    3131
     32/* Coprocessor Access Control Register, CPACR */
     33#define ARMV7M_CPACR 0xe000ed88
     34
     35#ifndef ASM
     36
    3237typedef struct {
    3338  uint32_t reserved_0;
     
    4853  void *register_pc;
    4954  uint32_t register_xpsr;
     55#ifdef ARM_MULTILIB_VFP
     56  uint32_t register_s0;
     57  uint32_t register_s1;
     58  uint32_t register_s2;
     59  uint32_t register_s3;
     60  uint32_t register_s4;
     61  uint32_t register_s5;
     62  uint32_t register_s6;
     63  uint32_t register_s7;
     64  uint32_t register_s8;
     65  uint32_t register_s9;
     66  uint32_t register_s10;
     67  uint32_t register_s11;
     68  uint32_t register_s12;
     69  uint32_t register_s13;
     70  uint32_t register_s14;
     71  uint32_t register_s15;
     72  uint32_t register_fpscr;
     73  uint32_t reserved;
     74#endif
    5075} ARMV7M_Exception_frame;
    5176
     
    98123  uint32_t bfar;
    99124  uint32_t afsr;
     125  uint32_t reserved_e000ed40[18];
     126  uint32_t cpacr;
     127  uint32_t reserved_e000ed8c[106];
     128  uint32_t fpccr;
     129  uint32_t fpcar;
     130  uint32_t fpdscr;
     131  uint32_t mvfr0;
     132  uint32_t mvfr1;
    100133} ARMV7M_SCB;
    101134
     
    505538void _ARMV7M_Supervisor_call( void );
    506539
     540#endif /* ASM */
     541
    507542#endif /* ARM_MULTILIB_ARCH_V7M */
    508543
  • cpukit/score/cpu/arm/rtems/score/cpu.h

    r81329f9 r8ae37323  
    99 *  processor.
    1010 *
    11  *  Copyright (c) 2009-2013 embedded brains GmbH.
     11 *  Copyright (c) 2009-2014 embedded brains GmbH.
    1212 *
    1313 *  Copyright (c) 2007 Ray Xu <Rayx.cn@gmail.com>
     
    213213#endif
    214214
    215 #ifdef ARM_MULTILIB_VFP_D32
     215#ifdef ARM_MULTILIB_VFP
    216216  #define ARM_CONTEXT_CONTROL_D8_OFFSET 48
    217217#endif
    218218
    219219#ifdef RTEMS_SMP
    220   #ifdef ARM_MULTILIB_VFP_D32
     220  #ifdef ARM_MULTILIB_VFP
    221221    #define ARM_CONTEXT_CONTROL_IS_EXECUTING_OFFSET 112
    222222  #else
     
    279279  uint32_t thread_id;
    280280#endif
    281 #ifdef ARM_MULTILIB_VFP_D32
     281#ifdef ARM_MULTILIB_VFP
    282282  uint64_t register_d8;
    283283  uint64_t register_d9;
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