Changeset 8a80d54 in umon


Ignore:
Timestamp:
Jul 16, 2015, 11:26:44 AM (4 years ago)
Author:
Jarielle Catbagan <jcatbagan93@…>
Branches:
master
Children:
d55aa7c
Parents:
273af8f
git-author:
Jarielle Catbagan <jcatbagan93@…> (07/16/15 11:26:44)
git-committer:
Ed Sutter <edsutterjr@…> (07/18/15 13:13:25)
Message:

BBB: rom_reset.S: Initialize the SP at the top of SRAM prior to invoking pll_init and ddr_init

File:
1 edited

Legend:

Unmodified
Added
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  • ports/beagleboneblack/rom_reset.S

    r273af8f r8a80d54  
    172172    orr r0, r0, #0x13           /* set System mode bits */
    173173    msr CPSR_c, r0              /* move back to CPSR */
    174     /* Reset the stack pointer for the SVC mode (our current mode) */
    175     ldr sp, =(MonStack + MONSTACKSIZE - 4)
     174
     175    /* Initialize the SP at the top of SRAM outside of the uMon code
     176     * space so that the following two C functions can be invoked
     177     * properly to take care of PLL and DDR3 initialization.
     178     */
     179    movw sp, #0x5e00
     180    movt sp, #0x4030
    176181
    177182    /* Initialize the MPU, Core, DDR, and Per PLLs.  Furthermore,
     
    181186    bl pll_init
    182187    bl ddr_init
     188
     189    /* Reset the stack pointer for the SVC mode (our current mode) */
     190    ldr sp, =(MonStack + MONSTACKSIZE - 4)
    183191
    184192    /*
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