Changeset 89fc9341 in rtems


Ignore:
Timestamp:
Sep 18, 2008, 5:40:14 PM (11 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, master
Children:
ccceaf3
Parents:
75c9e48d
Message:

2008-09-18 Joel Sherrill <joel.sherrill@…>

  • include/bsp.h, include/tm27.h: Remove unnecessary boilerplate comments.
Location:
c/src/lib/libbsp/mips/csb350
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/mips/csb350/ChangeLog

    r75c9e48d r89fc9341  
     12008-09-18      Joel Sherrill <joel.sherrill@oarcorp.com>
     2
     3        * include/bsp.h, include/tm27.h: Remove unnecessary boilerplate
     4        comments.
     5
    162008-09-16      Joel Sherrill <joel.sherrill@oarcorp.com>
    27
  • c/src/lib/libbsp/mips/csb350/include/bsp.h

    r75c9e48d r89fc9341  
    2929#include <libcpu/au1x00.h>
    3030
    31 /*
    32  *  Define the interrupt mechanism for Time Test 27
    33  */
    34 int assert_sw_irw(uint32_t irqnum);
    35 int negate_sw_irw(uint32_t irqnum);
    36 
    37 #define MUST_WAIT_FOR_INTERRUPT 0
    38 
    39 #define Install_tm27_vector( handler ) \
    40    (void) set_vector(handler, AU1X00_IRQ_SW0, 1);
    41 
    42 #define Cause_tm27_intr() \
    43   do { \
    44      assert_sw_irq(0); \
    45   } while(0)
    46 
    47 #define Clear_tm27_intr() \
    48   do { \
    49      negate_sw_irq(0); \
    50   } while(0)
    51 
    52 #if 0
    53 #define Lower_tm27_intr() \
    54   mips_enable_in_interrupt_mask( 0xff01 );
    55 #else
    56 #define Lower_tm27_intr() \
    57   do { \
    58      continue;\
    59   } while(0)
    60 #endif
    61 
    62 /* Constants */
    63 
    64 /* miscellaneous stuff assumed to exist */
    65 
    66 /*
    67  *  Device Driver Table Entries
    68  */
    69 
    70 /*
    71  * NOTE: Use the standard Console driver entry
    72  */
    73  
    74 /*
    75  * NOTE: Use the standard Clock driver entry
    76  */
    7731
    7832/*
  • c/src/lib/libbsp/mips/csb350/include/tm27.h

    r75c9e48d r89fc9341  
    2020 */
    2121
    22 #define MUST_WAIT_FOR_INTERRUPT 1
     22int assert_sw_irw(uint32_t irqnum);
     23int negate_sw_irw(uint32_t irqnum);
    2324
    24 #define Install_tm27_vector( handler )
     25#define MUST_WAIT_FOR_INTERRUPT 0
     26
     27#define Install_tm27_vector( handler ) \
     28   (void) set_vector(handler, AU1X00_IRQ_SW0, 1);
    2529
    2630#define Cause_tm27_intr() \
    2731  do { \
    28     ; \
     32     assert_sw_irq(0); \
    2933  } while(0)
    3034
    3135#define Clear_tm27_intr() \
    3236  do { \
    33     ; \
     37     negate_sw_irq(0); \
    3438  } while(0)
    3539
    36 #define Lower_tm27_intr()
     40#if 0
     41#define Lower_tm27_intr() \
     42  mips_enable_in_interrupt_mask( 0xff01 );
     43#else
     44#define Lower_tm27_intr() \
     45  do { \
     46     continue;\
     47  } while(0)
     48#endif
     49#endif
    3750
    3851#endif
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