Changeset 89b7e69 in rtems
- Timestamp:
- 06/13/07 21:20:50 (15 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 0d04790
- Parents:
- b016200a
- Location:
- c/src/lib/libbsp/arm
- Files:
-
- 2 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/arm/ChangeLog
rb016200a r89b7e69 1 2007-06-13 Ray Xu <rayx@gmail.com> 2 3 * shared/abort/simple_abort.c: Shrink the memory requirements. Joel 4 reformatted for style. 5 1 6 2007-06-13 Joel Sherrill <joel.sherrill@OARcorp.com> 2 7 -
c/src/lib/libbsp/arm/shared/abort/simple_abort.c
rb016200a r89b7e69 47 47 48 48 char *_print_full_context_mode2txt[0x10]={ 49 50 51 52 53 54 55 56 49 [0x0]="user", /* User */ 50 [0x1]="fiq", /* FIQ - Fast Interrupt Request */ 51 [0x2]="irq", /* IRQ - Interrupt Request */ 52 [0x3]="super", /* Supervisor */ 53 [0x7]="abort", /* Abort */ 54 [0xb]="undef", /* Undefined */ 55 [0xf]="system" /* System */ 56 }; 57 57 58 58 void _print_full_context(uint32_t spsr) 59 59 { 60 61 62 int i;60 char *mode; 61 uint32_t prev_sp,prev_lr,cpsr,tmp; 62 int i, j; 63 63 64 64 printk("active thread thread 0x%08x\n", _Thread_Executing->Object.id); 65 65 66 67 66 mode=_print_full_context_mode2txt[(spsr&0x1f)-0x10]; 67 if(!mode) mode="unknown"; 68 68 69 70 71 72 73 74 75 76 77 78 69 asm volatile (" MRS %[cpsr], cpsr \n" 70 " ORR %[tmp], %[spsr], #0xc0 \n" 71 " MSR cpsr_c, %[tmp] \n" 72 " MOV %[prev_sp], sp \n" 73 " MOV %[prev_lr], lr \n" 74 " MSR cpsr_c, %[cpsr] \n" 75 : [prev_sp] "=&r" (prev_sp), [prev_lr] "=&r" (prev_lr), 76 [cpsr] "=&r" (cpsr), [tmp] "=&r" (tmp) 77 : [spsr] "r" (spsr) 78 : "cc"); 79 79 80 printk("Previous sp=0x%08x lr=0x%08x and actual cpsr=%08x\n", prev_sp, prev_lr, cpsr); 80 printk( 81 "Previous sp=0x%08x lr=0x%08x and actual cpsr=%08x\n", 82 prev_sp, 83 prev_lr, 84 cpsr 85 ); 81 86 82 for(i=0;i<48;){ 83 printk(" 0x%08x",((uint32_t*)prev_sp)[i++]); 84 if((i%6) == 0) 85 printk("\n"); 86 } 87 87 j=0; 88 for(i=0;i<48;) { 89 printk(" 0x%08x",((uint32_t*)prev_sp)[i++]); 90 j++; 91 /*try not to use % because it introduces hundreds of byte overhead*/ 92 if((j-6)==0) { 93 printk("\n"); 94 j=0; 95 } 96 } 88 97 } 89 98 … … 95 104 */ 96 105 97 void do_data_abort(uint32_t insn, uint32_t spsr, 98 Context_Control *ctx) 106 void do_data_abort( 107 uint32_t insn, 108 uint32_t spsr, 109 Context_Control *ctx 110 ) 99 111 { 100 112 /* Clarify, which type is correct, CPU_Exception_frame or Context_Control */ 101 113 102 uint8_t decode; 103 uint8_t insn_type; 114 uint8_t decode; 115 uint8_t insn_type; 116 uint32_t tmp; 104 117 105 uint32_t tmp;118 decode = ((insn >> 20) & 0xff); 106 119 107 decode = ((insn >> 20) & 0xff); 120 insn_type = decode & INSN_MASK; 121 switch(insn_type) { 122 case INSN_STM1: 123 printk("\n\nINSN_STM1\n"); 124 break; 125 case INSN_STM2: 126 printk("\n\nINSN_STM2\n"); 127 break; 128 case INSN_STR: 129 printk("\n\nINSN_STR\n"); 130 break; 131 case INSN_STRB: 132 printk("\n\nINSN_STRB\n"); 133 break; 134 case INSN_LDM1: 135 printk("\n\nINSN_LDM1\n"); 136 break; 137 case INSN_LDM23: 138 printk("\n\nINSN_LDM23\n"); 139 break; 140 case INSN_LDR: 141 printk("\n\nINSN_LDR\n"); 142 break; 143 case INSN_LDRB: 144 printk("\n\nINSN_LDRB\n"); 145 break; 146 default: 147 printk("\n\nUnrecognized instruction\n"); 148 break; 149 } 150 151 printk("data_abort at address 0x%x, instruction: 0x%x, spsr = 0x%x\n", 152 ctx->register_lr - 8, insn, spsr); 108 153 109 insn_type = decode & INSN_MASK; 110 switch(insn_type) { 111 case INSN_STM1: 112 printk("\n\nINSN_STM1\n"); 113 break; 114 case INSN_STM2: 115 printk("\n\nINSN_STM2\n"); 116 break; 117 case INSN_STR: 118 printk("\n\nINSN_STR\n"); 119 break; 120 case INSN_STRB: 121 printk("\n\nINSN_STRB\n"); 122 break; 123 case INSN_LDM1: 124 printk("\n\nINSN_LDM1\n"); 125 break; 126 case INSN_LDM23: 127 printk("\n\nINSN_LDM23\n"); 128 break; 129 case INSN_LDR: 130 printk("\n\nINSN_LDR\n"); 131 break; 132 case INSN_LDRB: 133 printk("\n\nINSN_LDRB\n"); 134 break; 135 default: 136 printk("\n\nUnrecognized instruction\n"); 137 break; 138 } 139 140 printk("data_abort at address 0x%x, instruction: 0x%x, spsr = 0x%x\n", 141 ctx->register_lr - 8, insn, spsr); 154 _print_full_context(spsr); 142 155 143 _print_full_context(spsr); 144 145 /* disable interrupts, wait forever */ 146 _CPU_ISR_Disable(tmp); 147 while(1) { 148 continue; 149 } 150 return; 156 /* disable interrupts, wait forever */ 157 _CPU_ISR_Disable(tmp); 158 while(1) { 159 continue; 160 } 161 return; 151 162 } 152 163
Note: See TracChangeset
for help on using the changeset viewer.