Changeset 89173ee9 in rtems


Ignore:
Timestamp:
Jan 26, 2017, 10:36:52 AM (3 years ago)
Author:
Javier Jalle <javier.jalle@…>
Branches:
5, master
Children:
a545ce26
Parents:
84557ef
git-author:
Javier Jalle <javier.jalle@…> (01/26/17 10:36:52)
git-committer:
Daniel Hellstrom <daniel@…> (03/06/17 06:54:55)
Message:

bsps/sparc: Updated L2C registers

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/sparc/shared/include/grlib.h

    r84557ef r89173ee9  
    134134/* L2C - Level 2 Cache Controller registers */
    135135struct l2c_regs {
    136   volatile unsigned int control;
    137   volatile unsigned int status;
    138   volatile unsigned int flush_mem_addr;
    139   volatile unsigned int flush_set_index;
    140   volatile unsigned int access_counter;
    141   volatile unsigned int hit_counter;
    142   volatile unsigned int bus_cycle_counter;
    143   volatile unsigned int bus_usage_counter;
    144   volatile unsigned int error_status_control;
    145   volatile unsigned int error_addr;
    146   volatile unsigned int tag_check_bit;
    147   volatile unsigned int data_check_bit;
    148   volatile unsigned int scrub_control_status;
    149   volatile unsigned int scrub_delay;
    150   volatile unsigned int error_injection;
    151   volatile unsigned int reserved_3c[17];
    152   volatile unsigned int mtrr;
    153   volatile unsigned int reserved_84[131039];
    154   volatile unsigned int diag_iface_tag[16384];
    155   volatile unsigned int reserved_90000[376832];
    156   volatile unsigned int diag_iface_data[524288];
     136  volatile unsigned int control;                /* 0x00 Control register */
     137  volatile unsigned int status;                 /* 0x04 Status register */
     138  volatile unsigned int flush_mem_addr;         /* 0x08 Flush (Memory address) */
     139  volatile unsigned int flush_set_index;        /* 0x0c Flush (set, index) */
     140  volatile unsigned int access_counter;         /* 0x10 */
     141  volatile unsigned int hit_counter;            /* 0x14 */
     142  volatile unsigned int bus_cycle_counter;      /* 0x18 */
     143  volatile unsigned int bus_usage_counter;      /* 0x1c */
     144  volatile unsigned int error_status_control;   /* 0x20 Error status/control */
     145  volatile unsigned int error_addr;             /* 0x24 Error address */
     146  volatile unsigned int tag_check_bit;          /* 0x28 TAG-check-bit */
     147  volatile unsigned int data_check_bit;         /* 0x2c Data-check-bit */
     148  volatile unsigned int scrub_control_status;   /* 0x30 Scrub Control/Status */
     149  volatile unsigned int scrub_delay;            /* 0x34 Scrub Delay */
     150  volatile unsigned int error_injection;        /* 0x38 Error injection */
     151  volatile unsigned int access_control;         /* 0x3c Access control */
     152  volatile unsigned int reserved_40[16];        /* 0x40 Reserved */
     153  volatile unsigned int mtrr[32];               /* 0x80 - 0xFC MTRR registers */
     154  volatile unsigned int reserved_100[131008];   /* 0x100 Reserved */
     155  volatile unsigned int diag_iface_tag[16384];  /* 0x80000 - 0x8FFFC Diagnostic interface (Tag) */
     156  volatile unsigned int reserved_90000[376832]; /* 0x90000 Reserved */
     157  volatile unsigned int diag_iface_data[524288];/* 0x200000 - 0x3FFFFC Diagnostic interface (Data) */
    157158};
    158159
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