Changeset 87b721f5 in rtems

Nov 13, 2002, 4:58:09 PM (19 years ago)
Joel Sherrill <joel.sherrill@…>
4.10, 4.11, 4.8, 4.9, 5, master

2002-11-13 Jay Monkman <jtm@…>

  • intr_NOTIMES.t: Real version submitted.
2 edited


  • doc/supplements/arm/ChangeLog

    rdd1ad07b r87b721f5  
     12002-11-13      Jay Monkman <>
     3        * intr_NOTIMES.t: Real version submitted.
    152002-10-24      Joel Sherrill <>
  • doc/supplements/arm/intr_NOTIMES.t

    rdd1ad07b r87b721f5  
    2424details of interrupt processing, it is important to understand
    2525how the RTEMS interrupt manager is mapped onto the processor's
    26 unique architecture. Discussed in this chapter are the XXX's
     26unique architecture. Discussed in this chapter are the ARM's
    2727interrupt response and control mechanisms as they pertain to
     30The ARM has 7 exception types:
     31@itemize @bullet
     33@item Reset
     34@item Undefined instruction
     35@item Software interrupt (SWI)
     36@item Prefetch Abort
     37@item Data Abort
     38@item Interrupt (IRQ)
     39@item Fast Interrupt (FIQ)
     41@end itemize
     43Of these types, only IRQ and FIQ are handled through RTEMS's interrupt
    3046@section Vectoring of an Interrupt Handler
    32 Depending on whether or not the particular CPU
    33 supports a separate interrupt stack, the XXX family has two
    34 different interrupt handling models.
    36 @subsection Models Without Separate Interrupt Stacks
    38 Upon receipt of an interrupt the XXX family
    39 members without separate interrupt stacks automatically perform
    40 the following actions:
     49Unlike many other architectures, the ARM has seperate stacks for each
     50interrupt. When the CPU receives an interrupt, it:
    4252@itemize @bullet
    43 @item To Be Written
     53@item switches to the exception mode corresponding to the interrupt,
     55@item saves the Current Processor Status Register (CPSR) to the
     56exception mode's Saved Processor Status Register (SPSR),
     58@item masks off the IRQ and if the interrupt source was FIQ, the FIQ
     59is masked off as well,
     61@item saves the Program Counter (PC) to the exception mode's Link
     62Register (LR - same as R14),
     64@item and sets the PC to the exception's vector address.
    4466@end itemize
    46 @subsection Models With Separate Interrupt Stacks
    48 Upon receipt of an interrupt the XXX family
    49 members with separate interrupt stacks automatically perform the
    50 following actions:
    52 @itemize @bullet
    53 @item saves the current status register (SR),
    55 @item clears the master/interrupt (M) bit of the SR to
    56 indicate the switch from master state to interrupt state,
    58 @item sets the privilege mode to supervisor,
    60 @item suppresses tracing,
    62 @item sets the interrupt mask level equal to the level of the
    63 interrupt being serviced,
    65 @item pushes an interrupt stack frame (ISF), which includes
    66 the program counter (PC), the status register (SR), and the
    67 format/exception vector offset (FVO) word, onto the supervisor
    68 and interrupt stacks,
    70 @item switches the current stack to the interrupt stack and
    71 vectors to an interrupt service routine (ISR).  If the ISR was
    72 installed with the interrupt_catch directive, then the RTEMS
    73 interrupt handler will begin execution.  The RTEMS interrupt
    74 handler saves all registers which are not preserved according to
    75 the calling conventions and invokes the application's ISR.
    76 @end itemize
    78 A nested interrupt is processed similarly by these
    79 CPU models with the exception that only a single ISF is placed
    80 on the interrupt stack and the current stack need not be
    81 switched.
    83 The FVO word in the Interrupt Stack Frame is examined
    84 by RTEMS to determine when an outer most interrupt is being
    85 exited. Since the FVO is used by RTEMS for this purpose, the
    86 user application code MUST NOT modify this field.
    88 The following shows the Interrupt Stack Frame for
    89 XXX CPU models with separate interrupt stacks:
    91 @ifset use-ascii
    92 @example
    93 @group
    94                +----------------------+
    95                |    Status Register   | 0x0
    96                +----------------------+   
    97                | Program Counter High | 0x2
    98                +----------------------+   
    99                | Program Counter Low  | 0x4
    100                +----------------------+   
    101                | Format/Vector Offset | 0x6
    102                +----------------------+   
    103 @end group
    104 @end example
    105 @end ifset
    107 @ifset use-tex
    108 @sp 1
    109 @tex
    110 \centerline{\vbox{\offinterlineskip\halign{
    111 \strut\vrule#&
    112 \hbox to 2.00in{\enskip\hfil#\hfil}&
    113 \vrule#&
    114 \hbox to 0.50in{\enskip\hfil#\hfil}
    115 \cr
    116 \multispan{3}\hrulefill\cr
    117 & Status Register && 0x0\cr
    118 \multispan{3}\hrulefill\cr
    119 & Program Counter High && 0x2\cr
    120 \multispan{3}\hrulefill\cr
    121 & Program Counter Low && 0x4\cr
    122 \multispan{3}\hrulefill\cr
    123 & Format/Vector Offset && 0x6\cr
    124 \multispan{3}\hrulefill\cr
    125 }}\hfil}
    126 @end tex
    127 @end ifset
    129 @ifset use-html
    130 @html
    131 <CENTER>
    132   <TABLE COLS=2 WIDTH="40%" BORDER=2>
    133 <TR><TD ALIGN=center><STRONG>Status Register</STRONG></TD>
    134     <TD ALIGN=center>0x0</TD></TR>
    135 <TR><TD ALIGN=center><STRONG>Program Counter High</STRONG></TD>
    136     <TD ALIGN=center>0x2</TD></TR>
    137 <TR><TD ALIGN=center><STRONG>Program Counter Low</STRONG></TD>
    138     <TD ALIGN=center>0x4</TD></TR>
    139 <TR><TD ALIGN=center><STRONG>Format/Vector Offset</STRONG></TD>
    140     <TD ALIGN=center>0x6</TD></TR>
    141   </TABLE>
    142 </CENTER>
    143 @end html
    144 @end ifset
     68The vectors for both IRQ and FIQ point to the _ISR_Handler function.
     69_ISR_Handler() calls the BSP specific handler, ExecuteITHandler(). Before
     70calling ExecuteITHandler(), registers R0-R3, R12, and R14(LR) are saved so
     71that it is safe to call C functions. Even ExecuteITHandler() can be written
     72in C.
    14674@section Interrupt Levels
    148 Eight levels (0-7) of interrupt priorities are
    149 supported by XXX family members with level seven (7) being
    150 the highest priority.  Level zero (0) indicates that interrupts
    151 are fully enabled.  Interrupt requests for interrupts with
    152 priorities less than or equal to the current interrupt mask
    153 level are ignored.
     76The ARM architecture supports two external interrupts - IRQ and FIQ. FIQ
     77has a higher priority than IRQ, and has its own version of register R8 - R14,
     78however RTEMS does not take advantage of them. Both interrupts are enabled
     79through the CPSR.
    155 Although RTEMS supports 256 interrupt levels, the
    156 XXX family only supports eight.  RTEMS interrupt levels 0
    157 through 7 directly correspond to XXX interrupt levels.  All
    158 other RTEMS interrupt levels are undefined and their behavior is
    159 unpredictable.
     81The RTEMS interrupt level mapping scheme for the AEM is not a numeric level
     82as on most RTEMS ports. It is a bit mapping that corresponds the enable
     83bits's postions in the CPSR:
     85@table @b
     86@item FIQ
     87Setting bit 6 (0 is least significant bit) disables the FIQ.
     89@item IRQ
     90Setting bit 7 (0 is least significant bit) disables the IRQ.
     92@end table
    16195@section Disabling of Interrupts by RTEMS
    184118@section Interrupt Stack
    186 RTEMS allocates the interrupt stack from the
    187 Workspace Area.  The amount of memory allocated for the
    188 interrupt stack is determined by the interrupt_stack_size field
    189 in the CPU Configuration Table.  During the initialization
    190 process, RTEMS will install its interrupt stack.
     120RTEMS expects the interrupt stacks to be set up in bsp_start(). The memory
     121for the stacks is reserved in the linker script.
    192 The XXX port of RTEMS supports a software managed
    193 dedicated interrupt stack on those CPU models which do not
    194 support a separate interrupt stack in hardware.
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