Index: c/src/lib/libbsp/arm/tms570/include/tms570-pom.h
===================================================================
--- c/src/lib/libbsp/arm/tms570/include/tms570-pom.h	(revision 2f95794e490018ccd721227edc302c720d8abb48)
+++ c/src/lib/libbsp/arm/tms570/include/tms570-pom.h	(revision 870ff8e9b6a1c0d7f51cfbdf809b64f774f1869f)
@@ -49,6 +49,5 @@
 #define TMS570_POM_REGADDRMASK    ((1<<23)-1)
 
-
-int mem_dump(void *buf, unsigned long start, unsigned long len, int blen);
+void tms570_initialize_and_clear(void);
 void tms570_pom_remap(void);
 
Index: c/src/lib/libbsp/arm/tms570/irq/irq.c
===================================================================
--- c/src/lib/libbsp/arm/tms570/irq/irq.c	(revision 2f95794e490018ccd721227edc302c720d8abb48)
+++ c/src/lib/libbsp/arm/tms570/irq/irq.c	(revision 870ff8e9b6a1c0d7f51cfbdf809b64f774f1869f)
@@ -202,4 +202,27 @@
    */
   sctlr &= ~(1 << 24);
+  #if 0
+    /*
+     * Option to enable exception table bypass for interrupts
+     *
+     * Because RTEMS requires all interrupts to be serviced through
+     * common _ARMV4_Exception_interrupt handler to allow task switching
+     * on exit from interrupt working correctly, vim_vec cannot point
+     * directly to individual vector handlers and need to point
+     * to single entry path. But if TMS570_VIM.IRQINDEX is then used
+     * to target execution to corresponding service then for some
+     * peripherals (i.e. EMAC) interrupt is already acknowledged
+     * by VIM and IRQINDEX is read as zero which leads to spurious
+     * interrupt and peripheral not serviced/blocked.
+     *
+     * To analyze this behavior we used trampolines which setup
+     * bsp_interrupt_vector_inject and pass execution to
+     * _ARMV4_Exception_interrupt. It works but is more ugly than
+     * use of POM remap for these cases where application does not
+     * start at address 0x00000000. If RTEMS image is placed at
+     * memory space beginning then no of these constructs is necessary.
+     */
+    sctlr |= 1 << 24;
+  #endif
   asm volatile ("mcr p15, 0, %0, c1, c0, 0\n": : "r" (sctlr));
 
Index: c/src/lib/libbsp/arm/tms570/pom/tms570-pom.c
===================================================================
--- c/src/lib/libbsp/arm/tms570/pom/tms570-pom.c	(revision 2f95794e490018ccd721227edc302c720d8abb48)
+++ c/src/lib/libbsp/arm/tms570/pom/tms570-pom.c	(revision 870ff8e9b6a1c0d7f51cfbdf809b64f774f1869f)
@@ -23,5 +23,58 @@
 #include <bsp/tms570-pom.h>
 #include <bsp/linker-symbols.h>
+#include <rtems/score/armv4.h>
 #include <bsp.h>
+
+/*
+ * Placement of exceptions target addresses in memory
+ * when insructions with opcode 0xe59ff018
+ *      ldr pc, [pc, #0x18]
+ * are used to fill ARM exception vectors area
+ */
+typedef struct{
+  uint32_t reserved1;
+  uint32_t except_addr_undef;
+  uint32_t except_addr_swi;
+  uint32_t except_addr_prefetch;
+  uint32_t except_addr_abort;
+  uint32_t reserved2;
+  uint32_t except_addr_irq;
+  uint32_t except_addr_fiq;
+}vec_remap_table;
+
+void bsp_block_on_exception(void);
+
+void bsp_block_on_exception(void){
+  while(1);
+}
+
+extern char bsp_int_vec_overlay_start[];
+
+/*
+ * Global overlay target address holds shared MSB bits for all regions
+ * It is set to linker RAM_INT_VEC region - i.e. area reserved
+ * at internal SRAM memory start, address 0x08000000
+ */
+uint32_t pom_global_overlay_target_address_start =
+                                 (uintptr_t)bsp_int_vec_overlay_start;
+
+/**
+ * @brief initialize and clear parameters overlay module (POM)
+ *
+ * clears all remap regions. The actual POM enable is left to the first user.
+ *
+ * @retval Void
+ */
+void tms570_initialize_and_clear(void)
+{
+  int i;
+
+  TMS570_POM.GLBCTRL = 0 | (TMS570_POM_GLBCTRL_OTADDR(~0) &
+                            pom_global_overlay_target_address_start);
+
+  for ( i = 0; i < TMS570_POM_REGIONS; ++i ) {
+    TMS570_POM.REG[i].REGSIZE = TMS570_POM_REGSIZE_SIZE(TMS570_POM_REGSIZE_DISABLED);
+  }
+}
 
 /**
@@ -34,21 +87,49 @@
 void tms570_pom_remap(void)
 {
-  int i;
-  uint32_t vec_overlay_start = 0x08000000;
-  uint32_t temp = 0;
+  uint32_t vec_overlay_start = pom_global_overlay_target_address_start;
 
+  /*
+   * Copy RTEMS the first level exception processing code
+   * to RAM area which can be used for later as POM overlay
+   * of Flash vectors. The code is expected to have for of eight
+   *   ldr pc, [pc,#0x18]
+   * instructions followed by eight words with actual exception
+   * service routines target addresses. This is case of RTEMS default
+   * table found in
+   *   c/src/lib/libbsp/arm/shared/start/start.S
+   */
   memcpy((void*)vec_overlay_start, bsp_start_vector_table_begin, 64);
 
-  TMS570_POM.GLBCTRL = 0;
+  #if 0
+  {
+    /* Fill exception table by catch error infinite loop for debugging */
+    vec_remap_table* vec_table = (vec_remap_table*)(vec_overlay_start+32);
+    vec_table->except_addr_undef = (uint32_t)bsp_block_on_exception;
+    vec_table->except_addr_swi = (uint32_t)bsp_block_on_exception;
+    vec_table->except_addr_prefetch = (uint32_t)bsp_block_on_exception;//_ARMV4_Exception_prefetch_abort;
+    vec_table->except_addr_abort = (uint32_t)bsp_block_on_exception;//_ARMV4_Exception_data_abort;
+    vec_table->except_addr_irq = (uint32_t)_ARMV4_Exception_interrupt;
+    vec_table->except_addr_fiq = (uint32_t)bsp_block_on_exception;//_ARMV4_Exception_interrupt;
+  }
+  #endif
 
-  for ( i = 0; i < TMS570_POM_REGIONS; ++i ) {
-    TMS570_POM.REG[i].REGSIZE = TMS570_POM_REGSIZE_SIZE(TMS570_POM_REGSIZE_DISABLED);
-  }
-
-  TMS570_POM.REG[0].PROGSTART = TMS570_POM_PROGSTART_STARTADDRESS(0);
+  /*
+   * The overlay vectors replacement area cannot be used directly
+   * to replace jump instructions on start of Flash because instruction
+   * fetch through POM is not reliable supported (works in most times
+   * but sometimes fails).
+   * Area of 64 bytes starting at address 0x00000040 is replaced.
+   * This way target addresses are placed between 0x00000060
+   * and 0x0000007F. If boot loader startup code contains instructions
+   *   ldr pc,[pc,#0x58]
+   * (opcode 0xe59ff058) then the jump target addresses are replaced
+   * by pointers to actual RTEMS exceptions service functions.
+   */
+  TMS570_POM.REG[0].PROGSTART = TMS570_POM_PROGSTART_STARTADDRESS(64);
   TMS570_POM.REG[0].OVLSTART = TMS570_POM_OVLSTART_STARTADDRESS(vec_overlay_start);
   TMS570_POM.REG[0].REGSIZE = TMS570_POM_REGSIZE_SIZE(TMS570_POM_REGSIZE_64B);
   TMS570_POM.GLBCTRL = TMS570_POM_GLBCTRL_ON_OFF(0xa) |
                        TMS570_POM_GLBCTRL_ETO(0xa) |
-                       (TMS570_POM_GLBCTRL_OTADDR(~0) & vec_overlay_start);
+                       (TMS570_POM_GLBCTRL_OTADDR(~0) &
+                        pom_global_overlay_target_address_start);
 }
Index: c/src/lib/libbsp/arm/tms570/startup/bspstart.c
===================================================================
--- c/src/lib/libbsp/arm/tms570/startup/bspstart.c	(revision 2f95794e490018ccd721227edc302c720d8abb48)
+++ c/src/lib/libbsp/arm/tms570/startup/bspstart.c	(revision 870ff8e9b6a1c0d7f51cfbdf809b64f774f1869f)
@@ -28,11 +28,47 @@
 #include <bsp/start.h>
 #include <bsp/bootcard.h>
+#include <bsp/linker-symbols.h>
+#include <rtems/endian.h>
 
 void bsp_start( void )
 {
-  /* set the cpu mode to supervisor and big endian */
-  arm_cpu_mode = 0x213;
+  #if BYTE_ORDER == BIG_ENDIAN
+    /*
+     * If CPU is big endian (TMS570 family variant)
+     * set the CPU mode to supervisor and big endian.
+     * Do not set mode if CPU is little endian
+     * (RM48 family variant) for which default mode 0x13
+     * defined in cpukit/score/cpu/arm/cpu.c
+     * is right.
+     */
+    arm_cpu_mode = 0x213;
+  #endif
 
-  tms570_pom_remap();
+  tms570_initialize_and_clear();
+
+  /*
+   * If RTEMS image does not start at address 0x00000000
+   * then first level exception table at memory begin has
+   * to be replaced to point to RTEMS handlers addresses.
+   *
+   * There is no VBAR or other option because Cortex-R
+   * does provides only fixed address 0x00000000 for exceptions
+   * (0xFFFF0000-0xFFFF001C alternative SCTLR.V = 1 cannot
+   * be used because target area corersponds to PMM peripheral
+   * registers on TMS570).
+   *
+   * Alternative is to use jumps over SRAM based trampolines
+   * but that is not compatible with
+   *   Check TCRAM1 ECC error detection logic
+   * which intentionally introduces data abort during startup
+   * to check SRAM and if exception processing goes through
+   * SRAM then it leads to CPU error halt.
+   *
+   * So use of POM to replace jumps to vectors target
+   * addresses seems to be the best option.
+   */
+  if ( (uintptr_t)bsp_start_vector_table_begin != 0 ) {
+    tms570_pom_remap();
+  }
 
   /* Interrupts */
Index: c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk
===================================================================
--- c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk	(revision 2f95794e490018ccd721227edc302c720d8abb48)
+++ c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk	(revision 870ff8e9b6a1c0d7f51cfbdf809b64f774f1869f)
@@ -28,3 +28,5 @@
 bsp_stack_main_size = ALIGN (bsp_stack_main_size, bsp_stack_align);
 
+bsp_int_vec_overlay_start = ORIGIN(RAM_INT_VEC);
+
 INCLUDE linkcmds.armv4
Index: c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk_intram
===================================================================
--- c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk_intram	(revision 2f95794e490018ccd721227edc302c720d8abb48)
+++ c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk_intram	(revision 870ff8e9b6a1c0d7f51cfbdf809b64f774f1869f)
@@ -28,3 +28,5 @@
 bsp_stack_main_size = ALIGN (bsp_stack_main_size, bsp_stack_align);
 
+bsp_int_vec_overlay_start = ORIGIN(RAM_INT_VEC);
+
 INCLUDE linkcmds.armv4
Index: c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk_sdram
===================================================================
--- c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk_sdram	(revision 2f95794e490018ccd721227edc302c720d8abb48)
+++ c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk_sdram	(revision 870ff8e9b6a1c0d7f51cfbdf809b64f774f1869f)
@@ -28,3 +28,5 @@
 bsp_stack_main_size = ALIGN (bsp_stack_main_size, bsp_stack_align);
 
+bsp_int_vec_overlay_start = ORIGIN(RAM_INT_VEC);
+
 INCLUDE linkcmds.armv4
