Changeset 870ff8e9 in rtems for c/src/lib/libbsp/arm/tms570


Ignore:
Timestamp:
Nov 12, 2015, 10:11:31 PM (4 years ago)
Author:
Pavel Pisa <pisa@…>
Branches:
master
Children:
38404cb
Parents:
2f95794e
git-author:
Pavel Pisa <pisa@…> (11/12/15 22:11:31)
git-committer:
Gedare Bloom <gedare@…> (11/18/15 15:19:46)
Message:

bsp/tms570: use POM only when application image does not start at address 0.

Parameters overlay module is initialized and cleared first.
It is used later to replace exception target vectors
only if that is required.

The application loader code with CPU and SDRAM setup
code has to provide well defined pattern of instructions
at addresses 0x00000000 and 0x0000001f, because only data
read accesses can be processed reliably by POM. The expected
instruction pattern can be seen in the next example

https://github.com/hornmich/tms570ls3137-hdk-sdram/blob/master/SDRAM_SCI_configuration/source/sys_intvecs.asm

Comments with detailed description of code, background
and reasons for selected approach have been included
in TMS570 bsp startup code.

Signed-off-by: Pavel Pisa <pisa@…>
Signed-off-by: Premysl Houdek <kom541000@…>

Location:
c/src/lib/libbsp/arm/tms570
Files:
7 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/tms570/include/tms570-pom.h

    r2f95794e r870ff8e9  
    4949#define TMS570_POM_REGADDRMASK    ((1<<23)-1)
    5050
    51 
    52 int mem_dump(void *buf, unsigned long start, unsigned long len, int blen);
     51void tms570_initialize_and_clear(void);
    5352void tms570_pom_remap(void);
    5453
  • c/src/lib/libbsp/arm/tms570/irq/irq.c

    r2f95794e r870ff8e9  
    202202   */
    203203  sctlr &= ~(1 << 24);
     204  #if 0
     205    /*
     206     * Option to enable exception table bypass for interrupts
     207     *
     208     * Because RTEMS requires all interrupts to be serviced through
     209     * common _ARMV4_Exception_interrupt handler to allow task switching
     210     * on exit from interrupt working correctly, vim_vec cannot point
     211     * directly to individual vector handlers and need to point
     212     * to single entry path. But if TMS570_VIM.IRQINDEX is then used
     213     * to target execution to corresponding service then for some
     214     * peripherals (i.e. EMAC) interrupt is already acknowledged
     215     * by VIM and IRQINDEX is read as zero which leads to spurious
     216     * interrupt and peripheral not serviced/blocked.
     217     *
     218     * To analyze this behavior we used trampolines which setup
     219     * bsp_interrupt_vector_inject and pass execution to
     220     * _ARMV4_Exception_interrupt. It works but is more ugly than
     221     * use of POM remap for these cases where application does not
     222     * start at address 0x00000000. If RTEMS image is placed at
     223     * memory space beginning then no of these constructs is necessary.
     224     */
     225    sctlr |= 1 << 24;
     226  #endif
    204227  asm volatile ("mcr p15, 0, %0, c1, c0, 0\n": : "r" (sctlr));
    205228
  • c/src/lib/libbsp/arm/tms570/pom/tms570-pom.c

    r2f95794e r870ff8e9  
    2323#include <bsp/tms570-pom.h>
    2424#include <bsp/linker-symbols.h>
     25#include <rtems/score/armv4.h>
    2526#include <bsp.h>
     27
     28/*
     29 * Placement of exceptions target addresses in memory
     30 * when insructions with opcode 0xe59ff018
     31 *      ldr pc, [pc, #0x18]
     32 * are used to fill ARM exception vectors area
     33 */
     34typedef struct{
     35  uint32_t reserved1;
     36  uint32_t except_addr_undef;
     37  uint32_t except_addr_swi;
     38  uint32_t except_addr_prefetch;
     39  uint32_t except_addr_abort;
     40  uint32_t reserved2;
     41  uint32_t except_addr_irq;
     42  uint32_t except_addr_fiq;
     43}vec_remap_table;
     44
     45void bsp_block_on_exception(void);
     46
     47void bsp_block_on_exception(void){
     48  while(1);
     49}
     50
     51extern char bsp_int_vec_overlay_start[];
     52
     53/*
     54 * Global overlay target address holds shared MSB bits for all regions
     55 * It is set to linker RAM_INT_VEC region - i.e. area reserved
     56 * at internal SRAM memory start, address 0x08000000
     57 */
     58uint32_t pom_global_overlay_target_address_start =
     59                                 (uintptr_t)bsp_int_vec_overlay_start;
     60
     61/**
     62 * @brief initialize and clear parameters overlay module (POM)
     63 *
     64 * clears all remap regions. The actual POM enable is left to the first user.
     65 *
     66 * @retval Void
     67 */
     68void tms570_initialize_and_clear(void)
     69{
     70  int i;
     71
     72  TMS570_POM.GLBCTRL = 0 | (TMS570_POM_GLBCTRL_OTADDR(~0) &
     73                            pom_global_overlay_target_address_start);
     74
     75  for ( i = 0; i < TMS570_POM_REGIONS; ++i ) {
     76    TMS570_POM.REG[i].REGSIZE = TMS570_POM_REGSIZE_SIZE(TMS570_POM_REGSIZE_DISABLED);
     77  }
     78}
    2679
    2780/**
     
    3487void tms570_pom_remap(void)
    3588{
    36   int i;
    37   uint32_t vec_overlay_start = 0x08000000;
    38   uint32_t temp = 0;
     89  uint32_t vec_overlay_start = pom_global_overlay_target_address_start;
    3990
     91  /*
     92   * Copy RTEMS the first level exception processing code
     93   * to RAM area which can be used for later as POM overlay
     94   * of Flash vectors. The code is expected to have for of eight
     95   *   ldr pc, [pc,#0x18]
     96   * instructions followed by eight words with actual exception
     97   * service routines target addresses. This is case of RTEMS default
     98   * table found in
     99   *   c/src/lib/libbsp/arm/shared/start/start.S
     100   */
    40101  memcpy((void*)vec_overlay_start, bsp_start_vector_table_begin, 64);
    41102
    42   TMS570_POM.GLBCTRL = 0;
     103  #if 0
     104  {
     105    /* Fill exception table by catch error infinite loop for debugging */
     106    vec_remap_table* vec_table = (vec_remap_table*)(vec_overlay_start+32);
     107    vec_table->except_addr_undef = (uint32_t)bsp_block_on_exception;
     108    vec_table->except_addr_swi = (uint32_t)bsp_block_on_exception;
     109    vec_table->except_addr_prefetch = (uint32_t)bsp_block_on_exception;//_ARMV4_Exception_prefetch_abort;
     110    vec_table->except_addr_abort = (uint32_t)bsp_block_on_exception;//_ARMV4_Exception_data_abort;
     111    vec_table->except_addr_irq = (uint32_t)_ARMV4_Exception_interrupt;
     112    vec_table->except_addr_fiq = (uint32_t)bsp_block_on_exception;//_ARMV4_Exception_interrupt;
     113  }
     114  #endif
    43115
    44   for ( i = 0; i < TMS570_POM_REGIONS; ++i ) {
    45     TMS570_POM.REG[i].REGSIZE = TMS570_POM_REGSIZE_SIZE(TMS570_POM_REGSIZE_DISABLED);
    46   }
    47 
    48   TMS570_POM.REG[0].PROGSTART = TMS570_POM_PROGSTART_STARTADDRESS(0);
     116  /*
     117   * The overlay vectors replacement area cannot be used directly
     118   * to replace jump instructions on start of Flash because instruction
     119   * fetch through POM is not reliable supported (works in most times
     120   * but sometimes fails).
     121   * Area of 64 bytes starting at address 0x00000040 is replaced.
     122   * This way target addresses are placed between 0x00000060
     123   * and 0x0000007F. If boot loader startup code contains instructions
     124   *   ldr pc,[pc,#0x58]
     125   * (opcode 0xe59ff058) then the jump target addresses are replaced
     126   * by pointers to actual RTEMS exceptions service functions.
     127   */
     128  TMS570_POM.REG[0].PROGSTART = TMS570_POM_PROGSTART_STARTADDRESS(64);
    49129  TMS570_POM.REG[0].OVLSTART = TMS570_POM_OVLSTART_STARTADDRESS(vec_overlay_start);
    50130  TMS570_POM.REG[0].REGSIZE = TMS570_POM_REGSIZE_SIZE(TMS570_POM_REGSIZE_64B);
    51131  TMS570_POM.GLBCTRL = TMS570_POM_GLBCTRL_ON_OFF(0xa) |
    52132                       TMS570_POM_GLBCTRL_ETO(0xa) |
    53                        (TMS570_POM_GLBCTRL_OTADDR(~0) & vec_overlay_start);
     133                       (TMS570_POM_GLBCTRL_OTADDR(~0) &
     134                        pom_global_overlay_target_address_start);
    54135}
  • c/src/lib/libbsp/arm/tms570/startup/bspstart.c

    r2f95794e r870ff8e9  
    2828#include <bsp/start.h>
    2929#include <bsp/bootcard.h>
     30#include <bsp/linker-symbols.h>
     31#include <rtems/endian.h>
    3032
    3133void bsp_start( void )
    3234{
    33   /* set the cpu mode to supervisor and big endian */
    34   arm_cpu_mode = 0x213;
     35  #if BYTE_ORDER == BIG_ENDIAN
     36    /*
     37     * If CPU is big endian (TMS570 family variant)
     38     * set the CPU mode to supervisor and big endian.
     39     * Do not set mode if CPU is little endian
     40     * (RM48 family variant) for which default mode 0x13
     41     * defined in cpukit/score/cpu/arm/cpu.c
     42     * is right.
     43     */
     44    arm_cpu_mode = 0x213;
     45  #endif
    3546
    36   tms570_pom_remap();
     47  tms570_initialize_and_clear();
     48
     49  /*
     50   * If RTEMS image does not start at address 0x00000000
     51   * then first level exception table at memory begin has
     52   * to be replaced to point to RTEMS handlers addresses.
     53   *
     54   * There is no VBAR or other option because Cortex-R
     55   * does provides only fixed address 0x00000000 for exceptions
     56   * (0xFFFF0000-0xFFFF001C alternative SCTLR.V = 1 cannot
     57   * be used because target area corersponds to PMM peripheral
     58   * registers on TMS570).
     59   *
     60   * Alternative is to use jumps over SRAM based trampolines
     61   * but that is not compatible with
     62   *   Check TCRAM1 ECC error detection logic
     63   * which intentionally introduces data abort during startup
     64   * to check SRAM and if exception processing goes through
     65   * SRAM then it leads to CPU error halt.
     66   *
     67   * So use of POM to replace jumps to vectors target
     68   * addresses seems to be the best option.
     69   */
     70  if ( (uintptr_t)bsp_start_vector_table_begin != 0 ) {
     71    tms570_pom_remap();
     72  }
    3773
    3874  /* Interrupts */
  • c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk

    r2f95794e r870ff8e9  
    2828bsp_stack_main_size = ALIGN (bsp_stack_main_size, bsp_stack_align);
    2929
     30bsp_int_vec_overlay_start = ORIGIN(RAM_INT_VEC);
     31
    3032INCLUDE linkcmds.armv4
  • c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk_intram

    r2f95794e r870ff8e9  
    2828bsp_stack_main_size = ALIGN (bsp_stack_main_size, bsp_stack_align);
    2929
     30bsp_int_vec_overlay_start = ORIGIN(RAM_INT_VEC);
     31
    3032INCLUDE linkcmds.armv4
  • c/src/lib/libbsp/arm/tms570/startup/linkcmds.tms570ls3137_hdk_sdram

    r2f95794e r870ff8e9  
    2828bsp_stack_main_size = ALIGN (bsp_stack_main_size, bsp_stack_align);
    2929
     30bsp_int_vec_overlay_start = ORIGIN(RAM_INT_VEC);
     31
    3032INCLUDE linkcmds.armv4
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