Changeset 86748ff in rtems
- Timestamp:
- 10/24/00 21:50:37 (23 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 5b53d97
- Parents:
- fda47cd
- Location:
- c/src/lib/libbsp/mips/p4000
- Files:
-
- 5 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/mips/p4000/ChangeLog
rfda47cd r86748ff 1 2000-10-24 Alan Cudmore <alanc@linuxstart.com> and 2 Joel Sherrill <joel@OARcorp.com> 3 4 * This is a major reworking of the mips64orion port to use 5 gcc predefines as much as possible and a big push to multilib 6 the mips port. The mips64orion port was copied/renamed to mips 7 to be more like other GNU tools. Alan did most of the technical 8 work of determining how to map old macro names used by the mips64orion 9 port to standard compiler macro definitions. Joel did the merge 10 with CVS magic to keep individual file history and did the BSP 11 modifications. Details follow: 12 * console/led.S: Switch from using <idtmon.h> to <asm.h>. 13 * console/start.S: Switch from using <idtmon.h> to <asm.h>. Added 14 define of PMON stacksize. 15 * console/idtmem.S: Switch from using <idtmon.h> to <asm.h>. Also 16 reworked conditionals to use gcc predefines. 17 * console/idttlb.S: Ditto. 18 1 19 2000-09-04 Ralf Corsepius <corsepiu@faw.uni-ulm.de> 2 20 -
c/src/lib/libbsp/mips/p4000/console/led.S
rfda47cd r86748ff 4 4 5 5 #include <iregdef.h> 6 #include <idtmon.h>7 6 #include <idtcpu.h> 7 #include <asm.h> 8 8 9 9 -
c/src/lib/libbsp/mips/p4000/start/start.S
rfda47cd r86748ff 34 34 #include <iregdef.h> 35 35 #include <idtcpu.h> 36 #include < idtmon.h>36 #include <asm.h> 37 37 38 38 … … 213 213 214 214 215 /* 216 * P_STACKSIZE is the size of the Prom Stack. 217 * the prom stack grows downward 218 */ 219 #define P_STACKSIZE 0x2000 /* sets stack size to 8k */ 220 215 221 216 222 /************************************************************************** -
c/src/lib/libbsp/mips/p4000/startup/idtmem.S
rfda47cd r86748ff 41 41 #include <iregdef.h> 42 42 #include <idtcpu.h> 43 #include < idtmon.h>43 #include <asm.h> 44 44 45 45 .data … … 49 49 .word 0 50 50 icache_size: 51 #if defined(CPU_R3000)51 #if __mips == 1 52 52 .word MINCACHE 53 53 #endif 54 #if defined(CPU_R4000)54 #if __mips == 3 55 55 .word 0 56 56 #endif 57 57 58 #if defined(CPU_R4000)58 #if __mips == 3 59 59 .data 60 60 scache_size: … … 71 71 .text 72 72 73 #if defined (CPU_R3000)73 #if __mips == 1 74 74 #define CONFIGFRM ((2*4)+4) 75 75 … … 403 403 404 404 ENDFRAME(get_mem_conf) 405 #endif /* defined CPU_R3000*/406 407 #if defined(CPU_R4000)405 #endif /* __mips == 1 */ 406 407 #if __mips == 3 408 408 #define LEAF(label) FRAME(label,sp,0,ra) 409 409 #define XLEAF(label) \ … … 923 923 ENDFRAME(get_mem_conf) 924 924 925 #endif /* defined(CPU_R4000)*/925 #endif /* __mips == 3 */ 926 926 927 927 /* -
c/src/lib/libbsp/mips/p4000/startup/idttlb.S
rfda47cd r86748ff 33 33 #include <iregdef.h> 34 34 #include <idtcpu.h> 35 #include < idtmon.h>35 #include <asm.h> 36 36 37 37 38 38 .text 39 39 40 #if defined(CPU_R3000)40 #if __mips == 1 41 41 /* 42 42 ** ret_tlblo -- returns the 'entrylo' contents for the TLB … … 65 65 ENDFRAME(ret_tlblo) 66 66 #endif 67 #if defined(CPU_R4000)67 #if __mips == 3 68 68 /* 69 69 ** ret_tlblo[01] -- returns the 'entrylo' contents for the TLB … … 143 143 */ 144 144 FRAME(ret_tlbhi,sp,0,ra) 145 #if defined(CPU_R3000)145 #if __mips == 1 146 146 .set noreorder 147 147 mfc0 t0,C0_SR # save sr … … 162 162 .set reorder 163 163 #endif 164 #if defined(CPU_R4000)164 #if __mips == 3 165 165 mfc0 t0,C0_SR # save sr 166 166 mtc0 zero,C0_SR # disable interrupts … … 185 185 */ 186 186 FRAME(ret_tlbpid,sp,0,ra) 187 #if defined(CPU_R3000)187 #if __mips == 1 188 188 .set noreorder 189 189 mfc0 v0,C0_TLBHI # fetch tlb high … … 195 195 .set reorder 196 196 #endif 197 #if defined(CPU_R4000)197 #if __mips == 3 198 198 mfc0 v0,C0_TLBHI # to return value 199 199 nop … … 215 215 */ 216 216 FRAME(tlbprobe,sp,0,ra) 217 #if defined(CPU_R3000)217 #if __mips == 1 218 218 .set noreorder 219 219 mfc0 t0,C0_SR /* fetch status reg */ … … 241 241 .set reorder 242 242 #endif 243 #if defined(CPU_R4000)243 #if __mips == 3 244 244 mfc0 t0,C0_SR # save sr 245 245 mtc0 zero,C0_SR # disable interrupts … … 270 270 */ 271 271 FRAME(resettlb,sp,0,ra) 272 #if defined(CPU_R3000)272 #if __mips == 1 273 273 .set noreorder 274 274 mfc0 t0,C0_TLBHI # fetch the current hi … … 290 290 .set reorder 291 291 #endif 292 #if defined(CPU_R4000)292 #if __mips == 3 293 293 li t2,K0BASE&TLBHI_VPN2MASK 294 294 mfc0 t0,C0_TLBHI # save current TLBHI … … 312 312 ENDFRAME(resettlb) 313 313 314 #if defined(CPU_R3000)314 #if __mips == 1 315 315 /* 316 316 ** Setup TLB entry … … 341 341 .set reorder 342 342 ENDFRAME(map_tlb) 343 344 #if defined(CPU_R4000)343 #endif 344 #if __mips == 3 345 345 /* 346 346 ** Setup R4000 TLB entry
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