Changeset 861d315 in rtems


Ignore:
Timestamp:
Nov 19, 2014, 1:05:36 PM (5 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
d53de34
Parents:
f2fed0c1
git-author:
Sebastian Huber <sebastian.huber@…> (11/19/14 13:05:36)
git-committer:
Sebastian Huber <sebastian.huber@…> (11/20/14 09:30:27)
Message:

bsps/arm: L2C 310 use L2C_310_* prefix throughout

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h

    rf2fed0c1 r861d315  
    7777#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS
    7878
    79 #define CACHE_L2C_310_DATA_LINE_MASK ( CPU_DATA_CACHE_ALIGNMENT - 1 )
    80 #define CACHE_L2C_310_INSTRUCTION_LINE_MASK \
     79#define L2C_310_DATA_LINE_MASK ( CPU_DATA_CACHE_ALIGNMENT - 1 )
     80#define L2C_310_INSTRUCTION_LINE_MASK \
    8181  ( CPU_INSTRUCTION_CACHE_ALIGNMENT \
    8282    - 1 )
    83 #define CACHE_l2C_310_NUM_WAYS 8
    84 #define CACHE_l2C_310_WAY_MASK ( ( 1 << CACHE_l2C_310_NUM_WAYS ) - 1 )
    85 
    86 #define CACHE_MIN( a, b ) \
     83#define L2C_310_NUM_WAYS 8
     84#define L2C_310_WAY_MASK ( ( 1 << L2C_310_NUM_WAYS ) - 1 )
     85
     86#define L2C_310_MIN( a, b ) \
    8787  ((a < b) ? (a) : (b))
    8888
    89 #define CACHE_MAX_LOCKING_BYTES (4 * 1024)
     89#define L2C_310_MAX_LOCKING_BYTES (4 * 1024)
    9090
    9191
    9292/* RTL release number as can be read from cache_id register */
    9393typedef enum {
    94   CACHE_L2C_310_RTL_RELEASE_R0_P0 = 0x0,
    95   CACHE_L2C_310_RTL_RELEASE_R1_P0 = 0x2,
    96   CACHE_L2C_310_RTL_RELEASE_R2_P0 = 0x4,
    97   CACHE_L2C_310_RTL_RELEASE_R3_P0 = 0x5,
    98   CACHE_L2C_310_RTL_RELEASE_R3_P1 = 0x6,
    99   CACHE_L2C_310_RTL_RELEASE_R3_P2 = 0x8,
    100   CACHE_L2C_310_RTL_RELEASE_R3_P3 = 0x9
     94  L2C_310_RTL_RELEASE_R0_P0 = 0x0,
     95  L2C_310_RTL_RELEASE_R1_P0 = 0x2,
     96  L2C_310_RTL_RELEASE_R2_P0 = 0x4,
     97  L2C_310_RTL_RELEASE_R3_P0 = 0x5,
     98  L2C_310_RTL_RELEASE_R3_P1 = 0x6,
     99  L2C_310_RTL_RELEASE_R3_P2 = 0x8,
     100  L2C_310_RTL_RELEASE_R3_P3 = 0x9
    101101} cache_l2c_310_rtl_release;
    102102
     
    115115  /** @brief Cache ID */
    116116  uint32_t cache_id;
    117 #define CACHE_L2C_310_L2CC_ID_RTL_MASK 0x3f
    118 #define CACHE_L2C_310_L2CC_ID_PART_MASK ( 0xf << 6 )
    119 #define CACHE_L2C_310_L2CC_ID_PART_L210 ( 1 << 6 )
    120 #define CACHE_L2C_310_L2CC_ID_PART_L310 ( 3 << 6 )
    121 #define CACHE_L2C_310_L2CC_ID_IMPL_MASK ( 0xff << 24 )
     117#define L2C_310_ID_RTL_MASK 0x3f
     118#define L2C_310_ID_PART_MASK ( 0xf << 6 )
     119#define L2C_310_ID_PART_L210 ( 1 << 6 )
     120#define L2C_310_ID_PART_L310 ( 3 << 6 )
     121#define L2C_310_ID_IMPL_MASK ( 0xff << 24 )
    122122  /** @brief Cache type */
    123123  uint32_t cache_type;
    124124/** @brief 1 if data banking implemented, 0 if not */
    125 #define CACHE_L2C_310_L2CC_TYPE_DATA_BANKING_MASK 0x80000000
     125#define L2C_310_TYPE_DATA_BANKING_MASK 0x80000000
    126126/** @brief 11xy, where: x=1 if pl310_LOCKDOWN_BY_MASTER is defined, otherwise 0 */
    127 #define CACHE_L2C_310_L2CC_TYPE_CTYPE_MASK 0x1E000000
     127#define L2C_310_TYPE_CTYPE_MASK 0x1E000000
    128128/** @brief y=1 if pl310_LOCKDOWN_BY_LINE is defined, otherwise 0. */
    129 #define CACHE_L2C_310_L2CC_TYPE_CTYPE_SHIFT 25
     129#define L2C_310_TYPE_CTYPE_SHIFT 25
    130130/** @brief 1 for Harvard architecture, 0 for unified architecture */
    131 #define CACHE_L2C_310_L2CC_TYPE_HARVARD_MASK 0x01000000
     131#define L2C_310_TYPE_HARVARD_MASK 0x01000000
    132132/** @brief Data cache way size = 2 Exp(value + 2) KB */
    133 #define CACHE_L2C_310_L2CC_TYPE_SIZE_D_WAYS_MASK 0x00700000
    134 #define CACHE_L2C_310_L2CC_TYPE_SIZE_D_WAYS_SHIFT 20
     133#define L2C_310_TYPE_SIZE_D_WAYS_MASK 0x00700000
     134#define L2C_310_TYPE_SIZE_D_WAYS_SHIFT 20
    135135/** @brief Assoziativity aka number of data ways = (value * 8) + 8 */
    136 #define CACHE_L2C_310_L2CC_TYPE_NUM_D_WAYS_MASK 0x00040000
    137 #define CACHE_L2C_310_L2CC_TYPE_NUM_D_WAYS_SHIFT 18
     136#define L2C_310_TYPE_NUM_D_WAYS_MASK 0x00040000
     137#define L2C_310_TYPE_NUM_D_WAYS_SHIFT 18
    138138/** @brief Data cache line length 00 - 32 */
    139 #define CACHE_L2C_310_L2CC_TYPE_LENGTH_D_LINE_MASK 0x00003000
    140 #define CACHE_L2C_310_L2CC_TYPE_LENGTH_D_LINE_SHIFT 12
    141 #define CACHE_L2C_310_L2CC_TYPE_LENGTH_D_LINE_VAL_32 0x0
     139#define L2C_310_TYPE_LENGTH_D_LINE_MASK 0x00003000
     140#define L2C_310_TYPE_LENGTH_D_LINE_SHIFT 12
     141#define L2C_310_TYPE_LENGTH_D_LINE_VAL_32 0x0
    142142/** @brief Instruction cache way size = 2 Exp(value + 2) KB */
    143 #define CACHE_L2C_310_L2CC_TYPE_SIZE_I_WAYS_MASK 0x00000700
    144 #define CACHE_L2C_310_L2CC_TYPE_SIZE_I_WAYS_SHIFT 8
     143#define L2C_310_TYPE_SIZE_I_WAYS_MASK 0x00000700
     144#define L2C_310_TYPE_SIZE_I_WAYS_SHIFT 8
    145145/** @brief Assoziativity aka number of instruction ways = (value * 8) + 8 */
    146 #define CACHE_L2C_310_L2CC_TYPE_NUM_I_WAYS_MASK 0x00000040
    147 #define CACHE_L2C_310_L2CC_TYPE_NUM_I_WAYS_SHIFT 6
     146#define L2C_310_TYPE_NUM_I_WAYS_MASK 0x00000040
     147#define L2C_310_TYPE_NUM_I_WAYS_SHIFT 6
    148148/** @brief Instruction cache line length 00 - 32 */
    149 #define CACHE_L2C_310_L2CC_TYPE_LENGTH_I_LINE_MASK 0x00000003
    150 #define CACHE_L2C_310_L2CC_TYPE_LENGTH_I_LINE_SHIFT 0
    151 #define CACHE_L2C_310_L2CC_TYPE_LENGTH_I_LINE_VAL_32 0x0
     149#define L2C_310_TYPE_LENGTH_I_LINE_MASK 0x00000003
     150#define L2C_310_TYPE_LENGTH_I_LINE_SHIFT 0
     151#define L2C_310_TYPE_LENGTH_I_LINE_VAL_32 0x0
    152152
    153153  uint8_t reserved_8[0x100 - 8];
    154154  uint32_t ctrl; /* Control */
    155155/** @brief Enables the L2CC */
    156 #define CACHE_L2C_310_L2CC_ENABLE_MASK 0x00000001
     156#define L2C_310_ENABLE_MASK 0x00000001
    157157
    158158  /** @brief Auxiliary control */
     
    160160
    161161/** @brief Early BRESP Enable */
    162 #define CACHE_L2C_310_L2CC_AUX_EBRESPE_MASK 0x40000000
     162#define L2C_310_AUX_EBRESPE_MASK 0x40000000
    163163
    164164/** @brief Instruction Prefetch Enable */
    165 #define CACHE_L2C_310_L2CC_AUX_IPFE_MASK 0x20000000
     165#define L2C_310_AUX_IPFE_MASK 0x20000000
    166166
    167167/** @brief Data Prefetch Enable */
    168 #define CACHE_L2C_310_L2CC_AUX_DPFE_MASK 0x10000000
     168#define L2C_310_AUX_DPFE_MASK 0x10000000
    169169
    170170/** @brief Non-secure interrupt access control */
    171 #define CACHE_L2C_310_L2CC_AUX_NSIC_MASK 0x08000000
     171#define L2C_310_AUX_NSIC_MASK 0x08000000
    172172
    173173/** @brief Non-secure lockdown enable */
    174 #define CACHE_L2C_310_L2CC_AUX_NSLE_MASK 0x04000000
     174#define L2C_310_AUX_NSLE_MASK 0x04000000
    175175
    176176/** @brief Cache replacement policy */
    177 #define CACHE_L2C_310_L2CC_AUX_CRP_MASK 0x02000000
     177#define L2C_310_AUX_CRP_MASK 0x02000000
    178178
    179179/** @brief Force write allocate */
    180 #define CACHE_L2C_310_L2CC_AUX_FWE_MASK 0x01800000
     180#define L2C_310_AUX_FWE_MASK 0x01800000
    181181
    182182/** @brief Shared attribute override enable */
    183 #define CACHE_L2C_310_L2CC_AUX_SAOE_MASK 0x00400000
     183#define L2C_310_AUX_SAOE_MASK 0x00400000
    184184
    185185/** @brief Parity enable */
    186 #define CACHE_L2C_310_L2CC_AUX_PE_MASK 0x00200000
     186#define L2C_310_AUX_PE_MASK 0x00200000
    187187
    188188/** @brief Event monitor bus enable */
    189 #define CACHE_L2C_310_L2CC_AUX_EMBE_MASK 0x00100000
     189#define L2C_310_AUX_EMBE_MASK 0x00100000
    190190
    191191/** @brief Way-size */
    192 #define CACHE_L2C_310_L2CC_AUX_WAY_SIZE_MASK 0x000E0000
    193 #define CACHE_L2C_310_L2CC_AUX_WAY_SIZE_SHIFT 17
     192#define L2C_310_AUX_WAY_SIZE_MASK 0x000E0000
     193#define L2C_310_AUX_WAY_SIZE_SHIFT 17
    194194
    195195/** @brief Way-size */
    196 #define CACHE_L2C_310_L2CC_AUX_ASSOC_MASK 0x00010000
     196#define L2C_310_AUX_ASSOC_MASK 0x00010000
    197197
    198198/** @brief Shared attribute invalidate enable */
    199 #define CACHE_L2C_310_L2CC_AUX_SAIE_MASK 0x00002000
     199#define L2C_310_AUX_SAIE_MASK 0x00002000
    200200
    201201/** @brief Exclusive cache configuration */
    202 #define CACHE_L2C_310_L2CC_AUX_EXCL_CACHE_MASK 0x00001000
     202#define L2C_310_AUX_EXCL_CACHE_MASK 0x00001000
    203203
    204204/** @brief Store buffer device limitation Enable */
    205 #define CACHE_L2C_310_L2CC_AUX_SBDLE_MASK 0x00000800
     205#define L2C_310_AUX_SBDLE_MASK 0x00000800
    206206
    207207/** @brief High Priority for SO and Dev Reads Enable */
    208 #define CACHE_L2C_310_L2CC_AUX_HPSODRE_MASK 0x00000400
     208#define L2C_310_AUX_HPSODRE_MASK 0x00000400
    209209
    210210/** @brief Full line of zero enable */
    211 #define CACHE_L2C_310_L2CC_AUX_FLZE_MASK 0x00000001
     211#define L2C_310_AUX_FLZE_MASK 0x00000001
    212212
    213213/** @brief Enable all prefetching, */
    214 #define CACHE_L2C_310_L2CC_AUX_REG_DEFAULT_MASK \
    215   ( CACHE_L2C_310_L2CC_AUX_WAY_SIZE_MASK & ( 0x3 << CACHE_L2C_310_L2CC_AUX_WAY_SIZE_SHIFT ) ) \
    216   | CACHE_L2C_310_L2CC_AUX_PE_MASK      /* Prefetch enable */ \
    217   | CACHE_L2C_310_L2CC_AUX_SAOE_MASK    /* Shared attribute override enable */ \
    218   | CACHE_L2C_310_L2CC_AUX_CRP_MASK     /* Cache replacement policy */ \
    219   | CACHE_L2C_310_L2CC_AUX_DPFE_MASK    /* Data prefetch enable */ \
    220   | CACHE_L2C_310_L2CC_AUX_IPFE_MASK    /* Instruction prefetch enable */ \
    221   | CACHE_L2C_310_L2CC_AUX_EBRESPE_MASK /* Early BRESP enable */
    222 
    223 #define CACHE_L2C_310_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFF
     214#define L2C_310_AUX_REG_DEFAULT_MASK \
     215  ( L2C_310_AUX_WAY_SIZE_MASK & ( 0x3 << L2C_310_AUX_WAY_SIZE_SHIFT ) ) \
     216  | L2C_310_AUX_PE_MASK      /* Prefetch enable */ \
     217  | L2C_310_AUX_SAOE_MASK    /* Shared attribute override enable */ \
     218  | L2C_310_AUX_CRP_MASK     /* Cache replacement policy */ \
     219  | L2C_310_AUX_DPFE_MASK    /* Data prefetch enable */ \
     220  | L2C_310_AUX_IPFE_MASK    /* Instruction prefetch enable */ \
     221  | L2C_310_AUX_EBRESPE_MASK /* Early BRESP enable */
     222
     223#define L2C_310_AUX_REG_ZERO_MASK 0xFFF1FFFF
    224224
    225225/** @brief 1 cycle of latency, there is no additional latency fot tag RAM */
    226 #define CACHE_L2C_310_L2CC_RAM_1_CYCLE_LAT_VAL 0x00000000
     226#define L2C_310_RAM_1_CYCLE_LAT_VAL 0x00000000
    227227/** @brief 2 cycles of latency for tag RAM */
    228 #define CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL 0x00000001
     228#define L2C_310_RAM_2_CYCLE_LAT_VAL 0x00000001
    229229/** @brief 3 cycles of latency for tag RAM */
    230 #define CACHE_L2C_310_L2CC_RAM_3_CYCLE_LAT_VAL 0x00000002
     230#define L2C_310_RAM_3_CYCLE_LAT_VAL 0x00000002
    231231/** @brief 4 cycles of latency for tag RAM */
    232 #define CACHE_L2C_310_L2CC_RAM_4_CYCLE_LAT_VAL 0x00000003
     232#define L2C_310_RAM_4_CYCLE_LAT_VAL 0x00000003
    233233/** @brief 5 cycles of latency for tag RAM */
    234 #define CACHE_L2C_310_L2CC_RAM_5_CYCLE_LAT_VAL 0x00000004
     234#define L2C_310_RAM_5_CYCLE_LAT_VAL 0x00000004
    235235/** @brief 6 cycles of latency for tag RAM */
    236 #define CACHE_L2C_310_L2CC_RAM_6_CYCLE_LAT_VAL 0x00000005
     236#define L2C_310_RAM_6_CYCLE_LAT_VAL 0x00000005
    237237/** @brief 7 cycles of latency for tag RAM */
    238 #define CACHE_L2C_310_L2CC_RAM_7_CYCLE_LAT_VAL 0x00000006
     238#define L2C_310_RAM_7_CYCLE_LAT_VAL 0x00000006
    239239/** @brief 8 cycles of latency for tag RAM */
    240 #define CACHE_L2C_310_L2CC_RAM_8_CYCLE_LAT_VAL 0x00000007
     240#define L2C_310_RAM_8_CYCLE_LAT_VAL 0x00000007
    241241/** @brief Shift left setup latency values by this value */
    242 #define CACHE_L2C_310_L2CC_RAM_SETUP_SHIFT 0x00000000
     242#define L2C_310_RAM_SETUP_SHIFT 0x00000000
    243243/** @brief Shift left read latency values by this value */
    244 #define CACHE_L2C_310_L2CC_RAM_READ_SHIFT 0x00000004
     244#define L2C_310_RAM_READ_SHIFT 0x00000004
    245245/** @brief Shift left write latency values by this value */
    246 #define CACHE_L2C_310_L2CC_RAM_WRITE_SHIFT 0x00000008
     246#define L2C_310_RAM_WRITE_SHIFT 0x00000008
    247247/** @brief Mask for RAM setup latency */
    248 #define CACHE_L2C_310_L2CC_RAM_SETUP_LAT_MASK 0x00000007
     248#define L2C_310_RAM_SETUP_LAT_MASK 0x00000007
    249249/** @brief Mask for RAM read latency */
    250 #define CACHE_L2C_310_L2CC_RAM_READ_LAT_MASK 0x00000070
     250#define L2C_310_RAM_READ_LAT_MASK 0x00000070
    251251/** @brief Mask for RAM read latency */
    252 #define CACHE_L2C_310_L2CC_RAM_WRITE_LAT_MASK 0x00000700
     252#define L2C_310_RAM_WRITE_LAT_MASK 0x00000700
    253253  /** @brief Latency for tag RAM */
    254254  uint32_t tag_ram_ctrl;
    255255/* @brief Latency for tag RAM */
    256 #define CACHE_L2C_310_L2CC_TAG_RAM_DEFAULT_LAT \
    257   ( ( CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_SETUP_SHIFT ) \
    258     | ( CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_READ_SHIFT ) \
    259     | ( CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_WRITE_SHIFT ) )
     256#define L2C_310_TAG_RAM_DEFAULT_LAT \
     257  ( ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_SETUP_SHIFT ) \
     258    | ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_READ_SHIFT ) \
     259    | ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_WRITE_SHIFT ) )
    260260  /** @brief Latency for data RAM */
    261261  uint32_t data_ram_ctrl;
    262262/** @brief Latency for data RAM */
    263 #define CACHE_L2C_310_L2CC_DATA_RAM_DEFAULT_MASK \
    264   ( ( CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_SETUP_SHIFT ) \
    265     | ( CACHE_L2C_310_L2CC_RAM_3_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_READ_SHIFT ) \
    266     | ( CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_WRITE_SHIFT ) )
     263#define L2C_310_DATA_RAM_DEFAULT_MASK \
     264  ( ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_SETUP_SHIFT ) \
     265    | ( L2C_310_RAM_3_CYCLE_LAT_VAL << L2C_310_RAM_READ_SHIFT ) \
     266    | ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_WRITE_SHIFT ) )
    267267
    268268  uint8_t reserved_110[0x200 - 0x110];
     
    302302
    303303/** @brief DECERR from L3 */
    304 #define CACHE_L2C_310_L2CC_INT_DECERR_MASK 0x00000100
     304#define L2C_310_INT_DECERR_MASK 0x00000100
    305305
    306306/** @brief SLVERR from L3 */
    307 #define CACHE_L2C_310_L2CC_INT_SLVERR_MASK 0x00000080
     307#define L2C_310_INT_SLVERR_MASK 0x00000080
    308308
    309309/** @brief Error on L2 data RAM (Read) */
    310 #define CACHE_L2C_310_L2CC_INT_ERRRD_MASK 0x00000040
     310#define L2C_310_INT_ERRRD_MASK 0x00000040
    311311
    312312/** @brief Error on L2 tag RAM (Read) */
    313 #define CACHE_L2C_310_L2CC_INT_ERRRT_MASK 0x00000020
     313#define L2C_310_INT_ERRRT_MASK 0x00000020
    314314
    315315/** @brief Error on L2 data RAM (Write) */
    316 #define CACHE_L2C_310_L2CC_INT_ERRWD_MASK 0x00000010
     316#define L2C_310_INT_ERRWD_MASK 0x00000010
    317317
    318318/** @brief Error on L2 tag RAM (Write) */
    319 #define CACHE_L2C_310_L2CC_INT_ERRWT_MASK 0x00000008
     319#define L2C_310_INT_ERRWT_MASK 0x00000008
    320320
    321321/** @brief Parity Error on L2 data RAM (Read) */
    322 #define CACHE_L2C_310_L2CC_INT_PARRD_MASK 0x00000004
     322#define L2C_310_INT_PARRD_MASK 0x00000004
    323323
    324324/** @brief Parity Error on L2 tag RAM (Read) */
    325 #define CACHE_L2C_310_L2CC_INT_PARRT_MASK 0x00000002
     325#define L2C_310_INT_PARRT_MASK 0x00000002
    326326
    327327/** @brief Event Counter1/0 Overflow Increment */
    328 #define CACHE_L2C_310_L2CC_INT_ECNTR_MASK 0x00000001
     328#define L2C_310_INT_ECNTR_MASK 0x00000001
    329329
    330330/** @} */
     
    433433
    434434/** @brief Address filtering valid bits*/
    435 #define CACHE_L2C_310_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000
     435#define L2C_310_ADDR_FILTER_VALID_MASK 0xFFF00000
    436436
    437437/** @brief Address filtering enable bit*/
    438 #define CACHE_L2C_310_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001
     438#define L2C_310_ADDR_FILTER_ENABLE_MASK 0x00000001
    439439
    440440  uint8_t reserved_c08[0xf40 - 0xc08];
     
    444444
    445445/** @brief Debug SPIDEN bit */
    446 #define CACHE_L2C_310_L2CC_DEBUG_SPIDEN_MASK 0x00000004
     446#define L2C_310_DEBUG_SPIDEN_MASK 0x00000004
    447447
    448448/** @brief Debug DWB bit, forces write through */
    449 #define CACHE_L2C_310_L2CC_DEBUG_DWB_MASK 0x00000002
     449#define L2C_310_DEBUG_DWB_MASK 0x00000002
    450450
    451451/** @brief Debug DCL bit, disables cache line fill */
    452 #define CACHE_L2C_310_L2CC_DEBUG_DCL_MASK 0x00000002
     452#define L2C_310_DEBUG_DCL_MASK 0x00000002
    453453
    454454  uint8_t reserved_f44[0xf60 - 0xf44];
     
    457457  uint32_t prefetch_ctrl;
    458458/** @brief Prefetch offset */
    459 #define CACHE_L2C_310_L2CC_PREFETCH_OFFSET_MASK 0x0000001F
     459#define L2C_310_PREFETCH_OFFSET_MASK 0x0000001F
    460460  uint8_t reserved_f64[0xf80 - 0xf64];
    461461
     
    485485
    486486  switch ( rtl_release ) {
    487     case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    488     case CACHE_L2C_310_RTL_RELEASE_R3_P2:
    489     case CACHE_L2C_310_RTL_RELEASE_R3_P1:
    490     case CACHE_L2C_310_RTL_RELEASE_R2_P0:
    491     case CACHE_L2C_310_RTL_RELEASE_R1_P0:
    492     case CACHE_L2C_310_RTL_RELEASE_R0_P0:
     487    case L2C_310_RTL_RELEASE_R3_P3:
     488    case L2C_310_RTL_RELEASE_R3_P2:
     489    case L2C_310_RTL_RELEASE_R3_P1:
     490    case L2C_310_RTL_RELEASE_R2_P0:
     491    case L2C_310_RTL_RELEASE_R1_P0:
     492    case L2C_310_RTL_RELEASE_R0_P0:
    493493      is_applicable = false;
    494494      break;
    495     case CACHE_L2C_310_RTL_RELEASE_R3_P0:
     495    case L2C_310_RTL_RELEASE_R3_P0:
    496496      is_applicable = true;
    497497      break;
     
    511511
    512512  switch ( rtl_release ) {
    513     case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    514     case CACHE_L2C_310_RTL_RELEASE_R3_P2:
    515     case CACHE_L2C_310_RTL_RELEASE_R3_P1:
    516     case CACHE_L2C_310_RTL_RELEASE_R2_P0:
    517     case CACHE_L2C_310_RTL_RELEASE_R1_P0:
    518     case CACHE_L2C_310_RTL_RELEASE_R0_P0:
     513    case L2C_310_RTL_RELEASE_R3_P3:
     514    case L2C_310_RTL_RELEASE_R3_P2:
     515    case L2C_310_RTL_RELEASE_R3_P1:
     516    case L2C_310_RTL_RELEASE_R2_P0:
     517    case L2C_310_RTL_RELEASE_R1_P0:
     518    case L2C_310_RTL_RELEASE_R0_P0:
    519519      is_applicable = false;
    520520      break;
    521     case CACHE_L2C_310_RTL_RELEASE_R3_P0:
     521    case L2C_310_RTL_RELEASE_R3_P0:
    522522      is_applicable = true;
    523523      break;
     
    537537
    538538  switch ( rtl_release ) {
    539     case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    540     case CACHE_L2C_310_RTL_RELEASE_R3_P2:
    541     case CACHE_L2C_310_RTL_RELEASE_R3_P1:
    542     case CACHE_L2C_310_RTL_RELEASE_R2_P0:
    543     case CACHE_L2C_310_RTL_RELEASE_R1_P0:
    544     case CACHE_L2C_310_RTL_RELEASE_R0_P0:
     539    case L2C_310_RTL_RELEASE_R3_P3:
     540    case L2C_310_RTL_RELEASE_R3_P2:
     541    case L2C_310_RTL_RELEASE_R3_P1:
     542    case L2C_310_RTL_RELEASE_R2_P0:
     543    case L2C_310_RTL_RELEASE_R1_P0:
     544    case L2C_310_RTL_RELEASE_R0_P0:
    545545      is_applicable = false;
    546546      break;
    547     case CACHE_L2C_310_RTL_RELEASE_R3_P0:
     547    case L2C_310_RTL_RELEASE_R3_P0:
    548548      is_applicable = true;
    549549      break;
     
    563563
    564564  switch ( rtl_release ) {
    565     case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    566     case CACHE_L2C_310_RTL_RELEASE_R3_P2:
    567     case CACHE_L2C_310_RTL_RELEASE_R3_P1:
    568     case CACHE_L2C_310_RTL_RELEASE_R1_P0:
    569     case CACHE_L2C_310_RTL_RELEASE_R0_P0:
     565    case L2C_310_RTL_RELEASE_R3_P3:
     566    case L2C_310_RTL_RELEASE_R3_P2:
     567    case L2C_310_RTL_RELEASE_R3_P1:
     568    case L2C_310_RTL_RELEASE_R1_P0:
     569    case L2C_310_RTL_RELEASE_R0_P0:
    570570      is_applicable = false;
    571571      break;
    572     case CACHE_L2C_310_RTL_RELEASE_R3_P0:
    573     case CACHE_L2C_310_RTL_RELEASE_R2_P0:
     572    case L2C_310_RTL_RELEASE_R3_P0:
     573    case L2C_310_RTL_RELEASE_R2_P0:
    574574      is_applicable = true;
    575575      break;
     
    589589
    590590  switch ( rtl_release ) {
    591     case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    592     case CACHE_L2C_310_RTL_RELEASE_R3_P2:
    593     case CACHE_L2C_310_RTL_RELEASE_R2_P0:
    594     case CACHE_L2C_310_RTL_RELEASE_R1_P0:
    595     case CACHE_L2C_310_RTL_RELEASE_R0_P0:
     591    case L2C_310_RTL_RELEASE_R3_P3:
     592    case L2C_310_RTL_RELEASE_R3_P2:
     593    case L2C_310_RTL_RELEASE_R2_P0:
     594    case L2C_310_RTL_RELEASE_R1_P0:
     595    case L2C_310_RTL_RELEASE_R0_P0:
    596596      is_applicable = false;
    597597      break;
    598     case CACHE_L2C_310_RTL_RELEASE_R3_P1:
    599     case CACHE_L2C_310_RTL_RELEASE_R3_P0:
     598    case L2C_310_RTL_RELEASE_R3_P1:
     599    case L2C_310_RTL_RELEASE_R3_P0:
    600600      is_applicable = true;
    601601      break;
     
    615615
    616616  switch ( rtl_release ) {
    617     case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    618     case CACHE_L2C_310_RTL_RELEASE_R1_P0:
    619     case CACHE_L2C_310_RTL_RELEASE_R0_P0:
     617    case L2C_310_RTL_RELEASE_R3_P3:
     618    case L2C_310_RTL_RELEASE_R1_P0:
     619    case L2C_310_RTL_RELEASE_R0_P0:
    620620      is_applicable = false;
    621621      break;
    622     case CACHE_L2C_310_RTL_RELEASE_R3_P2:
    623     case CACHE_L2C_310_RTL_RELEASE_R3_P1:
    624     case CACHE_L2C_310_RTL_RELEASE_R3_P0:
    625     case CACHE_L2C_310_RTL_RELEASE_R2_P0:
     622    case L2C_310_RTL_RELEASE_R3_P2:
     623    case L2C_310_RTL_RELEASE_R3_P1:
     624    case L2C_310_RTL_RELEASE_R3_P0:
     625    case L2C_310_RTL_RELEASE_R2_P0:
    626626      is_applicable = true;
    627627      break;
     
    641641
    642642  switch ( rtl_release ) {
    643     case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    644     case CACHE_L2C_310_RTL_RELEASE_R3_P2:
    645     case CACHE_L2C_310_RTL_RELEASE_R3_P0:
    646     case CACHE_L2C_310_RTL_RELEASE_R2_P0:
    647     case CACHE_L2C_310_RTL_RELEASE_R1_P0:
    648     case CACHE_L2C_310_RTL_RELEASE_R0_P0:
     643    case L2C_310_RTL_RELEASE_R3_P3:
     644    case L2C_310_RTL_RELEASE_R3_P2:
     645    case L2C_310_RTL_RELEASE_R3_P0:
     646    case L2C_310_RTL_RELEASE_R2_P0:
     647    case L2C_310_RTL_RELEASE_R1_P0:
     648    case L2C_310_RTL_RELEASE_R0_P0:
    649649      is_applicable = false;
    650650      break;
    651     case CACHE_L2C_310_RTL_RELEASE_R3_P1:
     651    case L2C_310_RTL_RELEASE_R3_P1:
    652652      is_applicable = true;
    653653      break;
     
    667667
    668668  switch ( rtl_release ) {
    669     case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    670     case CACHE_L2C_310_RTL_RELEASE_R3_P2:
    671     case CACHE_L2C_310_RTL_RELEASE_R2_P0:
    672     case CACHE_L2C_310_RTL_RELEASE_R1_P0:
    673     case CACHE_L2C_310_RTL_RELEASE_R0_P0:
     669    case L2C_310_RTL_RELEASE_R3_P3:
     670    case L2C_310_RTL_RELEASE_R3_P2:
     671    case L2C_310_RTL_RELEASE_R2_P0:
     672    case L2C_310_RTL_RELEASE_R1_P0:
     673    case L2C_310_RTL_RELEASE_R0_P0:
    674674      is_applicable = false;
    675675      break;
    676     case CACHE_L2C_310_RTL_RELEASE_R3_P1:
    677     case CACHE_L2C_310_RTL_RELEASE_R3_P0:
     676    case L2C_310_RTL_RELEASE_R3_P1:
     677    case L2C_310_RTL_RELEASE_R3_P0:
    678678      is_applicable = true;
    679679      break;
     
    693693
    694694  switch ( rtl_release ) {
    695     case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    696     case CACHE_L2C_310_RTL_RELEASE_R3_P2:
    697     case CACHE_L2C_310_RTL_RELEASE_R3_P1:
    698     case CACHE_L2C_310_RTL_RELEASE_R3_P0:
    699     case CACHE_L2C_310_RTL_RELEASE_R2_P0:
    700     case CACHE_L2C_310_RTL_RELEASE_R1_P0:
    701     case CACHE_L2C_310_RTL_RELEASE_R0_P0:
     695    case L2C_310_RTL_RELEASE_R3_P3:
     696    case L2C_310_RTL_RELEASE_R3_P2:
     697    case L2C_310_RTL_RELEASE_R3_P1:
     698    case L2C_310_RTL_RELEASE_R3_P0:
     699    case L2C_310_RTL_RELEASE_R2_P0:
     700    case L2C_310_RTL_RELEASE_R1_P0:
     701    case L2C_310_RTL_RELEASE_R0_P0:
    702702      is_applicable = true;
    703703      break;
     
    717717
    718718  switch ( rtl_release ) {
    719     case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    720     case CACHE_L2C_310_RTL_RELEASE_R3_P2:
     719    case L2C_310_RTL_RELEASE_R3_P3:
     720    case L2C_310_RTL_RELEASE_R3_P2:
    721721      is_applicable = false;
    722722      break;
    723     case CACHE_L2C_310_RTL_RELEASE_R3_P1:
    724     case CACHE_L2C_310_RTL_RELEASE_R3_P0:
    725     case CACHE_L2C_310_RTL_RELEASE_R2_P0:
    726     case CACHE_L2C_310_RTL_RELEASE_R1_P0:
    727     case CACHE_L2C_310_RTL_RELEASE_R0_P0:
     723    case L2C_310_RTL_RELEASE_R3_P1:
     724    case L2C_310_RTL_RELEASE_R3_P0:
     725    case L2C_310_RTL_RELEASE_R2_P0:
     726    case L2C_310_RTL_RELEASE_R1_P0:
     727    case L2C_310_RTL_RELEASE_R0_P0:
    728728      is_applicable = true;
    729729      break;
     
    743743
    744744  switch ( rtl_release ) {
    745     case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    746     case CACHE_L2C_310_RTL_RELEASE_R3_P2:
    747     case CACHE_L2C_310_RTL_RELEASE_R3_P1:
    748     case CACHE_L2C_310_RTL_RELEASE_R3_P0:
    749     case CACHE_L2C_310_RTL_RELEASE_R2_P0:
     745    case L2C_310_RTL_RELEASE_R3_P3:
     746    case L2C_310_RTL_RELEASE_R3_P2:
     747    case L2C_310_RTL_RELEASE_R3_P1:
     748    case L2C_310_RTL_RELEASE_R3_P0:
     749    case L2C_310_RTL_RELEASE_R2_P0:
    750750      is_applicable = false;
    751751      break;
    752     case CACHE_L2C_310_RTL_RELEASE_R1_P0:
    753     case CACHE_L2C_310_RTL_RELEASE_R0_P0:
     752    case L2C_310_RTL_RELEASE_R1_P0:
     753    case L2C_310_RTL_RELEASE_R0_P0:
    754754      is_applicable = true;
    755755      break;
     
    770770
    771771  switch ( rtl_release ) {
    772     case CACHE_L2C_310_RTL_RELEASE_R3_P3:
    773     case CACHE_L2C_310_RTL_RELEASE_R3_P2:
    774     case CACHE_L2C_310_RTL_RELEASE_R3_P1:
    775     case CACHE_L2C_310_RTL_RELEASE_R3_P0:
    776     case CACHE_L2C_310_RTL_RELEASE_R2_P0:
    777     case CACHE_L2C_310_RTL_RELEASE_R1_P0:
    778     case CACHE_L2C_310_RTL_RELEASE_R0_P0:
     772    case L2C_310_RTL_RELEASE_R3_P3:
     773    case L2C_310_RTL_RELEASE_R3_P2:
     774    case L2C_310_RTL_RELEASE_R3_P1:
     775    case L2C_310_RTL_RELEASE_R3_P0:
     776    case L2C_310_RTL_RELEASE_R2_P0:
     777    case L2C_310_RTL_RELEASE_R1_P0:
     778    case L2C_310_RTL_RELEASE_R0_P0:
    779779      is_applicable = true;
    780780    break;
     
    825825    volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    826826
    827     assert( 0 == ( l2cc->aux_ctrl & CACHE_L2C_310_L2CC_AUX_HPSODRE_MASK ) );
     827    assert( 0 == ( l2cc->aux_ctrl & L2C_310_AUX_HPSODRE_MASK ) );
    828828
    829829    /* Erratum: 729815 The “High Priority for SO and Dev reads” feature can
     
    861861    volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    862862
    863     assert( !( ( l2cc->aux_ctrl & CACHE_L2C_310_L2CC_AUX_IPFE_MASK
    864                  || l2cc->aux_ctrl & CACHE_L2C_310_L2CC_AUX_DPFE_MASK )
    865                && ( ( l2cc->prefetch_ctrl & CACHE_L2C_310_L2CC_PREFETCH_OFFSET_MASK )
     863    assert( !( ( l2cc->aux_ctrl & L2C_310_AUX_IPFE_MASK
     864                 || l2cc->aux_ctrl & L2C_310_AUX_DPFE_MASK )
     865               && ( ( l2cc->prefetch_ctrl & L2C_310_PREFETCH_OFFSET_MASK )
    866866                    == 23 ) ) );
    867867
     
    889889  volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    890890  cache_l2c_310_rtl_release rtl_release =
    891     l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
     891    l2cc->cache_id & L2C_310_ID_RTL_MASK;
    892892
    893893  if( l2c_310_cache_errata_is_applicable_753970( rtl_release ) ) {
     
    927927  /* Back starting address up to start of a line and invalidate until ADDR_LAST */
    928928  uint32_t       adx               = (uint32_t)d_addr
    929     & ~CACHE_L2C_310_DATA_LINE_MASK;
     929    & ~L2C_310_DATA_LINE_MASK;
    930930  const uint32_t ADDR_LAST         =
    931931    (uint32_t)( (size_t)d_addr + n_bytes - 1 );
    932932  uint32_t       block_end         =
    933     CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES );
     933    L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES );
    934934  volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE;
    935935  cache_l2c_310_rtl_release rtl_release =
    936     l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
     936    l2cc->cache_id & L2C_310_ID_RTL_MASK;
    937937  bool is_errata_588369_applicable =
    938938    l2c_310_cache_errata_is_applicable_588369( rtl_release );
     
    943943       adx      <= ADDR_LAST;
    944944       adx       = block_end + 1,
    945        block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES )) {
     945       block_end = L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES )) {
    946946    for (; adx <= block_end; adx += CPU_DATA_CACHE_ALIGNMENT ) {
    947947      cache_l2c_310_flush_1_line( (void*)adx, is_errata_588369_applicable );
     
    963963
    964964  /* Only flush if level 2 cache is active */
    965   if( ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) != 0 ) {
     965  if( ( l2cc->ctrl & L2C_310_ENABLE_MASK ) != 0 ) {
    966966
    967967    /* ensure ordering with previous memory accesses */
     
    969969
    970970    rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
    971     l2cc->clean_inv_way = CACHE_l2C_310_WAY_MASK;
    972 
    973     while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) {};
     971    l2cc->clean_inv_way = L2C_310_WAY_MASK;
     972
     973    while ( l2cc->clean_inv_way & L2C_310_WAY_MASK ) {};
    974974
    975975    /* Wait for the flush to complete */
     
    10171017  _ARM_Data_memory_barrier();
    10181018
    1019   l2cc->inv_way = CACHE_l2C_310_WAY_MASK;
    1020 
    1021   while ( l2cc->inv_way & CACHE_l2C_310_WAY_MASK ) ;
     1019  l2cc->inv_way = L2C_310_WAY_MASK;
     1020
     1021  while ( l2cc->inv_way & L2C_310_WAY_MASK ) ;
    10221022
    10231023  /* Wait for the invalidate to complete */
     
    10311031  rtems_interrupt_lock_context lock_context;
    10321032
    1033   if( ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) != 0 ) {
     1033  if( ( l2cc->ctrl & L2C_310_ENABLE_MASK ) != 0 ) {
    10341034    /* Invalidate the caches */
    10351035
     
    10381038
    10391039    rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
    1040     l2cc->clean_inv_way = CACHE_l2C_310_WAY_MASK;
    1041 
    1042     while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) ;
     1040    l2cc->clean_inv_way = L2C_310_WAY_MASK;
     1041
     1042    while ( l2cc->clean_inv_way & L2C_310_WAY_MASK ) ;
    10431043
    10441044    /* Wait for the invalidate to complete */
     
    10721072  uint32_t       num_ways;
    10731073
    1074   way_size = (cache_type & CACHE_L2C_310_L2CC_TYPE_SIZE_D_WAYS_MASK)
    1075     >> CACHE_L2C_310_L2CC_TYPE_SIZE_D_WAYS_SHIFT;
    1076   num_ways = (cache_type & CACHE_L2C_310_L2CC_TYPE_NUM_D_WAYS_MASK)
    1077     >> CACHE_L2C_310_L2CC_TYPE_NUM_D_WAYS_SHIFT;
     1074  way_size = (cache_type & L2C_310_TYPE_SIZE_D_WAYS_MASK)
     1075    >> L2C_310_TYPE_SIZE_D_WAYS_SHIFT;
     1076  num_ways = (cache_type & L2C_310_TYPE_NUM_D_WAYS_MASK)
     1077    >> L2C_310_TYPE_NUM_D_WAYS_SHIFT;
    10781078
    10791079  assert( way_size <= 0x07 );
     
    11251125static void cache_l2c_310_wait_for_background_ops( volatile L2CC *l2cc )
    11261126{
    1127   while ( l2cc->inv_way & CACHE_l2C_310_WAY_MASK ) ;
    1128 
    1129   while ( l2cc->clean_way & CACHE_l2C_310_WAY_MASK ) ;
    1130 
    1131   while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) ;
     1127  while ( l2cc->inv_way & L2C_310_WAY_MASK ) ;
     1128
     1129  while ( l2cc->clean_way & L2C_310_WAY_MASK ) ;
     1130
     1131  while ( l2cc->clean_inv_way & L2C_310_WAY_MASK ) ;
    11321132}
    11331133
    11341134/* We support only the L2C-310 revisions r3p2 and r3p3 cache controller */
    11351135
    1136 #if (BSP_ARM_L2C_310_ID & CACHE_L2C_310_L2CC_ID_PART_MASK) \
    1137   != CACHE_L2C_310_L2CC_ID_PART_L310
     1136#if (BSP_ARM_L2C_310_ID & L2C_310_ID_PART_MASK) \
     1137  != L2C_310_ID_PART_L310
    11381138#error "invalid L2-310 cache controller part number"
    11391139#endif
    11401140
    1141 #if ((BSP_ARM_L2C_310_ID & CACHE_L2C_310_L2CC_ID_RTL_MASK) != 0x8) \
    1142   && ((BSP_ARM_L2C_310_ID & CACHE_L2C_310_L2CC_ID_RTL_MASK) != 0x9)
     1141#if ((BSP_ARM_L2C_310_ID & L2C_310_ID_RTL_MASK) != 0x8) \
     1142  && ((BSP_ARM_L2C_310_ID & L2C_310_ID_RTL_MASK) != 0x9)
    11431143#error "invalid L2-310 cache controller RTL revision"
    11441144#endif
     
    11501150  uint32_t cache_id = l2cc->cache_id;
    11511151  cache_l2c_310_rtl_release rtl_release =
    1152     cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
     1152    cache_id & L2C_310_ID_RTL_MASK;
    11531153  uint32_t id_mask =
    1154     CACHE_L2C_310_L2CC_ID_IMPL_MASK | CACHE_L2C_310_L2CC_ID_PART_MASK;
     1154    L2C_310_ID_IMPL_MASK | L2C_310_ID_PART_MASK;
    11551155
    11561156  /*
     
    11601160  if (
    11611161    (BSP_ARM_L2C_310_ID & id_mask) != (cache_id & id_mask)
    1162       || rtl_release < (BSP_ARM_L2C_310_ID & CACHE_L2C_310_L2CC_ID_RTL_MASK)
     1162      || rtl_release < (BSP_ARM_L2C_310_ID & L2C_310_ID_RTL_MASK)
    11631163  ) {
    11641164    bsp_fatal( ARM_FATAL_L2C_310_UNEXPECTED_ID );
     
    11681168
    11691169  /* Only enable if L2CC is currently disabled */
    1170   if( ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) == 0 ) {
     1170  if( ( l2cc->ctrl & L2C_310_ENABLE_MASK ) == 0 ) {
    11711171    uint32_t aux_ctrl;
    11721172    int ways;
     
    11851185    }
    11861186
    1187     if ( ways != CACHE_l2C_310_NUM_WAYS ) {
     1187    if ( ways != L2C_310_NUM_WAYS ) {
    11881188      bsp_fatal( ARM_FATAL_L2C_310_UNEXPECTED_NUM_WAYS );
    11891189    }
    11901190
    11911191    /* Set up the way size */
    1192     aux_ctrl &= CACHE_L2C_310_L2CC_AUX_REG_ZERO_MASK; /* Set way_size to 0 */
    1193     aux_ctrl |= CACHE_L2C_310_L2CC_AUX_REG_DEFAULT_MASK;
     1192    aux_ctrl &= L2C_310_AUX_REG_ZERO_MASK; /* Set way_size to 0 */
     1193    aux_ctrl |= L2C_310_AUX_REG_DEFAULT_MASK;
    11941194
    11951195    l2cc->aux_ctrl = aux_ctrl;
    11961196
    11971197    /* Set up the latencies */
    1198     l2cc->tag_ram_ctrl  = CACHE_L2C_310_L2CC_TAG_RAM_DEFAULT_LAT;
    1199     l2cc->data_ram_ctrl = CACHE_L2C_310_L2CC_DATA_RAM_DEFAULT_MASK;
     1198    l2cc->tag_ram_ctrl  = L2C_310_TAG_RAM_DEFAULT_LAT;
     1199    l2cc->data_ram_ctrl = L2C_310_DATA_RAM_DEFAULT_MASK;
    12001200
    12011201    cache_l2c_310_invalidate_entire();
     
    12051205
    12061206    /* Enable the L2CC */
    1207     l2cc->ctrl |= CACHE_L2C_310_L2CC_ENABLE_MASK;
     1207    l2cc->ctrl |= L2C_310_ENABLE_MASK;
    12081208  }
    12091209}
     
    12151215  rtems_interrupt_lock_context lock_context;
    12161216
    1217   if ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) {
     1217  if ( l2cc->ctrl & L2C_310_ENABLE_MASK ) {
    12181218    /* Clean and Invalidate L2 Cache */
    12191219    cache_l2c_310_flush_entire();
     
    12231223
    12241224    /* Disable the L2 cache */
    1225     l2cc->ctrl &= ~CACHE_L2C_310_L2CC_ENABLE_MASK;
     1225    l2cc->ctrl &= ~L2C_310_ENABLE_MASK;
    12261226    rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context );
    12271227  }
     
    12881288    /* Back starting address up to start of a line and invalidate until ADDR_LAST */
    12891289    uint32_t       adx       = (uint32_t) addr_first
    1290       & ~CACHE_L2C_310_DATA_LINE_MASK;
     1290      & ~L2C_310_DATA_LINE_MASK;
    12911291    const uint32_t ADDR_LAST =
    12921292      (uint32_t)( (size_t)addr_first + n_bytes - 1 );
    12931293    uint32_t       block_end =
    1294       CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES );
    1295 
    1296     /* We have to apply a lock. Thus we will operate only CACHE_MAX_LOCKING_BYTES
     1294      L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES );
     1295
     1296    /* We have to apply a lock. Thus we will operate only L2C_310_MAX_LOCKING_BYTES
    12971297     * at a time */
    12981298    for (;
    12991299         adx      <= ADDR_LAST;
    13001300         adx       = block_end + 1,
    1301          block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES )) {
     1301         block_end = L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES )) {
    13021302      cache_l2c_310_invalidate_range(
    13031303        adx,
     
    13101310    );
    13111311
    1312     adx       = (uint32_t)addr_first & ~CACHE_L2C_310_DATA_LINE_MASK;
    1313     block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES );
     1312    adx       = (uint32_t)addr_first & ~L2C_310_DATA_LINE_MASK;
     1313    block_end = L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES );
    13141314    for (;
    13151315         adx      <= ADDR_LAST;
    13161316         adx       = block_end + 1,
    1317          block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES )) {
     1317         block_end = L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES )) {
    13181318      cache_l2c_310_invalidate_range(
    13191319        adx,
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