Changeset 861d315 in rtems
- Timestamp:
- 11/19/14 13:05:36 (9 years ago)
- Branches:
- 4.11, 5, master
- Children:
- d53de34
- Parents:
- f2fed0c1
- git-author:
- Sebastian Huber <sebastian.huber@…> (11/19/14 13:05:36)
- git-committer:
- Sebastian Huber <sebastian.huber@…> (11/20/14 09:30:27)
- File:
-
- 1 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h
rf2fed0c1 r861d315 77 77 #define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS 78 78 79 #define CACHE_L2C_310_DATA_LINE_MASK ( CPU_DATA_CACHE_ALIGNMENT - 1 )80 #define CACHE_L2C_310_INSTRUCTION_LINE_MASK \79 #define L2C_310_DATA_LINE_MASK ( CPU_DATA_CACHE_ALIGNMENT - 1 ) 80 #define L2C_310_INSTRUCTION_LINE_MASK \ 81 81 ( CPU_INSTRUCTION_CACHE_ALIGNMENT \ 82 82 - 1 ) 83 #define CACHE_l2C_310_NUM_WAYS 884 #define CACHE_l2C_310_WAY_MASK ( ( 1 << CACHE_l2C_310_NUM_WAYS ) - 1 )85 86 #define CACHE_MIN( a, b ) \83 #define L2C_310_NUM_WAYS 8 84 #define L2C_310_WAY_MASK ( ( 1 << L2C_310_NUM_WAYS ) - 1 ) 85 86 #define L2C_310_MIN( a, b ) \ 87 87 ((a < b) ? (a) : (b)) 88 88 89 #define CACHE_MAX_LOCKING_BYTES (4 * 1024)89 #define L2C_310_MAX_LOCKING_BYTES (4 * 1024) 90 90 91 91 92 92 /* RTL release number as can be read from cache_id register */ 93 93 typedef enum { 94 CACHE_L2C_310_RTL_RELEASE_R0_P0 = 0x0,95 CACHE_L2C_310_RTL_RELEASE_R1_P0 = 0x2,96 CACHE_L2C_310_RTL_RELEASE_R2_P0 = 0x4,97 CACHE_L2C_310_RTL_RELEASE_R3_P0 = 0x5,98 CACHE_L2C_310_RTL_RELEASE_R3_P1 = 0x6,99 CACHE_L2C_310_RTL_RELEASE_R3_P2 = 0x8,100 CACHE_L2C_310_RTL_RELEASE_R3_P3 = 0x994 L2C_310_RTL_RELEASE_R0_P0 = 0x0, 95 L2C_310_RTL_RELEASE_R1_P0 = 0x2, 96 L2C_310_RTL_RELEASE_R2_P0 = 0x4, 97 L2C_310_RTL_RELEASE_R3_P0 = 0x5, 98 L2C_310_RTL_RELEASE_R3_P1 = 0x6, 99 L2C_310_RTL_RELEASE_R3_P2 = 0x8, 100 L2C_310_RTL_RELEASE_R3_P3 = 0x9 101 101 } cache_l2c_310_rtl_release; 102 102 … … 115 115 /** @brief Cache ID */ 116 116 uint32_t cache_id; 117 #define CACHE_L2C_310_L2CC_ID_RTL_MASK 0x3f118 #define CACHE_L2C_310_L2CC_ID_PART_MASK ( 0xf << 6 )119 #define CACHE_L2C_310_L2CC_ID_PART_L210 ( 1 << 6 )120 #define CACHE_L2C_310_L2CC_ID_PART_L310 ( 3 << 6 )121 #define CACHE_L2C_310_L2CC_ID_IMPL_MASK ( 0xff << 24 )117 #define L2C_310_ID_RTL_MASK 0x3f 118 #define L2C_310_ID_PART_MASK ( 0xf << 6 ) 119 #define L2C_310_ID_PART_L210 ( 1 << 6 ) 120 #define L2C_310_ID_PART_L310 ( 3 << 6 ) 121 #define L2C_310_ID_IMPL_MASK ( 0xff << 24 ) 122 122 /** @brief Cache type */ 123 123 uint32_t cache_type; 124 124 /** @brief 1 if data banking implemented, 0 if not */ 125 #define CACHE_L2C_310_L2CC_TYPE_DATA_BANKING_MASK 0x80000000125 #define L2C_310_TYPE_DATA_BANKING_MASK 0x80000000 126 126 /** @brief 11xy, where: x=1 if pl310_LOCKDOWN_BY_MASTER is defined, otherwise 0 */ 127 #define CACHE_L2C_310_L2CC_TYPE_CTYPE_MASK 0x1E000000127 #define L2C_310_TYPE_CTYPE_MASK 0x1E000000 128 128 /** @brief y=1 if pl310_LOCKDOWN_BY_LINE is defined, otherwise 0. */ 129 #define CACHE_L2C_310_L2CC_TYPE_CTYPE_SHIFT 25129 #define L2C_310_TYPE_CTYPE_SHIFT 25 130 130 /** @brief 1 for Harvard architecture, 0 for unified architecture */ 131 #define CACHE_L2C_310_L2CC_TYPE_HARVARD_MASK 0x01000000131 #define L2C_310_TYPE_HARVARD_MASK 0x01000000 132 132 /** @brief Data cache way size = 2 Exp(value + 2) KB */ 133 #define CACHE_L2C_310_L2CC_TYPE_SIZE_D_WAYS_MASK 0x00700000134 #define CACHE_L2C_310_L2CC_TYPE_SIZE_D_WAYS_SHIFT 20133 #define L2C_310_TYPE_SIZE_D_WAYS_MASK 0x00700000 134 #define L2C_310_TYPE_SIZE_D_WAYS_SHIFT 20 135 135 /** @brief Assoziativity aka number of data ways = (value * 8) + 8 */ 136 #define CACHE_L2C_310_L2CC_TYPE_NUM_D_WAYS_MASK 0x00040000137 #define CACHE_L2C_310_L2CC_TYPE_NUM_D_WAYS_SHIFT 18136 #define L2C_310_TYPE_NUM_D_WAYS_MASK 0x00040000 137 #define L2C_310_TYPE_NUM_D_WAYS_SHIFT 18 138 138 /** @brief Data cache line length 00 - 32 */ 139 #define CACHE_L2C_310_L2CC_TYPE_LENGTH_D_LINE_MASK 0x00003000140 #define CACHE_L2C_310_L2CC_TYPE_LENGTH_D_LINE_SHIFT 12141 #define CACHE_L2C_310_L2CC_TYPE_LENGTH_D_LINE_VAL_32 0x0139 #define L2C_310_TYPE_LENGTH_D_LINE_MASK 0x00003000 140 #define L2C_310_TYPE_LENGTH_D_LINE_SHIFT 12 141 #define L2C_310_TYPE_LENGTH_D_LINE_VAL_32 0x0 142 142 /** @brief Instruction cache way size = 2 Exp(value + 2) KB */ 143 #define CACHE_L2C_310_L2CC_TYPE_SIZE_I_WAYS_MASK 0x00000700144 #define CACHE_L2C_310_L2CC_TYPE_SIZE_I_WAYS_SHIFT 8143 #define L2C_310_TYPE_SIZE_I_WAYS_MASK 0x00000700 144 #define L2C_310_TYPE_SIZE_I_WAYS_SHIFT 8 145 145 /** @brief Assoziativity aka number of instruction ways = (value * 8) + 8 */ 146 #define CACHE_L2C_310_L2CC_TYPE_NUM_I_WAYS_MASK 0x00000040147 #define CACHE_L2C_310_L2CC_TYPE_NUM_I_WAYS_SHIFT 6146 #define L2C_310_TYPE_NUM_I_WAYS_MASK 0x00000040 147 #define L2C_310_TYPE_NUM_I_WAYS_SHIFT 6 148 148 /** @brief Instruction cache line length 00 - 32 */ 149 #define CACHE_L2C_310_L2CC_TYPE_LENGTH_I_LINE_MASK 0x00000003150 #define CACHE_L2C_310_L2CC_TYPE_LENGTH_I_LINE_SHIFT 0151 #define CACHE_L2C_310_L2CC_TYPE_LENGTH_I_LINE_VAL_32 0x0149 #define L2C_310_TYPE_LENGTH_I_LINE_MASK 0x00000003 150 #define L2C_310_TYPE_LENGTH_I_LINE_SHIFT 0 151 #define L2C_310_TYPE_LENGTH_I_LINE_VAL_32 0x0 152 152 153 153 uint8_t reserved_8[0x100 - 8]; 154 154 uint32_t ctrl; /* Control */ 155 155 /** @brief Enables the L2CC */ 156 #define CACHE_L2C_310_L2CC_ENABLE_MASK 0x00000001156 #define L2C_310_ENABLE_MASK 0x00000001 157 157 158 158 /** @brief Auxiliary control */ … … 160 160 161 161 /** @brief Early BRESP Enable */ 162 #define CACHE_L2C_310_L2CC_AUX_EBRESPE_MASK 0x40000000162 #define L2C_310_AUX_EBRESPE_MASK 0x40000000 163 163 164 164 /** @brief Instruction Prefetch Enable */ 165 #define CACHE_L2C_310_L2CC_AUX_IPFE_MASK 0x20000000165 #define L2C_310_AUX_IPFE_MASK 0x20000000 166 166 167 167 /** @brief Data Prefetch Enable */ 168 #define CACHE_L2C_310_L2CC_AUX_DPFE_MASK 0x10000000168 #define L2C_310_AUX_DPFE_MASK 0x10000000 169 169 170 170 /** @brief Non-secure interrupt access control */ 171 #define CACHE_L2C_310_L2CC_AUX_NSIC_MASK 0x08000000171 #define L2C_310_AUX_NSIC_MASK 0x08000000 172 172 173 173 /** @brief Non-secure lockdown enable */ 174 #define CACHE_L2C_310_L2CC_AUX_NSLE_MASK 0x04000000174 #define L2C_310_AUX_NSLE_MASK 0x04000000 175 175 176 176 /** @brief Cache replacement policy */ 177 #define CACHE_L2C_310_L2CC_AUX_CRP_MASK 0x02000000177 #define L2C_310_AUX_CRP_MASK 0x02000000 178 178 179 179 /** @brief Force write allocate */ 180 #define CACHE_L2C_310_L2CC_AUX_FWE_MASK 0x01800000180 #define L2C_310_AUX_FWE_MASK 0x01800000 181 181 182 182 /** @brief Shared attribute override enable */ 183 #define CACHE_L2C_310_L2CC_AUX_SAOE_MASK 0x00400000183 #define L2C_310_AUX_SAOE_MASK 0x00400000 184 184 185 185 /** @brief Parity enable */ 186 #define CACHE_L2C_310_L2CC_AUX_PE_MASK 0x00200000186 #define L2C_310_AUX_PE_MASK 0x00200000 187 187 188 188 /** @brief Event monitor bus enable */ 189 #define CACHE_L2C_310_L2CC_AUX_EMBE_MASK 0x00100000189 #define L2C_310_AUX_EMBE_MASK 0x00100000 190 190 191 191 /** @brief Way-size */ 192 #define CACHE_L2C_310_L2CC_AUX_WAY_SIZE_MASK 0x000E0000193 #define CACHE_L2C_310_L2CC_AUX_WAY_SIZE_SHIFT 17192 #define L2C_310_AUX_WAY_SIZE_MASK 0x000E0000 193 #define L2C_310_AUX_WAY_SIZE_SHIFT 17 194 194 195 195 /** @brief Way-size */ 196 #define CACHE_L2C_310_L2CC_AUX_ASSOC_MASK 0x00010000196 #define L2C_310_AUX_ASSOC_MASK 0x00010000 197 197 198 198 /** @brief Shared attribute invalidate enable */ 199 #define CACHE_L2C_310_L2CC_AUX_SAIE_MASK 0x00002000199 #define L2C_310_AUX_SAIE_MASK 0x00002000 200 200 201 201 /** @brief Exclusive cache configuration */ 202 #define CACHE_L2C_310_L2CC_AUX_EXCL_CACHE_MASK 0x00001000202 #define L2C_310_AUX_EXCL_CACHE_MASK 0x00001000 203 203 204 204 /** @brief Store buffer device limitation Enable */ 205 #define CACHE_L2C_310_L2CC_AUX_SBDLE_MASK 0x00000800205 #define L2C_310_AUX_SBDLE_MASK 0x00000800 206 206 207 207 /** @brief High Priority for SO and Dev Reads Enable */ 208 #define CACHE_L2C_310_L2CC_AUX_HPSODRE_MASK 0x00000400208 #define L2C_310_AUX_HPSODRE_MASK 0x00000400 209 209 210 210 /** @brief Full line of zero enable */ 211 #define CACHE_L2C_310_L2CC_AUX_FLZE_MASK 0x00000001211 #define L2C_310_AUX_FLZE_MASK 0x00000001 212 212 213 213 /** @brief Enable all prefetching, */ 214 #define CACHE_L2C_310_L2CC_AUX_REG_DEFAULT_MASK \215 ( CACHE_L2C_310_L2CC_AUX_WAY_SIZE_MASK & ( 0x3 << CACHE_L2C_310_L2CC_AUX_WAY_SIZE_SHIFT ) ) \216 | CACHE_L2C_310_L2CC_AUX_PE_MASK /* Prefetch enable */ \217 | CACHE_L2C_310_L2CC_AUX_SAOE_MASK /* Shared attribute override enable */ \218 | CACHE_L2C_310_L2CC_AUX_CRP_MASK /* Cache replacement policy */ \219 | CACHE_L2C_310_L2CC_AUX_DPFE_MASK /* Data prefetch enable */ \220 | CACHE_L2C_310_L2CC_AUX_IPFE_MASK /* Instruction prefetch enable */ \221 | CACHE_L2C_310_L2CC_AUX_EBRESPE_MASK /* Early BRESP enable */222 223 #define CACHE_L2C_310_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFF214 #define L2C_310_AUX_REG_DEFAULT_MASK \ 215 ( L2C_310_AUX_WAY_SIZE_MASK & ( 0x3 << L2C_310_AUX_WAY_SIZE_SHIFT ) ) \ 216 | L2C_310_AUX_PE_MASK /* Prefetch enable */ \ 217 | L2C_310_AUX_SAOE_MASK /* Shared attribute override enable */ \ 218 | L2C_310_AUX_CRP_MASK /* Cache replacement policy */ \ 219 | L2C_310_AUX_DPFE_MASK /* Data prefetch enable */ \ 220 | L2C_310_AUX_IPFE_MASK /* Instruction prefetch enable */ \ 221 | L2C_310_AUX_EBRESPE_MASK /* Early BRESP enable */ 222 223 #define L2C_310_AUX_REG_ZERO_MASK 0xFFF1FFFF 224 224 225 225 /** @brief 1 cycle of latency, there is no additional latency fot tag RAM */ 226 #define CACHE_L2C_310_L2CC_RAM_1_CYCLE_LAT_VAL 0x00000000226 #define L2C_310_RAM_1_CYCLE_LAT_VAL 0x00000000 227 227 /** @brief 2 cycles of latency for tag RAM */ 228 #define CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL 0x00000001228 #define L2C_310_RAM_2_CYCLE_LAT_VAL 0x00000001 229 229 /** @brief 3 cycles of latency for tag RAM */ 230 #define CACHE_L2C_310_L2CC_RAM_3_CYCLE_LAT_VAL 0x00000002230 #define L2C_310_RAM_3_CYCLE_LAT_VAL 0x00000002 231 231 /** @brief 4 cycles of latency for tag RAM */ 232 #define CACHE_L2C_310_L2CC_RAM_4_CYCLE_LAT_VAL 0x00000003232 #define L2C_310_RAM_4_CYCLE_LAT_VAL 0x00000003 233 233 /** @brief 5 cycles of latency for tag RAM */ 234 #define CACHE_L2C_310_L2CC_RAM_5_CYCLE_LAT_VAL 0x00000004234 #define L2C_310_RAM_5_CYCLE_LAT_VAL 0x00000004 235 235 /** @brief 6 cycles of latency for tag RAM */ 236 #define CACHE_L2C_310_L2CC_RAM_6_CYCLE_LAT_VAL 0x00000005236 #define L2C_310_RAM_6_CYCLE_LAT_VAL 0x00000005 237 237 /** @brief 7 cycles of latency for tag RAM */ 238 #define CACHE_L2C_310_L2CC_RAM_7_CYCLE_LAT_VAL 0x00000006238 #define L2C_310_RAM_7_CYCLE_LAT_VAL 0x00000006 239 239 /** @brief 8 cycles of latency for tag RAM */ 240 #define CACHE_L2C_310_L2CC_RAM_8_CYCLE_LAT_VAL 0x00000007240 #define L2C_310_RAM_8_CYCLE_LAT_VAL 0x00000007 241 241 /** @brief Shift left setup latency values by this value */ 242 #define CACHE_L2C_310_L2CC_RAM_SETUP_SHIFT 0x00000000242 #define L2C_310_RAM_SETUP_SHIFT 0x00000000 243 243 /** @brief Shift left read latency values by this value */ 244 #define CACHE_L2C_310_L2CC_RAM_READ_SHIFT 0x00000004244 #define L2C_310_RAM_READ_SHIFT 0x00000004 245 245 /** @brief Shift left write latency values by this value */ 246 #define CACHE_L2C_310_L2CC_RAM_WRITE_SHIFT 0x00000008246 #define L2C_310_RAM_WRITE_SHIFT 0x00000008 247 247 /** @brief Mask for RAM setup latency */ 248 #define CACHE_L2C_310_L2CC_RAM_SETUP_LAT_MASK 0x00000007248 #define L2C_310_RAM_SETUP_LAT_MASK 0x00000007 249 249 /** @brief Mask for RAM read latency */ 250 #define CACHE_L2C_310_L2CC_RAM_READ_LAT_MASK 0x00000070250 #define L2C_310_RAM_READ_LAT_MASK 0x00000070 251 251 /** @brief Mask for RAM read latency */ 252 #define CACHE_L2C_310_L2CC_RAM_WRITE_LAT_MASK 0x00000700252 #define L2C_310_RAM_WRITE_LAT_MASK 0x00000700 253 253 /** @brief Latency for tag RAM */ 254 254 uint32_t tag_ram_ctrl; 255 255 /* @brief Latency for tag RAM */ 256 #define CACHE_L2C_310_L2CC_TAG_RAM_DEFAULT_LAT \257 ( ( CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_SETUP_SHIFT ) \258 | ( CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_READ_SHIFT ) \259 | ( CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_WRITE_SHIFT ) )256 #define L2C_310_TAG_RAM_DEFAULT_LAT \ 257 ( ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_SETUP_SHIFT ) \ 258 | ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_READ_SHIFT ) \ 259 | ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_WRITE_SHIFT ) ) 260 260 /** @brief Latency for data RAM */ 261 261 uint32_t data_ram_ctrl; 262 262 /** @brief Latency for data RAM */ 263 #define CACHE_L2C_310_L2CC_DATA_RAM_DEFAULT_MASK \264 ( ( CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_SETUP_SHIFT ) \265 | ( CACHE_L2C_310_L2CC_RAM_3_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_READ_SHIFT ) \266 | ( CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_WRITE_SHIFT ) )263 #define L2C_310_DATA_RAM_DEFAULT_MASK \ 264 ( ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_SETUP_SHIFT ) \ 265 | ( L2C_310_RAM_3_CYCLE_LAT_VAL << L2C_310_RAM_READ_SHIFT ) \ 266 | ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_WRITE_SHIFT ) ) 267 267 268 268 uint8_t reserved_110[0x200 - 0x110]; … … 302 302 303 303 /** @brief DECERR from L3 */ 304 #define CACHE_L2C_310_L2CC_INT_DECERR_MASK 0x00000100304 #define L2C_310_INT_DECERR_MASK 0x00000100 305 305 306 306 /** @brief SLVERR from L3 */ 307 #define CACHE_L2C_310_L2CC_INT_SLVERR_MASK 0x00000080307 #define L2C_310_INT_SLVERR_MASK 0x00000080 308 308 309 309 /** @brief Error on L2 data RAM (Read) */ 310 #define CACHE_L2C_310_L2CC_INT_ERRRD_MASK 0x00000040310 #define L2C_310_INT_ERRRD_MASK 0x00000040 311 311 312 312 /** @brief Error on L2 tag RAM (Read) */ 313 #define CACHE_L2C_310_L2CC_INT_ERRRT_MASK 0x00000020313 #define L2C_310_INT_ERRRT_MASK 0x00000020 314 314 315 315 /** @brief Error on L2 data RAM (Write) */ 316 #define CACHE_L2C_310_L2CC_INT_ERRWD_MASK 0x00000010316 #define L2C_310_INT_ERRWD_MASK 0x00000010 317 317 318 318 /** @brief Error on L2 tag RAM (Write) */ 319 #define CACHE_L2C_310_L2CC_INT_ERRWT_MASK 0x00000008319 #define L2C_310_INT_ERRWT_MASK 0x00000008 320 320 321 321 /** @brief Parity Error on L2 data RAM (Read) */ 322 #define CACHE_L2C_310_L2CC_INT_PARRD_MASK 0x00000004322 #define L2C_310_INT_PARRD_MASK 0x00000004 323 323 324 324 /** @brief Parity Error on L2 tag RAM (Read) */ 325 #define CACHE_L2C_310_L2CC_INT_PARRT_MASK 0x00000002325 #define L2C_310_INT_PARRT_MASK 0x00000002 326 326 327 327 /** @brief Event Counter1/0 Overflow Increment */ 328 #define CACHE_L2C_310_L2CC_INT_ECNTR_MASK 0x00000001328 #define L2C_310_INT_ECNTR_MASK 0x00000001 329 329 330 330 /** @} */ … … 433 433 434 434 /** @brief Address filtering valid bits*/ 435 #define CACHE_L2C_310_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000435 #define L2C_310_ADDR_FILTER_VALID_MASK 0xFFF00000 436 436 437 437 /** @brief Address filtering enable bit*/ 438 #define CACHE_L2C_310_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001438 #define L2C_310_ADDR_FILTER_ENABLE_MASK 0x00000001 439 439 440 440 uint8_t reserved_c08[0xf40 - 0xc08]; … … 444 444 445 445 /** @brief Debug SPIDEN bit */ 446 #define CACHE_L2C_310_L2CC_DEBUG_SPIDEN_MASK 0x00000004446 #define L2C_310_DEBUG_SPIDEN_MASK 0x00000004 447 447 448 448 /** @brief Debug DWB bit, forces write through */ 449 #define CACHE_L2C_310_L2CC_DEBUG_DWB_MASK 0x00000002449 #define L2C_310_DEBUG_DWB_MASK 0x00000002 450 450 451 451 /** @brief Debug DCL bit, disables cache line fill */ 452 #define CACHE_L2C_310_L2CC_DEBUG_DCL_MASK 0x00000002452 #define L2C_310_DEBUG_DCL_MASK 0x00000002 453 453 454 454 uint8_t reserved_f44[0xf60 - 0xf44]; … … 457 457 uint32_t prefetch_ctrl; 458 458 /** @brief Prefetch offset */ 459 #define CACHE_L2C_310_L2CC_PREFETCH_OFFSET_MASK 0x0000001F459 #define L2C_310_PREFETCH_OFFSET_MASK 0x0000001F 460 460 uint8_t reserved_f64[0xf80 - 0xf64]; 461 461 … … 485 485 486 486 switch ( rtl_release ) { 487 case CACHE_L2C_310_RTL_RELEASE_R3_P3:488 case CACHE_L2C_310_RTL_RELEASE_R3_P2:489 case CACHE_L2C_310_RTL_RELEASE_R3_P1:490 case CACHE_L2C_310_RTL_RELEASE_R2_P0:491 case CACHE_L2C_310_RTL_RELEASE_R1_P0:492 case CACHE_L2C_310_RTL_RELEASE_R0_P0:487 case L2C_310_RTL_RELEASE_R3_P3: 488 case L2C_310_RTL_RELEASE_R3_P2: 489 case L2C_310_RTL_RELEASE_R3_P1: 490 case L2C_310_RTL_RELEASE_R2_P0: 491 case L2C_310_RTL_RELEASE_R1_P0: 492 case L2C_310_RTL_RELEASE_R0_P0: 493 493 is_applicable = false; 494 494 break; 495 case CACHE_L2C_310_RTL_RELEASE_R3_P0:495 case L2C_310_RTL_RELEASE_R3_P0: 496 496 is_applicable = true; 497 497 break; … … 511 511 512 512 switch ( rtl_release ) { 513 case CACHE_L2C_310_RTL_RELEASE_R3_P3:514 case CACHE_L2C_310_RTL_RELEASE_R3_P2:515 case CACHE_L2C_310_RTL_RELEASE_R3_P1:516 case CACHE_L2C_310_RTL_RELEASE_R2_P0:517 case CACHE_L2C_310_RTL_RELEASE_R1_P0:518 case CACHE_L2C_310_RTL_RELEASE_R0_P0:513 case L2C_310_RTL_RELEASE_R3_P3: 514 case L2C_310_RTL_RELEASE_R3_P2: 515 case L2C_310_RTL_RELEASE_R3_P1: 516 case L2C_310_RTL_RELEASE_R2_P0: 517 case L2C_310_RTL_RELEASE_R1_P0: 518 case L2C_310_RTL_RELEASE_R0_P0: 519 519 is_applicable = false; 520 520 break; 521 case CACHE_L2C_310_RTL_RELEASE_R3_P0:521 case L2C_310_RTL_RELEASE_R3_P0: 522 522 is_applicable = true; 523 523 break; … … 537 537 538 538 switch ( rtl_release ) { 539 case CACHE_L2C_310_RTL_RELEASE_R3_P3:540 case CACHE_L2C_310_RTL_RELEASE_R3_P2:541 case CACHE_L2C_310_RTL_RELEASE_R3_P1:542 case CACHE_L2C_310_RTL_RELEASE_R2_P0:543 case CACHE_L2C_310_RTL_RELEASE_R1_P0:544 case CACHE_L2C_310_RTL_RELEASE_R0_P0:539 case L2C_310_RTL_RELEASE_R3_P3: 540 case L2C_310_RTL_RELEASE_R3_P2: 541 case L2C_310_RTL_RELEASE_R3_P1: 542 case L2C_310_RTL_RELEASE_R2_P0: 543 case L2C_310_RTL_RELEASE_R1_P0: 544 case L2C_310_RTL_RELEASE_R0_P0: 545 545 is_applicable = false; 546 546 break; 547 case CACHE_L2C_310_RTL_RELEASE_R3_P0:547 case L2C_310_RTL_RELEASE_R3_P0: 548 548 is_applicable = true; 549 549 break; … … 563 563 564 564 switch ( rtl_release ) { 565 case CACHE_L2C_310_RTL_RELEASE_R3_P3:566 case CACHE_L2C_310_RTL_RELEASE_R3_P2:567 case CACHE_L2C_310_RTL_RELEASE_R3_P1:568 case CACHE_L2C_310_RTL_RELEASE_R1_P0:569 case CACHE_L2C_310_RTL_RELEASE_R0_P0:565 case L2C_310_RTL_RELEASE_R3_P3: 566 case L2C_310_RTL_RELEASE_R3_P2: 567 case L2C_310_RTL_RELEASE_R3_P1: 568 case L2C_310_RTL_RELEASE_R1_P0: 569 case L2C_310_RTL_RELEASE_R0_P0: 570 570 is_applicable = false; 571 571 break; 572 case CACHE_L2C_310_RTL_RELEASE_R3_P0:573 case CACHE_L2C_310_RTL_RELEASE_R2_P0:572 case L2C_310_RTL_RELEASE_R3_P0: 573 case L2C_310_RTL_RELEASE_R2_P0: 574 574 is_applicable = true; 575 575 break; … … 589 589 590 590 switch ( rtl_release ) { 591 case CACHE_L2C_310_RTL_RELEASE_R3_P3:592 case CACHE_L2C_310_RTL_RELEASE_R3_P2:593 case CACHE_L2C_310_RTL_RELEASE_R2_P0:594 case CACHE_L2C_310_RTL_RELEASE_R1_P0:595 case CACHE_L2C_310_RTL_RELEASE_R0_P0:591 case L2C_310_RTL_RELEASE_R3_P3: 592 case L2C_310_RTL_RELEASE_R3_P2: 593 case L2C_310_RTL_RELEASE_R2_P0: 594 case L2C_310_RTL_RELEASE_R1_P0: 595 case L2C_310_RTL_RELEASE_R0_P0: 596 596 is_applicable = false; 597 597 break; 598 case CACHE_L2C_310_RTL_RELEASE_R3_P1:599 case CACHE_L2C_310_RTL_RELEASE_R3_P0:598 case L2C_310_RTL_RELEASE_R3_P1: 599 case L2C_310_RTL_RELEASE_R3_P0: 600 600 is_applicable = true; 601 601 break; … … 615 615 616 616 switch ( rtl_release ) { 617 case CACHE_L2C_310_RTL_RELEASE_R3_P3:618 case CACHE_L2C_310_RTL_RELEASE_R1_P0:619 case CACHE_L2C_310_RTL_RELEASE_R0_P0:617 case L2C_310_RTL_RELEASE_R3_P3: 618 case L2C_310_RTL_RELEASE_R1_P0: 619 case L2C_310_RTL_RELEASE_R0_P0: 620 620 is_applicable = false; 621 621 break; 622 case CACHE_L2C_310_RTL_RELEASE_R3_P2:623 case CACHE_L2C_310_RTL_RELEASE_R3_P1:624 case CACHE_L2C_310_RTL_RELEASE_R3_P0:625 case CACHE_L2C_310_RTL_RELEASE_R2_P0:622 case L2C_310_RTL_RELEASE_R3_P2: 623 case L2C_310_RTL_RELEASE_R3_P1: 624 case L2C_310_RTL_RELEASE_R3_P0: 625 case L2C_310_RTL_RELEASE_R2_P0: 626 626 is_applicable = true; 627 627 break; … … 641 641 642 642 switch ( rtl_release ) { 643 case CACHE_L2C_310_RTL_RELEASE_R3_P3:644 case CACHE_L2C_310_RTL_RELEASE_R3_P2:645 case CACHE_L2C_310_RTL_RELEASE_R3_P0:646 case CACHE_L2C_310_RTL_RELEASE_R2_P0:647 case CACHE_L2C_310_RTL_RELEASE_R1_P0:648 case CACHE_L2C_310_RTL_RELEASE_R0_P0:643 case L2C_310_RTL_RELEASE_R3_P3: 644 case L2C_310_RTL_RELEASE_R3_P2: 645 case L2C_310_RTL_RELEASE_R3_P0: 646 case L2C_310_RTL_RELEASE_R2_P0: 647 case L2C_310_RTL_RELEASE_R1_P0: 648 case L2C_310_RTL_RELEASE_R0_P0: 649 649 is_applicable = false; 650 650 break; 651 case CACHE_L2C_310_RTL_RELEASE_R3_P1:651 case L2C_310_RTL_RELEASE_R3_P1: 652 652 is_applicable = true; 653 653 break; … … 667 667 668 668 switch ( rtl_release ) { 669 case CACHE_L2C_310_RTL_RELEASE_R3_P3:670 case CACHE_L2C_310_RTL_RELEASE_R3_P2:671 case CACHE_L2C_310_RTL_RELEASE_R2_P0:672 case CACHE_L2C_310_RTL_RELEASE_R1_P0:673 case CACHE_L2C_310_RTL_RELEASE_R0_P0:669 case L2C_310_RTL_RELEASE_R3_P3: 670 case L2C_310_RTL_RELEASE_R3_P2: 671 case L2C_310_RTL_RELEASE_R2_P0: 672 case L2C_310_RTL_RELEASE_R1_P0: 673 case L2C_310_RTL_RELEASE_R0_P0: 674 674 is_applicable = false; 675 675 break; 676 case CACHE_L2C_310_RTL_RELEASE_R3_P1:677 case CACHE_L2C_310_RTL_RELEASE_R3_P0:676 case L2C_310_RTL_RELEASE_R3_P1: 677 case L2C_310_RTL_RELEASE_R3_P0: 678 678 is_applicable = true; 679 679 break; … … 693 693 694 694 switch ( rtl_release ) { 695 case CACHE_L2C_310_RTL_RELEASE_R3_P3:696 case CACHE_L2C_310_RTL_RELEASE_R3_P2:697 case CACHE_L2C_310_RTL_RELEASE_R3_P1:698 case CACHE_L2C_310_RTL_RELEASE_R3_P0:699 case CACHE_L2C_310_RTL_RELEASE_R2_P0:700 case CACHE_L2C_310_RTL_RELEASE_R1_P0:701 case CACHE_L2C_310_RTL_RELEASE_R0_P0:695 case L2C_310_RTL_RELEASE_R3_P3: 696 case L2C_310_RTL_RELEASE_R3_P2: 697 case L2C_310_RTL_RELEASE_R3_P1: 698 case L2C_310_RTL_RELEASE_R3_P0: 699 case L2C_310_RTL_RELEASE_R2_P0: 700 case L2C_310_RTL_RELEASE_R1_P0: 701 case L2C_310_RTL_RELEASE_R0_P0: 702 702 is_applicable = true; 703 703 break; … … 717 717 718 718 switch ( rtl_release ) { 719 case CACHE_L2C_310_RTL_RELEASE_R3_P3:720 case CACHE_L2C_310_RTL_RELEASE_R3_P2:719 case L2C_310_RTL_RELEASE_R3_P3: 720 case L2C_310_RTL_RELEASE_R3_P2: 721 721 is_applicable = false; 722 722 break; 723 case CACHE_L2C_310_RTL_RELEASE_R3_P1:724 case CACHE_L2C_310_RTL_RELEASE_R3_P0:725 case CACHE_L2C_310_RTL_RELEASE_R2_P0:726 case CACHE_L2C_310_RTL_RELEASE_R1_P0:727 case CACHE_L2C_310_RTL_RELEASE_R0_P0:723 case L2C_310_RTL_RELEASE_R3_P1: 724 case L2C_310_RTL_RELEASE_R3_P0: 725 case L2C_310_RTL_RELEASE_R2_P0: 726 case L2C_310_RTL_RELEASE_R1_P0: 727 case L2C_310_RTL_RELEASE_R0_P0: 728 728 is_applicable = true; 729 729 break; … … 743 743 744 744 switch ( rtl_release ) { 745 case CACHE_L2C_310_RTL_RELEASE_R3_P3:746 case CACHE_L2C_310_RTL_RELEASE_R3_P2:747 case CACHE_L2C_310_RTL_RELEASE_R3_P1:748 case CACHE_L2C_310_RTL_RELEASE_R3_P0:749 case CACHE_L2C_310_RTL_RELEASE_R2_P0:745 case L2C_310_RTL_RELEASE_R3_P3: 746 case L2C_310_RTL_RELEASE_R3_P2: 747 case L2C_310_RTL_RELEASE_R3_P1: 748 case L2C_310_RTL_RELEASE_R3_P0: 749 case L2C_310_RTL_RELEASE_R2_P0: 750 750 is_applicable = false; 751 751 break; 752 case CACHE_L2C_310_RTL_RELEASE_R1_P0:753 case CACHE_L2C_310_RTL_RELEASE_R0_P0:752 case L2C_310_RTL_RELEASE_R1_P0: 753 case L2C_310_RTL_RELEASE_R0_P0: 754 754 is_applicable = true; 755 755 break; … … 770 770 771 771 switch ( rtl_release ) { 772 case CACHE_L2C_310_RTL_RELEASE_R3_P3:773 case CACHE_L2C_310_RTL_RELEASE_R3_P2:774 case CACHE_L2C_310_RTL_RELEASE_R3_P1:775 case CACHE_L2C_310_RTL_RELEASE_R3_P0:776 case CACHE_L2C_310_RTL_RELEASE_R2_P0:777 case CACHE_L2C_310_RTL_RELEASE_R1_P0:778 case CACHE_L2C_310_RTL_RELEASE_R0_P0:772 case L2C_310_RTL_RELEASE_R3_P3: 773 case L2C_310_RTL_RELEASE_R3_P2: 774 case L2C_310_RTL_RELEASE_R3_P1: 775 case L2C_310_RTL_RELEASE_R3_P0: 776 case L2C_310_RTL_RELEASE_R2_P0: 777 case L2C_310_RTL_RELEASE_R1_P0: 778 case L2C_310_RTL_RELEASE_R0_P0: 779 779 is_applicable = true; 780 780 break; … … 825 825 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 826 826 827 assert( 0 == ( l2cc->aux_ctrl & CACHE_L2C_310_L2CC_AUX_HPSODRE_MASK ) );827 assert( 0 == ( l2cc->aux_ctrl & L2C_310_AUX_HPSODRE_MASK ) ); 828 828 829 829 /* Erratum: 729815 The âHigh Priority for SO and Dev readsâ feature can … … 861 861 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 862 862 863 assert( !( ( l2cc->aux_ctrl & CACHE_L2C_310_L2CC_AUX_IPFE_MASK864 || l2cc->aux_ctrl & CACHE_L2C_310_L2CC_AUX_DPFE_MASK )865 && ( ( l2cc->prefetch_ctrl & CACHE_L2C_310_L2CC_PREFETCH_OFFSET_MASK )863 assert( !( ( l2cc->aux_ctrl & L2C_310_AUX_IPFE_MASK 864 || l2cc->aux_ctrl & L2C_310_AUX_DPFE_MASK ) 865 && ( ( l2cc->prefetch_ctrl & L2C_310_PREFETCH_OFFSET_MASK ) 866 866 == 23 ) ) ); 867 867 … … 889 889 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 890 890 cache_l2c_310_rtl_release rtl_release = 891 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;891 l2cc->cache_id & L2C_310_ID_RTL_MASK; 892 892 893 893 if( l2c_310_cache_errata_is_applicable_753970( rtl_release ) ) { … … 927 927 /* Back starting address up to start of a line and invalidate until ADDR_LAST */ 928 928 uint32_t adx = (uint32_t)d_addr 929 & ~ CACHE_L2C_310_DATA_LINE_MASK;929 & ~L2C_310_DATA_LINE_MASK; 930 930 const uint32_t ADDR_LAST = 931 931 (uint32_t)( (size_t)d_addr + n_bytes - 1 ); 932 932 uint32_t block_end = 933 CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES );933 L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES ); 934 934 volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; 935 935 cache_l2c_310_rtl_release rtl_release = 936 l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;936 l2cc->cache_id & L2C_310_ID_RTL_MASK; 937 937 bool is_errata_588369_applicable = 938 938 l2c_310_cache_errata_is_applicable_588369( rtl_release ); … … 943 943 adx <= ADDR_LAST; 944 944 adx = block_end + 1, 945 block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES )) {945 block_end = L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES )) { 946 946 for (; adx <= block_end; adx += CPU_DATA_CACHE_ALIGNMENT ) { 947 947 cache_l2c_310_flush_1_line( (void*)adx, is_errata_588369_applicable ); … … 963 963 964 964 /* Only flush if level 2 cache is active */ 965 if( ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) != 0 ) {965 if( ( l2cc->ctrl & L2C_310_ENABLE_MASK ) != 0 ) { 966 966 967 967 /* ensure ordering with previous memory accesses */ … … 969 969 970 970 rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context ); 971 l2cc->clean_inv_way = CACHE_l2C_310_WAY_MASK;972 973 while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) {};971 l2cc->clean_inv_way = L2C_310_WAY_MASK; 972 973 while ( l2cc->clean_inv_way & L2C_310_WAY_MASK ) {}; 974 974 975 975 /* Wait for the flush to complete */ … … 1017 1017 _ARM_Data_memory_barrier(); 1018 1018 1019 l2cc->inv_way = CACHE_l2C_310_WAY_MASK;1020 1021 while ( l2cc->inv_way & CACHE_l2C_310_WAY_MASK ) ;1019 l2cc->inv_way = L2C_310_WAY_MASK; 1020 1021 while ( l2cc->inv_way & L2C_310_WAY_MASK ) ; 1022 1022 1023 1023 /* Wait for the invalidate to complete */ … … 1031 1031 rtems_interrupt_lock_context lock_context; 1032 1032 1033 if( ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) != 0 ) {1033 if( ( l2cc->ctrl & L2C_310_ENABLE_MASK ) != 0 ) { 1034 1034 /* Invalidate the caches */ 1035 1035 … … 1038 1038 1039 1039 rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context ); 1040 l2cc->clean_inv_way = CACHE_l2C_310_WAY_MASK;1041 1042 while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) ;1040 l2cc->clean_inv_way = L2C_310_WAY_MASK; 1041 1042 while ( l2cc->clean_inv_way & L2C_310_WAY_MASK ) ; 1043 1043 1044 1044 /* Wait for the invalidate to complete */ … … 1072 1072 uint32_t num_ways; 1073 1073 1074 way_size = (cache_type & CACHE_L2C_310_L2CC_TYPE_SIZE_D_WAYS_MASK)1075 >> CACHE_L2C_310_L2CC_TYPE_SIZE_D_WAYS_SHIFT;1076 num_ways = (cache_type & CACHE_L2C_310_L2CC_TYPE_NUM_D_WAYS_MASK)1077 >> CACHE_L2C_310_L2CC_TYPE_NUM_D_WAYS_SHIFT;1074 way_size = (cache_type & L2C_310_TYPE_SIZE_D_WAYS_MASK) 1075 >> L2C_310_TYPE_SIZE_D_WAYS_SHIFT; 1076 num_ways = (cache_type & L2C_310_TYPE_NUM_D_WAYS_MASK) 1077 >> L2C_310_TYPE_NUM_D_WAYS_SHIFT; 1078 1078 1079 1079 assert( way_size <= 0x07 ); … … 1125 1125 static void cache_l2c_310_wait_for_background_ops( volatile L2CC *l2cc ) 1126 1126 { 1127 while ( l2cc->inv_way & CACHE_l2C_310_WAY_MASK ) ;1128 1129 while ( l2cc->clean_way & CACHE_l2C_310_WAY_MASK ) ;1130 1131 while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) ;1127 while ( l2cc->inv_way & L2C_310_WAY_MASK ) ; 1128 1129 while ( l2cc->clean_way & L2C_310_WAY_MASK ) ; 1130 1131 while ( l2cc->clean_inv_way & L2C_310_WAY_MASK ) ; 1132 1132 } 1133 1133 1134 1134 /* We support only the L2C-310 revisions r3p2 and r3p3 cache controller */ 1135 1135 1136 #if (BSP_ARM_L2C_310_ID & CACHE_L2C_310_L2CC_ID_PART_MASK) \1137 != CACHE_L2C_310_L2CC_ID_PART_L3101136 #if (BSP_ARM_L2C_310_ID & L2C_310_ID_PART_MASK) \ 1137 != L2C_310_ID_PART_L310 1138 1138 #error "invalid L2-310 cache controller part number" 1139 1139 #endif 1140 1140 1141 #if ((BSP_ARM_L2C_310_ID & CACHE_L2C_310_L2CC_ID_RTL_MASK) != 0x8) \1142 && ((BSP_ARM_L2C_310_ID & CACHE_L2C_310_L2CC_ID_RTL_MASK) != 0x9)1141 #if ((BSP_ARM_L2C_310_ID & L2C_310_ID_RTL_MASK) != 0x8) \ 1142 && ((BSP_ARM_L2C_310_ID & L2C_310_ID_RTL_MASK) != 0x9) 1143 1143 #error "invalid L2-310 cache controller RTL revision" 1144 1144 #endif … … 1150 1150 uint32_t cache_id = l2cc->cache_id; 1151 1151 cache_l2c_310_rtl_release rtl_release = 1152 cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;1152 cache_id & L2C_310_ID_RTL_MASK; 1153 1153 uint32_t id_mask = 1154 CACHE_L2C_310_L2CC_ID_IMPL_MASK | CACHE_L2C_310_L2CC_ID_PART_MASK;1154 L2C_310_ID_IMPL_MASK | L2C_310_ID_PART_MASK; 1155 1155 1156 1156 /* … … 1160 1160 if ( 1161 1161 (BSP_ARM_L2C_310_ID & id_mask) != (cache_id & id_mask) 1162 || rtl_release < (BSP_ARM_L2C_310_ID & CACHE_L2C_310_L2CC_ID_RTL_MASK)1162 || rtl_release < (BSP_ARM_L2C_310_ID & L2C_310_ID_RTL_MASK) 1163 1163 ) { 1164 1164 bsp_fatal( ARM_FATAL_L2C_310_UNEXPECTED_ID ); … … 1168 1168 1169 1169 /* Only enable if L2CC is currently disabled */ 1170 if( ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) == 0 ) {1170 if( ( l2cc->ctrl & L2C_310_ENABLE_MASK ) == 0 ) { 1171 1171 uint32_t aux_ctrl; 1172 1172 int ways; … … 1185 1185 } 1186 1186 1187 if ( ways != CACHE_l2C_310_NUM_WAYS ) {1187 if ( ways != L2C_310_NUM_WAYS ) { 1188 1188 bsp_fatal( ARM_FATAL_L2C_310_UNEXPECTED_NUM_WAYS ); 1189 1189 } 1190 1190 1191 1191 /* Set up the way size */ 1192 aux_ctrl &= CACHE_L2C_310_L2CC_AUX_REG_ZERO_MASK; /* Set way_size to 0 */1193 aux_ctrl |= CACHE_L2C_310_L2CC_AUX_REG_DEFAULT_MASK;1192 aux_ctrl &= L2C_310_AUX_REG_ZERO_MASK; /* Set way_size to 0 */ 1193 aux_ctrl |= L2C_310_AUX_REG_DEFAULT_MASK; 1194 1194 1195 1195 l2cc->aux_ctrl = aux_ctrl; 1196 1196 1197 1197 /* Set up the latencies */ 1198 l2cc->tag_ram_ctrl = CACHE_L2C_310_L2CC_TAG_RAM_DEFAULT_LAT;1199 l2cc->data_ram_ctrl = CACHE_L2C_310_L2CC_DATA_RAM_DEFAULT_MASK;1198 l2cc->tag_ram_ctrl = L2C_310_TAG_RAM_DEFAULT_LAT; 1199 l2cc->data_ram_ctrl = L2C_310_DATA_RAM_DEFAULT_MASK; 1200 1200 1201 1201 cache_l2c_310_invalidate_entire(); … … 1205 1205 1206 1206 /* Enable the L2CC */ 1207 l2cc->ctrl |= CACHE_L2C_310_L2CC_ENABLE_MASK;1207 l2cc->ctrl |= L2C_310_ENABLE_MASK; 1208 1208 } 1209 1209 } … … 1215 1215 rtems_interrupt_lock_context lock_context; 1216 1216 1217 if ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) {1217 if ( l2cc->ctrl & L2C_310_ENABLE_MASK ) { 1218 1218 /* Clean and Invalidate L2 Cache */ 1219 1219 cache_l2c_310_flush_entire(); … … 1223 1223 1224 1224 /* Disable the L2 cache */ 1225 l2cc->ctrl &= ~ CACHE_L2C_310_L2CC_ENABLE_MASK;1225 l2cc->ctrl &= ~L2C_310_ENABLE_MASK; 1226 1226 rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context ); 1227 1227 } … … 1288 1288 /* Back starting address up to start of a line and invalidate until ADDR_LAST */ 1289 1289 uint32_t adx = (uint32_t) addr_first 1290 & ~ CACHE_L2C_310_DATA_LINE_MASK;1290 & ~L2C_310_DATA_LINE_MASK; 1291 1291 const uint32_t ADDR_LAST = 1292 1292 (uint32_t)( (size_t)addr_first + n_bytes - 1 ); 1293 1293 uint32_t block_end = 1294 CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES );1295 1296 /* We have to apply a lock. Thus we will operate only CACHE_MAX_LOCKING_BYTES1294 L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES ); 1295 1296 /* We have to apply a lock. Thus we will operate only L2C_310_MAX_LOCKING_BYTES 1297 1297 * at a time */ 1298 1298 for (; 1299 1299 adx <= ADDR_LAST; 1300 1300 adx = block_end + 1, 1301 block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES )) {1301 block_end = L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES )) { 1302 1302 cache_l2c_310_invalidate_range( 1303 1303 adx, … … 1310 1310 ); 1311 1311 1312 adx = (uint32_t)addr_first & ~ CACHE_L2C_310_DATA_LINE_MASK;1313 block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES );1312 adx = (uint32_t)addr_first & ~L2C_310_DATA_LINE_MASK; 1313 block_end = L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES ); 1314 1314 for (; 1315 1315 adx <= ADDR_LAST; 1316 1316 adx = block_end + 1, 1317 block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES )) {1317 block_end = L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES )) { 1318 1318 cache_l2c_310_invalidate_range( 1319 1319 adx,
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