Changeset 84c53452 in rtems


Ignore:
Timestamp:
Apr 16, 2004, 11:08:36 AM (16 years ago)
Author:
Ralf Corsepius <ralf.corsepius@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
c9520165
Parents:
27138f3
Message:

Remove stray white spaces.

Location:
cpukit/score/cpu/i386
Files:
6 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/i386/cpu.c

    r27138f3 r84c53452  
    7777 *  _CPU_ISR_Get_level
    7878 */
    79  
     79
    8080uint32_t   _CPU_ISR_Get_level( void )
    8181{
    8282  uint32_t   level;
    83  
     83
    8484  i386_get_interrupt_level( level );
    85  
     85
    8686  return level;
    8787}
     
    185185      unsigned                   limit;
    186186      unsigned                   level;
    187      
     187
    188188      i = sizeof(tbl) / sizeof (rtems_raw_irq_hdl);
    189189
  • cpukit/score/cpu/i386/cpu_asm.S

    r27138f3 r84c53452  
    119119        addl    $8, esp                    /* skill vector number and faultCode */
    120120        iret
    121                
     121
    122122#define DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY(_vector) \
    123123        .p2align 4                         ; \
     
    137137/*
    138138 * Divide Error
    139  */     
     139 */
    140140DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (0)
    141141/*
    142142 * Debug Exception
    143  */     
     143 */
    144144DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (1)
    145145/*
    146146 * NMI
    147  */     
     147 */
    148148DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (2)
    149149/*
    150150 * Breakpoint
    151  */     
     151 */
    152152DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (3)
    153153/*
    154154 * Overflow
    155  */     
     155 */
    156156DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (4)
    157157/*
    158158 * Bound Range Exceeded
    159  */     
     159 */
    160160DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (5)
    161161/*
    162162 * Invalid Opcode
    163  */     
     163 */
    164164DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (6)
    165165/*
    166166 * No Math Coproc
    167  */     
     167 */
    168168DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (7)
    169169/*
    170170 * Double Fault
    171  */     
     171 */
    172172DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (8)
    173173/*
    174174 * Coprocessor segment overrun
    175  */     
     175 */
    176176DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (9)
    177177/*
    178178 * Invalid TSS
    179  */     
     179 */
    180180DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (10)
    181181/*
    182182 * Segment Not Present
    183  */     
     183 */
    184184DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (11)
    185185/*
    186186 * Stack segment Fault
    187  */     
     187 */
    188188DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (12)
    189189/*
    190190 * General Protection Fault
    191  */     
     191 */
    192192DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (13)
    193193/*
    194194 * Page Fault
    195  */     
     195 */
    196196DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (14)
    197197/*
    198198 * Floating point error (NB 15 is reserved it is therefor skipped)
    199  */     
     199 */
    200200DISTINCT_EXCEPTION_WITHOUT_FAULTCODE_ENTRY (16)
    201201/*
    202202 * Aligment Check
    203  */     
     203 */
    204204DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (17)
    205205/*
    206206 * Machine Check
    207  */     
     207 */
    208208DISTINCT_EXCEPTION_WITH_FAULTCODE_ENTRY (18)
    209        
     209
    210210
    211211/*
  • cpukit/score/cpu/i386/rtems/score/cpu.h

    r27138f3 r84c53452  
    4444/*
    4545 *  Does the RTEMS invoke the user's ISR with the vector number and
    46  *  a pointer to the saved interrupt frame (1) or just the vector 
     46 *  a pointer to the saved interrupt frame (1) or just the vector
    4747 *  number (0)?
    4848 */
     
    7171/*
    7272 *  Does this port provide a CPU dependent IDLE task implementation?
    73  * 
     73 *
    7474 *  If TRUE, then the routine _CPU_Thread_Idle_body
    7575 *  must be provided and is the default IDLE thread body instead of
     
    7979 *  not provide one.
    8080 */
    81  
     81
    8282#define CPU_PROVIDES_IDLE_THREAD_BODY    TRUE
    8383
     
    175175
    176176} Intel_symbolic_exception_name;
    177  
     177
    178178
    179179/*
     
    200200
    201201/*
    202  *  Macros to access required entires in the CPU Table are in 
     202 *  Macros to access required entires in the CPU Table are in
    203203 *  the file rtems/system.h.
    204204 */
     
    430430 *  _CPU_ISR_install_raw_handler
    431431 *
    432  *  This routine installs a "raw" interrupt handler directly into the 
     432 *  This routine installs a "raw" interrupt handler directly into the
    433433 *  processor's vector table.
    434434 */
    435  
     435
    436436void _CPU_ISR_install_raw_handler(
    437437  uint32_t    vector,
  • cpukit/score/cpu/i386/rtems/score/i386.h

    r27138f3 r84c53452  
    3939 *  CPU Model Feature Flags:
    4040 *
    41  *  I386_HAS_BSWAP:  Defined to "1" if the instruction for endian swapping 
     41 *  I386_HAS_BSWAP:  Defined to "1" if the instruction for endian swapping
    4242 *                   (bswap) should be used.  This instruction appears to
    4343 *                   be present in all i486's and above.
     
    146146 * Added for pagination management
    147147 */
    148  
     148
    149149static inline unsigned int i386_get_cr0()
    150150{
     
    214214
    215215/* segment access routines */
    216  
     216
    217217#define get_cs()   i386_get_cs()
    218218#define get_ds()   i386_get_ds()
     
    221221#define get_fs()   i386_get_fs()
    222222#define get_gs()   i386_get_gs()
    223  
     223
    224224#define CPU_swap_u32( _value )  i386_swap_u32( _value )
    225225#define CPU_swap_u16( _value )  i386_swap_u16( _value )
    226  
     226
    227227/* i80x86 I/O instructions */
    228  
     228
    229229#define outport_byte( _port, _value ) i386_outport_byte( _port, _value )
    230230#define outport_word( _port, _value ) i386_outport_word( _port, _value )
     
    233233#define inport_word( _port, _value )  i386_inport_word( _port, _value )
    234234#define inport_long( _port, _value )  i386_inport_long( _port, _value )
    235  
     235
    236236
    237237#ifdef __cplusplus
  • cpukit/score/cpu/i386/rtems/score/interrupts.h

    r27138f3 r84c53452  
    99 *  found in the file LICENSE in this distribution or at
    1010 *  http://www.rtems.com/license/LICENSE.
    11  * 
     11 *
    1212 *  $Id$
    1313 *
     
    7171#define _CPU_ISR_Disable( _level ) i386_disable_interrupts( _level )
    7272#define _CPU_ISR_Enable( _level ) i386_enable_interrupts( _level )
    73      
     73
    7474#endif
    7575#endif
  • cpukit/score/cpu/i386/rtems/score/registers.h

    r27138f3 r84c53452  
    11/* registers.h
    2  * 
     2 *
    33 *  This file contains definition and constants related to Intel Cpu
    44 *
     
    107107  unsigned int id                       : 1;
    108108  unsigned int                          : 2;
    109  
     109
    110110  /*
    111111   * fourth byte : bits 24->31 : UNUSED
     
    129129  unsigned int coproc_soft_emul         : 1;
    130130  unsigned int floating_instr_except    : 1;
    131  
     131
    132132  unsigned int extension_type           : 1;
    133133  unsigned int numeric_error            : 1;
     
    150150   */
    151151  unsigned int                          : 4;
    152  
     152
    153153  unsigned int                          : 1;
    154154  unsigned int no_write_through         : 1;
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