Changeset 83d7232 in rtems
- Timestamp:
- 10/20/04 15:42:24 (19 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 2fd2786
- Parents:
- f801bf2
- Files:
-
- 10 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libcpu/powerpc/ChangeLog
rf801bf2 r83d7232 1 1 2004-10-20 Eric Norum <norume@aps.anl.gov> 2 2 3 * configure.ac: Add MPC7455 support 3 Add Kate Feng's MPC7455 support 4 * configure.ac 5 * mpc6xx/exceptions/raw_exception.c 6 * mpc6xx/mmu/mmuAsm.S 7 * mpc6xx/mmu/pte121.c 8 * shared/include/cpuIdent.c 9 * shared/include/cpuIdent.h 4 10 5 11 2004-10-19 Ralf Corsepius <ralf_corsepius@rtems.org> -
c/src/lib/libcpu/powerpc/mpc6xx/exceptions/raw_exception.c
rf801bf2 r83d7232 127 127 case PPC_604e: 128 128 case PPC_604r: 129 case PPC_7455: /* Kate Feng */ 129 130 if (!mpc604_vector_is_valid(vector)) { 130 131 return 0; -
c/src/lib/libcpu/powerpc/mpc6xx/mmu/mmuAsm.S
rf801bf2 r83d7232 14 14 * 15 15 * T. Straumann - 11/2001: added support for 7400 (no AltiVec yet) 16 * S.K. Feng - 10/2003: added support for 7455 (no AltiVec yet) 17 * 16 18 */ 17 19 … … 32 34 #define PPC_604r 0xA 33 35 #define PPC_7400 0xC 36 #define PPC_7455 0x8001 34 37 #define PPC_620 0x16 35 38 #define PPC_860 0x50 … … 51 54 #define DL1HWF (1<<(31-8)) 52 55 #define L2HWF (1<<(31-20)) 53 54 55 56 56 57 /* 57 58 * Each setdbat routine start by invalidating the DBAT as some … … 148 149 sync 149 150 isync 150 cmpi 0,r9,PPC_604 /* check for 604 */ 151 cmpi 1,r9,PPC_604e /* or 604e */ 152 cmpi 2,r9,PPC_604r /* or mach5 */ 153 cror 2,2,6 154 cror 2,2,10 155 cmpi 1,r9,PPC_750 /* or 750 */ 156 cror 2,2,6 157 cmpi 1,r9,PPC_7400 /* or 7400 */ 151 cmpi 1,r9,PPC_604 /* check for 604 */ 152 cmpi 2,r9,PPC_604e /* or 604e */ 153 cmpi 3,r9,PPC_604r /* or mach5 */ 154 cror 6,6,10 155 cror 6,6,14 156 cmpi 2,r9,PPC_750 /* or 750 */ 157 cror 6,6,10 158 cmpi 2,r9,PPC_7400 /* or 7400 */ 159 cror 6,6,10 160 cmpli 0,r9,PPC_7455 /* or 7455 */ 161 bne 2f 162 /* 7455:link register stack,branch folding & 163 * TBEN : enable the time base and decrementer. 164 * EMCP bit is defined in HID1. However, it's not used 165 * in mvme5500 board because of GT64260 (e.g. it's connected 166 * pull-up). 167 */ 168 oris r11,r11,(HID0_LRSTK|HID0_FOLD|HID0_TBEN)@h 169 ori r11,r11,(HID0_LRSTK|HID0_FOLD|HID0_TBEN)@l 170 2: cror 2,2,10 158 171 bne 3f 159 ori r11,r11,HID0_BTIC /* enable branch tgt cache on 7400 */172 ori r11,r11,HID0_BTIC /* enable branch tgt cache on 7400 & 7455 */ 160 173 3: cror 2,2,6 161 174 bne 4f … … 165 178 ori r11,r11,HID0_BTCD 166 179 5: mtspr HID0,r11 /* superscalar exec & br history tbl */ 180 sync /* for SGE bit */ 181 isync /* P2-17 to 2-22 in MPC7450UM */ 167 182 4: 168 183 blr 169 184 185 .globl get_L1CR 186 .type get_L1CR, @function 187 get_L1CR: 188 mfspr r3,HID0 189 blr 190 170 191 .globl get_L2CR 171 192 .type get_L2CR, @function … … 178 199 cmplwi r3,PPC_7400 /* it's a 7400 */ 179 200 beq 1f 180 li r3,0 201 cmplwi r3,PPC_7455 /* it's a 7455 */ 202 beq 1f 203 li r3,-1 181 204 blr 182 205 … … 225 248 cmplwi r0,PPC_7400 226 249 beq thisIs750 250 cmplwi r0,PPC_7455 251 beq thisIs750 227 252 li r3,-1 228 253 blr … … 235 260 /* See if we want to perform a global inval this time. */ 236 261 rlwinm r6,r3,0,10,10 /* r6 contains the new invalidate bit */ 237 rlwinm. r5,r3,0,0,0 262 rlwinm. r5,r3,0,0,0 /* r5 contains the new enable bit */ 238 263 rlwinm r3,r3,0,11,9 /* Turn off the invalidate bit */ 239 264 rlwinm r3,r3,0,1,31 /* Turn off the enable bit */ 240 or r3,r3,r4/* Keep the enable bit the same as it was for now. */241 mfmsr r7 265 or r3,r3,r4 /* Keep the enable bit the same as it was for now. */ 266 mfmsr r7 /* shut off interrupts around critical flush/invalidate sections */ 242 267 rlwinm r4,r7,0,17,15 /* Turn off EE bit - an external exception while we are flushing 243 268 the cache is fatal (comment this line and see!) */ 244 269 mtmsr r4 245 bne 246 247 cmplwi r0,PPC_7400 /* >7400 ? */248 bne 270 bne dontDisableCache /* Only disable the cache if L2CRApply has the enable bit off */ 271 272 cmplwi r0,PPC_7400 /* 7400 ? */ 273 bne disableCache /* use traditional method */ 249 274 250 275 /* On the 7400, they recommend using the hardware flush feature */ … … 258 283 /* L1 flushed */ 259 284 mfspr r4, L2CR 260 ori 285 ori r4, r4, L2HWF 261 286 mtspr L2CR, r4 262 287 sync 263 288 /* L2 flushed */ 264 b 289 b flushDone 265 290 266 291 disableCache: … … 268 293 rlwinm r4,r4,0,28,26 /* Turn off DR bit */ 269 294 mtmsr r4 270 isync /* make sure memory accesses have completed */ 271 295 isync /* make sure memory accesses have completed */ 296 cmplwi r0,PPC_7455 /* 7455 ? */ 297 bne not745x 298 /* 7455:L1 Load/Flush, L2, L3 : hardware flush */ 299 /* If not using AltiVec data streaming instructions,DSSALL not necessary */ 300 sync 301 mfspr r4, MSSCR0 302 rlwinm r4,r4,0,29,0 /* Turn off the L2PFE bits */ 303 mtspr MSSCR0, r4 304 sync 305 /* flush L1 first */ 306 lis r4,0x0001 307 mtctr r4 308 li r4,0 309 li r0,0 310 loadFlush: 311 lwzx r0,r0,r4 312 dcbf r0,r4 313 addi r4,r4,CACHE_LINE_SIZE /* Go to start of next cache line */ 314 bdnz loadFlush 315 sync 316 /* Set the L2CR[L2IO & L2DO] bits to completely lock the L2 cache */ 317 mfspr r0, L2CR 318 lis r4,L2CR_LOCK_745x@h 319 ori r4,r4,L2CR_LOCK_745x@l 320 or r4,r0,r4 321 rlwinm r4,r4,0,11,9 /* make sure the invalidate bit off */ 322 mtspr L2CR, r4 323 sync 324 ori r4, r4, L2HWF 325 mtspr L2CR, r4 326 sync 327 /* L2 flushed,L2IO & L2DO got cleared in the dontDisableCache: */ 328 b reenableDR 329 330 not745x: 272 331 /* 273 332 Now, read the first 2MB of memory to put new data in the cache. … … 275 334 the size of the L1 cache, but 2MB will cover everything just to be safe). 276 335 */ 277 lis 336 lis r4,0x0001 278 337 mtctr r4 279 li 338 li r4,0 280 339 loadLoop: 281 340 lwzx r0,r0,r4 … … 293 352 bdnz flushLoop 294 353 sync 295 354 reenableDR: 296 355 rlwinm r4,r7,0,17,15 /* still mask EE but reenable data relocation */ 297 356 mtmsr r4 … … 339 398 sync 340 399 blr 400 401 402 .globl get_L3CR 403 .type get_L3CR, @function 404 get_L3CR: 405 /* Make sure this is a 7455 chip */ 406 mfspr r3,PVR 407 rlwinm r3,r3,16,16,31 408 cmplwi r3,PPC_7455 /* it's a 7455 */ 409 beq 1f 410 li r3,-1 411 blr 412 413 1: 414 /* Return the L3CR contents */ 415 mfspr r3,L3CR 416 blr 417 418 .globl set_L3CR 419 .type set_L3CR, @function 420 set_L3CR: 421 /* Usage: 422 * When setting the L3CR register, you must do a few special things. 423 * If you are enabling the cache, you must perform a global invalidate. 424 * Then call cpu_enable_l3cr(l3cr). 425 * If you are disabling the cache, you must flush the cache contents first. 426 * This routine takes care of doing these things. If you 427 * want to modify the L3CR contents after the cache has been enabled, 428 * the recommended procedure is to first call __setL3CR(0) to disable 429 * the cache and then call cpu_enable_l3cr with the new values for 430 * L3CR. 431 */ 432 433 /* Make sure this is a 7455 chip */ 434 mfspr r0,PVR 435 rlwinm r0,r0,16,16,31 436 cmplwi r0,PPC_7455 437 beq thisIs7455 438 li r3,-1 439 blr 440 441 thisIs7455: 442 /* Get the current enable bit of the L3CR into r4 */ 443 mfspr r4,L3CR 444 rlwinm r4,r4,0,0,0 445 446 /* See if we want to perform a global inval this time. */ 447 rlwinm r6,r3,0,10,10 /* r6 contains the new invalidate bit */ 448 rlwinm. r5,r3,0,0,0 /* r5 contains the new enable bit */ 449 rlwinm r3,r3,0,11,9 /* Turn off the invalidate bit */ 450 rlwinm r3,r3,0,1,31 /* Turn off the enable bit */ 451 or r3,r3,r4 /* Keep the enable bit the same as it was for now. */ 452 mfmsr r7 /* shut off interrupts around critical flush/invalidate sections */ 453 rlwinm r4,r7,0,17,15 /* Turn off EE bit - an external exception while we are flushing 454 the cache is fatal (comment this line and see!) */ 455 mtmsr r4 456 bne dontDisableL3Cache /* Only disable the cache if L3CRApply has the enable bit off */ 457 /* Before the L3 is disabled, it must be flused to prevent coherency problems */ 458 /* First, we turn off data relocation. */ 459 rlwinm r4,r4,0,28,26 /* Turn off DR bit */ 460 mtmsr r4 461 isync /* make sure memory accesses have completed */ 462 /* 7455: L3 : hardware flush 463 * Set the L3CR[L3IO & L3DO] bits to completely lock the L3 cache */ 464 mfspr r0, L3CR 465 lis r4, L3CR_LOCK_745x@h 466 ori r4,r4, L3CR_LOCK_745x@l 467 or r4,r0,r4 468 rlwinm r4,r4,0,11,9 /* make sure the invalidate bit off */ 469 mtspr L3CR, r4 470 sync 471 ori r4, r4, L3CR_L3HWF 472 mtspr L3CR, r4 473 sync 474 /* L3 flushed,L3IO & L3DO got cleared in the dontDisableL3Cache: */ 475 rlwinm r4,r7,0,17,15 /* still mask EE but reenable data relocation */ 476 mtmsr r4 477 isync 478 479 /* Turn off the L3CR enable bit. */ 480 rlwinm r3,r3,0,1,31 481 482 dontDisableL3Cache: 483 /* Set up the L3CR configuration bits */ 484 sync 485 mtspr L3CR,r3 486 sync 487 ifL3Inval: 488 cmplwi r6,0 489 beq noL3Inval 490 491 /* Perform a global invalidation */ 492 oris r3,r3,0x0020 493 sync 494 mtspr L3CR,r3 495 sync 496 invalCompleteL3: /* Wait for the invalidation to complete */ 497 mfspr r3,L3CR 498 rlwinm. r4,r3,0,31,31 499 bne invalCompleteL3 500 501 rlwinm r3,r3,0,11,9; /* Turn off the L3I bit */ 502 sync 503 mtspr L3CR,r3 504 sync 505 506 noL3Inval: 507 /* re-enable interrupts, i.e. restore original MSR */ 508 mtmsr r7 /* (no sync needed) */ 509 /* See if we need to enable the cache */ 510 cmplwi r5,0 511 beqlr 512 513 enableL3Cache: 514 /* Enable the cache */ 515 oris r3,r3,0x8000 516 mtspr L3CR,r3 517 sync 518 blr -
c/src/lib/libcpu/powerpc/mpc6xx/mmu/pte121.c
rf801bf2 r83d7232 383 383 PPC_604r !=current_ppc_cpu && 384 384 PPC_750 !=current_ppc_cpu && 385 PPC_7400 !=current_ppc_cpu ) 385 PPC_7400 !=current_ppc_cpu && 386 PPC_7455 !=current_ppc_cpu ) 386 387 return 0; /* unsupported by this CPU */ 387 388 … … 426 427 triv121PgTblMap( 427 428 Triv121PgTbl pt, 428 long 429 long ovsid, 429 430 unsigned long start, 430 431 unsigned long numPages, … … 433 434 ) 434 435 { 435 int 436 int i,pass; 436 437 unsigned long pi; 437 PTE 438 438 PTE pte; 439 long vsid; 439 440 /* already activated - no change allowed */ 440 441 if (pt->active) 441 442 return -1; 442 443 443 if ( vsid < 0) {444 if (ovsid < 0) { 444 445 /* use 1:1 mapping */ 445 vsid = VSID121(start);446 ovsid = VSID121(start); 446 447 } 447 448 … … 466 467 for (pass=0; pass<2; pass++) { 467 468 /* check if we would succeed during the first pass */ 468 for (i=0, pi=PI121(start); i<numPages; i++,pi++) { 469 for (i=0, pi=PI121(start), vsid = ovsid; i<numPages; i++,pi++) { 470 if ( pi >= 1<<LD_PI_SIZE ) { 471 vsid++; 472 pi = 0; 473 } 469 474 /* leave alone existing mappings for this EA */ 470 475 if (!alreadyMapped(pt, vsid, pi)) { -
c/src/lib/libcpu/powerpc/rtems/powerpc/powerpc.h
rf801bf2 r83d7232 261 261 262 262 #define PPC_ALIGNMENT 8 263 #define PPC_I_CACHE 32768 264 #define PPC_D_CACHE 32768 265 266 #elif defined(mpc7455) 267 /* 268 * Added by S.K. Feng <feng1@bnl.gov> 10/03 269 */ 270 271 #define CPU_MODEL_NAME "PowerPC 7455" 272 273 #define PPC_ALIGNMENT 8 274 #define PPC_CACHE_ALIGNMENT 32 263 275 #define PPC_I_CACHE 32768 264 276 #define PPC_D_CACHE 32768 -
c/src/lib/libcpu/powerpc/shared/include/cpuIdent.c
rf801bf2 r83d7232 37 37 case PPC_750: return "MPC750"; 38 38 case PPC_7400: return "MPC7400"; 39 case PPC_7455: return "MPC7455"; 39 40 case PPC_604e: return "MPC604e"; 40 41 case PPC_604r: return "MPC604r"; … … 61 62 case PPC_750: 62 63 case PPC_7400: 64 case PPC_7455: 63 65 case PPC_604e: 64 66 case PPC_620: -
c/src/lib/libcpu/powerpc/shared/include/cpuIdent.h
rf801bf2 r83d7232 30 30 PPC_604r = 0xA, 31 31 PPC_7400 = 0xC, 32 PPC_7455 = 0x8001, /* Kate Feng */ 32 33 PPC_620 = 0x16, 33 34 PPC_860 = 0x50, -
cpukit/score/cpu/powerpc/ChangeLog
rf801bf2 r83d7232 1 2004-10-20 Eric Norum <norume@aps.anl.gov 2 3 Add Kate Feng's MVME5500 BSP 4 * rtems/powerpc/registers.h, rtems/score/powerpc.h 5 1 6 2004-09-29 Joel Sherrill <joel@OARcorp.com> 2 7 -
cpukit/score/cpu/powerpc/rtems/powerpc/registers.h
rf801bf2 r83d7232 51 51 #define HID0_EBD (1<<28) /* Enable Bus Data Parity */ 52 52 #define HID0_SBCLK (1<<27) 53 #define HID0_TBEN (1<<26) /* 7455:this bit must be set 54 * and TBEN signal must be asserted 55 * to enable the time base and 56 * decrementer. 57 */ 53 58 #define HID0_EICE (1<<26) 54 59 #define HID0_ECLK (1<<25) … … 66 71 #define HID0_SIED (1<<7) /* Serial Instruction Execution [Disable] */ 67 72 #define HID0_BTIC (1<<5) /* Branch Target Instruction Cache [Enable] */ 73 /* S.K. Feng 10/03, added for MPC7455 */ 74 #define HID0_LRSTK (1<<4) /* Link register stack enable (7455) */ 75 #define HID0_FOLD (1<<3) /* Branch folding enable (7455) */ 76 68 77 #define HID0_BHTE (1<<2) /* Branch History Table Enable */ 69 78 #define HID0_BTCD (1<<1) /* Branch target cache disable */ … … 144 153 #define DEC 22 /* Decrementer */ 145 154 #define EAR 282 /* External Address Register */ 146 #define L2CR 1017 /* PPC 750 L2 control register */ 155 156 #define MSSCR0 1014 /* Memory Subsystem Control Register */ 157 158 #define L2CR 1017 /* PPC 750 and 74xx L2 control register */ 159 160 #define L2CR_L2E (1<<31) /* enable */ 161 #define L2CR_L2I (1<<21) /* global invalidate */ 162 163 /* watch out L2IO and L2DO are different between 745x and 7400/7410 */ 164 /* Oddly, the following L2CR bit defintions in 745x 165 * is different from that of 7400 and 7410. 166 * Though not used in 7400 and 7410, it is appeded with _745x just 167 * to be clarified. 168 */ 169 #define L2CR_L2IO_745x 0x100000 /* (1<<20) L2 Instruction-Only */ 170 #define L2CR_L2DO_745x 0x10000 /* (1<<16) L2 Data-Only */ 171 #define L2CR_LOCK_745x (L2CR_L2IO_745x|L2CR_L2DO_745x) 172 #define L2CR_L3OH0 0x00080000 /* 12:L3 output hold 0 */ 173 174 #define L3CR 1018 /* PPC 7450/7455 L3 control register */ 175 #define L3CR_L3IO_745x 0x400000 /* (1<<22) L3 Instruction-Only */ 176 #define L3CR_L3DO_745x 0x40 /* (1<<6) L3 Data-Only */ 177 178 #define L3CR_LOCK_745x (L3CR_L3IO_745x|L3CR_L3DO_745x) 179 180 #define L3CR_RESERVED 0x0438003a /* Reserved bits in L3CR */ 181 #define L3CR_L3E 0x80000000 /* 0: L3 enable */ 182 #define L3CR_L3PE 0x40000000 /* 1: L3 data parity checking enable */ 183 #define L3CR_L3APE 0x20000000 /* 2: L3 address parity checking enable */ 184 #define L3CR_L3SIZ 0x10000000 /* 3: L3 size (0=1MB, 1=2MB) */ 185 #define L3SIZ_1M 0x00000000 186 #define L3SIZ_2M 0x10000000 187 #define L3CR_L3CLKEN 0x08000000 /* 4: Enables the L3_CLK[0:1] signals */ 188 #define L3CR_L3CLK 0x03800000 /* 6-8: L3 clock ratio */ 189 #define L3CLK_60 0x00000000 /* core clock / 6 */ 190 #define L3CLK_20 0x01000000 /* / 2 */ 191 #define L3CLK_25 0x01800000 /* / 2.5 */ 192 #define L3CLK_30 0x02000000 /* / 3 */ 193 #define L3CLK_35 0x02800000 /* / 3.5 */ 194 #define L3CLK_40 0x03000000 /* / 4 */ 195 #define L3CLK_50 0x03800000 /* / 5 */ 196 #define L3CR_L3IO 0x00400000 /* 9: L3 instruction-only mode */ 197 #define L3CR_L3SPO 0x00040000 /* 13: L3 sample point override */ 198 #define L3CR_L3CKSP 0x00030000 /* 14-15: L3 clock sample point */ 199 #define L3CKSP_2 0x00000000 /* 2 clocks */ 200 #define L3CKSP_3 0x00010000 /* 3 clocks */ 201 #define L3CKSP_4 0x00020000 /* 4 clocks */ 202 #define L3CKSP_5 0x00030000 /* 5 clocks */ 203 #define L3CR_L3PSP 0x0000e000 /* 16-18: L3 P-clock sample point */ 204 #define L3PSP_0 0x00000000 /* 0 clocks */ 205 #define L3PSP_1 0x00002000 /* 1 clocks */ 206 #define L3PSP_2 0x00004000 /* 2 clocks */ 207 #define L3PSP_3 0x00006000 /* 3 clocks */ 208 #define L3PSP_4 0x00008000 /* 4 clocks */ 209 #define L3PSP_5 0x0000a000 /* 5 clocks */ 210 #define L3CR_L3REP 0x00001000 /* 19: L3 replacement algorithm (0=default, 1=alternate) */ 211 #define L3CR_L3HWF 0x00000800 /* 20: L3 hardware flush */ 212 #define L3CR_L3I 0x00000400 /* 21: L3 global invaregisters.h.orig 213 lidate */ 214 #define L3CR_L3RT 0x00000300 /* 22-23: L3 SRAM type */ 215 #define L3RT_MSUG2_DDR 0x00000000 /* MSUG2 DDR SRAM */ 216 #define L3RT_PIPELINE_LATE 0x00000100 /* Pipelined (register-register) synchronous late-write SRAM */ 217 #define L3RT_PB2_SRAM 0x00000300 /* PB2 SRAM */ 218 #define L3CR_L3NIRCA 0x00000080 /* 24: L3 non-integer ratios clock adjustment for the SRAM */ 219 #define L3CR_L3DO 0x00000040 /* 25: L3 data-only mode */ 220 #define L3CR_PMEN 0x00000004 /* 29: Private memory enable */ 221 #define L3CR_PMSIZ 0x00000004 /* 31: Private memory size (0=1MB, 1=2MB) */ 147 222 148 223 #define THRM1 1020 -
cpukit/score/cpu/powerpc/rtems/score/powerpc.h
rf801bf2 r83d7232 261 261 262 262 #define PPC_ALIGNMENT 8 263 #define PPC_I_CACHE 32768 264 #define PPC_D_CACHE 32768 265 266 #elif defined(mpc7455) 267 /* 268 * Added by S.K. Feng <feng1@bnl.gov> 10/03 269 */ 270 271 #define CPU_MODEL_NAME "PowerPC 7455" 272 273 #define PPC_ALIGNMENT 8 274 #define PPC_CACHE_ALIGNMENT 32 263 275 #define PPC_I_CACHE 32768 264 276 #define PPC_D_CACHE 32768
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