Changeset 83b1b25d in rtems


Ignore:
Timestamp:
Mar 2, 2021, 11:31:45 AM (7 weeks ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
a510e243
Parents:
9a13f37
git-author:
Sebastian Huber <sebastian.huber@…> (03/02/21 11:31:45)
git-committer:
Sebastian Huber <sebastian.huber@…> (03/02/21 20:46:52)
Message:

rtems: Simplify rtems_signal_catch()

In uniprocessor configurations, we can simplify rtems_signal_catch().
Add a validation test for the SMP special case.

Files:
2 edited

Legend:

Unmodified
Added
Removed
  • cpukit/rtems/src/signalcatch.c

    r9a13f37 r83b1b25d  
    5959  asr->mode_set = mode_set;
    6060
     61#if defined(RTEMS_SMP)
    6162  if ( asr_handler == NULL ) {
    6263    Chain_Node *node;
    6364
    64     asr->signals_pending = 0;
     65    /*
     66     * In SMP configurations, signals may be sent on other processors
     67     * (interrupts or threads) in parallel.  This will cause an inter-processor
     68     * interrupt which may be blocked by the above interrupt disable.
     69     */
     70
    6571    node = &api->Signal_action.Node;
     72    _Assert( asr->signals_pending == 0 || !_Chain_Is_node_off_chain( node ) );
     73    _Assert( asr->signals_pending != 0 || _Chain_Is_node_off_chain( node ) );
    6674
    6775    if ( !_Chain_Is_node_off_chain( node ) ) {
     76      asr->signals_pending = 0;
    6877      _Chain_Extract_unprotected( node );
    6978      _Chain_Set_off_chain( node );
    7079    }
    7180  }
     81#else
     82  /*
     83   * In uniprocessor configurations, as soon as interrupts are disabled above
     84   * nobody can send signals to the executing thread.  So, pending signals at
     85   * this point cannot appear.
     86   */
     87  _Assert( asr->signals_pending == 0 );
     88  _Assert( _Chain_Is_node_off_chain( &api->Signal_action.Node ) );
     89#endif
    7290
    7391  _Thread_State_release( executing, &lock_context );
  • testsuites/validation/tc-signal-catch.c

    r9a13f37 r83b1b25d  
    5454
    5555#include <rtems.h>
     56#include <string.h>
     57#include <rtems/score/smpbarrier.h>
    5658
    5759#include <rtems/test.h>
     
    6769
    6870typedef enum {
     71  RtemsSignalReqCatch_Pre_Pending_Yes,
     72  RtemsSignalReqCatch_Pre_Pending_No,
     73  RtemsSignalReqCatch_Pre_Pending_NA
     74} RtemsSignalReqCatch_Pre_Pending;
     75
     76typedef enum {
    6977  RtemsSignalReqCatch_Pre_Handler_Invalid,
    7078  RtemsSignalReqCatch_Pre_Handler_Valid,
     
    137145 */
    138146typedef struct {
     147  rtems_id runner_id;
     148
     149  rtems_id worker_id;
     150
     151  uint32_t pending_signals;
     152
     153  SMP_barrier_Control barrier;
     154
     155  SMP_barrier_State runner_barrier_state;
     156
    139157  uint32_t default_handler_calls;
    140158
     
    156174   * @brief This member defines the pre-condition states for the next action.
    157175   */
    158   size_t pcs[ 5 ];
     176  size_t pcs[ 6 ];
    159177
    160178  /**
     
    168186  RtemsSignalReqCatch_Instance;
    169187
     188static const char * const RtemsSignalReqCatch_PreDesc_Pending[] = {
     189  "Yes",
     190  "No",
     191  "NA"
     192};
     193
    170194static const char * const RtemsSignalReqCatch_PreDesc_Handler[] = {
    171195  "Invalid",
     
    199223
    200224static const char * const * const RtemsSignalReqCatch_PreDesc[] = {
     225  RtemsSignalReqCatch_PreDesc_Pending,
    201226  RtemsSignalReqCatch_PreDesc_Handler,
    202227  RtemsSignalReqCatch_PreDesc_Preempt,
     
    216241  ++ctx->default_handler_calls;
    217242
    218   T_eq_u32( signal_set, 0xdeadbeef );
     243  if ( ctx->pending_signals != 0 && ctx->default_handler_calls == 1 ) {
     244    T_eq_u32( signal_set, 0x600df00d );
     245  } else {
     246    T_eq_u32( signal_set, 0xdeadbeef );
     247  }
    219248}
    220249
     
    234263  T_rsc_success( sc );
    235264
    236   T_eq_u32( signal_set, 0xdeadbeef );
     265  if ( ctx->pending_signals != 0 && ctx->handler_calls == 1 ) {
     266    T_eq_u32( signal_set, 0x600df00d );
     267  } else {
     268    T_eq_u32( signal_set, 0xdeadbeef );
     269  }
    237270}
    238271
     
    242275    T_ne_u32( ctx->handler_mode, 0xffffffff );
    243276    T_eq_u32( ctx->handler_mode & mask, mode );
     277  }
     278}
     279
     280static void Worker( rtems_task_argument arg )
     281{
     282  Context          *ctx;
     283  SMP_barrier_State barrier_state;
     284
     285  ctx = (Context *) arg;
     286  _SMP_barrier_State_initialize( &barrier_state );
     287
     288  while ( true ) {
     289    rtems_status_code sc;
     290
     291    _SMP_barrier_Wait( &ctx->barrier, &barrier_state, 2 );
     292
     293    sc = rtems_signal_send( ctx->runner_id, 0x600df00d );
     294    T_rsc_success( sc );
     295
     296    _SMP_barrier_Wait( &ctx->barrier, &barrier_state, 2 );
     297  }
     298}
     299
     300static void RtemsSignalReqCatch_Pre_Pending_Prepare(
     301  RtemsSignalReqCatch_Context    *ctx,
     302  RtemsSignalReqCatch_Pre_Pending state
     303)
     304{
     305  switch ( state ) {
     306    case RtemsSignalReqCatch_Pre_Pending_Yes: {
     307      /*
     308       * Where the system has more than one processor, when
     309       * rtems_signal_catch() is called, the calling task shall have pending
     310       * signals.
     311       */
     312      ctx->pending_signals = ( rtems_scheduler_get_processor_maximum() > 1 ) ? 1 : 0;
     313      break;
     314    }
     315
     316    case RtemsSignalReqCatch_Pre_Pending_No: {
     317      /*
     318       * When rtems_signal_catch() is called, the calling task shall have no
     319       * pending signals.
     320       */
     321      ctx->pending_signals = 0;
     322      break;
     323    }
     324
     325    case RtemsSignalReqCatch_Pre_Pending_NA:
     326      break;
    244327  }
    245328}
     
    467550      if ( ctx->catch_status == RTEMS_SUCCESSFUL ) {
    468551        T_eq_u32( ctx->default_handler_calls, 0 );
    469         T_eq_u32( ctx->handler_calls, 1 );
     552        T_eq_u32( ctx->handler_calls, 1 + ctx->pending_signals );
    470553        T_ne_u32( ctx->handler_mode, 0xffffffff );
    471554      } else {
    472         T_eq_u32( ctx->default_handler_calls, 1 );
     555        T_eq_u32( ctx->default_handler_calls, 1 + ctx->pending_signals );
    473556        T_eq_u32( ctx->handler_calls, 0 );
    474557        T_eq_u32( ctx->handler_mode, 0xffffffff );
     
    491574      } else {
    492575        T_rsc_success( ctx->send_status );
    493         T_eq_u32( ctx->default_handler_calls, 1 );
     576        T_eq_u32( ctx->default_handler_calls, 1 + ctx->pending_signals );
    494577        T_eq_u32( ctx->handler_calls, 0 );
    495578        T_eq_u32( ctx->handler_mode, 0xffffffff );
     
    628711}
    629712
     713static void RtemsSignalReqCatch_Setup( RtemsSignalReqCatch_Context *ctx )
     714{
     715  memset( ctx, 0, sizeof( *ctx ) );
     716  ctx->runner_id = rtems_task_self();
     717  _SMP_barrier_Control_initialize( &ctx->barrier );
     718  _SMP_barrier_State_initialize( &ctx->runner_barrier_state );
     719
     720  if ( rtems_scheduler_get_processor_maximum() > 1 ) {
     721    rtems_status_code sc;
     722    rtems_id          scheduler_id;
     723
     724    sc = rtems_task_create(
     725      rtems_build_name( 'W', 'O', 'R', 'K' ),
     726      1,
     727      RTEMS_MINIMUM_STACK_SIZE,
     728      RTEMS_DEFAULT_MODES,
     729      RTEMS_DEFAULT_ATTRIBUTES,
     730      &ctx->worker_id
     731    );
     732    T_assert_rsc_success( sc );
     733
     734    sc = rtems_scheduler_ident_by_processor( 1, &scheduler_id );
     735    T_assert_rsc_success( sc );
     736
     737    sc = rtems_task_set_scheduler( ctx->worker_id, scheduler_id, 1 );
     738    T_assert_rsc_success( sc );
     739
     740    sc = rtems_task_start(
     741      ctx->worker_id,
     742      Worker,
     743      (rtems_task_argument) ctx
     744    );
     745    T_assert_rsc_success( sc );
     746  }
     747}
     748
     749static void RtemsSignalReqCatch_Setup_Wrap( void *arg )
     750{
     751  RtemsSignalReqCatch_Context *ctx;
     752
     753  ctx = arg;
     754  ctx->in_action_loop = false;
     755  RtemsSignalReqCatch_Setup( ctx );
     756}
     757
    630758static void RtemsSignalReqCatch_Teardown( RtemsSignalReqCatch_Context *ctx )
    631759{
    632760  rtems_status_code sc;
     761
     762  if ( ctx->worker_id != 0 ) {
     763    sc = rtems_task_delete( ctx->worker_id );
     764    T_rsc_success( sc );
     765  }
    633766
    634767  sc = rtems_signal_catch( NULL, RTEMS_DEFAULT_MODES );
     
    659792
    660793static T_fixture RtemsSignalReqCatch_Fixture = {
    661   .setup = NULL,
     794  .setup = RtemsSignalReqCatch_Setup_Wrap,
    662795  .stop = NULL,
    663796  .teardown = RtemsSignalReqCatch_Teardown_Wrap,
     
    8911024    RtemsSignalReqCatch_Post_ASR_No,
    8921025    RtemsSignalReqCatch_Post_IntLvl_Positive
     1026  }, {
     1027    RtemsSignalReqCatch_Post_Status_Ok,
     1028    RtemsSignalReqCatch_Post_Send_NotDef,
     1029    RtemsSignalReqCatch_Post_Preempt_Yes,
     1030    RtemsSignalReqCatch_Post_Timeslice_Yes,
     1031    RtemsSignalReqCatch_Post_ASR_Yes,
     1032    RtemsSignalReqCatch_Post_IntLvl_Zero
     1033  }, {
     1034    RtemsSignalReqCatch_Post_Status_NotImplIntLvl,
     1035    RtemsSignalReqCatch_Post_Send_NotDef,
     1036    RtemsSignalReqCatch_Post_Preempt_Yes,
     1037    RtemsSignalReqCatch_Post_Timeslice_Yes,
     1038    RtemsSignalReqCatch_Post_ASR_Yes,
     1039    RtemsSignalReqCatch_Post_IntLvl_Positive
     1040  }, {
     1041    RtemsSignalReqCatch_Post_Status_Ok,
     1042    RtemsSignalReqCatch_Post_Send_NotDef,
     1043    RtemsSignalReqCatch_Post_Preempt_Yes,
     1044    RtemsSignalReqCatch_Post_Timeslice_Yes,
     1045    RtemsSignalReqCatch_Post_ASR_No,
     1046    RtemsSignalReqCatch_Post_IntLvl_Zero
     1047  }, {
     1048    RtemsSignalReqCatch_Post_Status_NotImplIntLvl,
     1049    RtemsSignalReqCatch_Post_Send_NotDef,
     1050    RtemsSignalReqCatch_Post_Preempt_Yes,
     1051    RtemsSignalReqCatch_Post_Timeslice_Yes,
     1052    RtemsSignalReqCatch_Post_ASR_No,
     1053    RtemsSignalReqCatch_Post_IntLvl_Positive
     1054  }, {
     1055    RtemsSignalReqCatch_Post_Status_Ok,
     1056    RtemsSignalReqCatch_Post_Send_NotDef,
     1057    RtemsSignalReqCatch_Post_Preempt_Yes,
     1058    RtemsSignalReqCatch_Post_Timeslice_No,
     1059    RtemsSignalReqCatch_Post_ASR_Yes,
     1060    RtemsSignalReqCatch_Post_IntLvl_Zero
     1061  }, {
     1062    RtemsSignalReqCatch_Post_Status_NotImplIntLvl,
     1063    RtemsSignalReqCatch_Post_Send_NotDef,
     1064    RtemsSignalReqCatch_Post_Preempt_Yes,
     1065    RtemsSignalReqCatch_Post_Timeslice_No,
     1066    RtemsSignalReqCatch_Post_ASR_Yes,
     1067    RtemsSignalReqCatch_Post_IntLvl_Positive
     1068  }, {
     1069    RtemsSignalReqCatch_Post_Status_Ok,
     1070    RtemsSignalReqCatch_Post_Send_NotDef,
     1071    RtemsSignalReqCatch_Post_Preempt_Yes,
     1072    RtemsSignalReqCatch_Post_Timeslice_No,
     1073    RtemsSignalReqCatch_Post_ASR_No,
     1074    RtemsSignalReqCatch_Post_IntLvl_Zero
     1075  }, {
     1076    RtemsSignalReqCatch_Post_Status_NotImplIntLvl,
     1077    RtemsSignalReqCatch_Post_Send_NotDef,
     1078    RtemsSignalReqCatch_Post_Preempt_Yes,
     1079    RtemsSignalReqCatch_Post_Timeslice_No,
     1080    RtemsSignalReqCatch_Post_ASR_No,
     1081    RtemsSignalReqCatch_Post_IntLvl_Positive
     1082  }, {
     1083    RtemsSignalReqCatch_Post_Status_NotImplNoPreempt,
     1084    RtemsSignalReqCatch_Post_Send_NotDef,
     1085    RtemsSignalReqCatch_Post_Preempt_No,
     1086    RtemsSignalReqCatch_Post_Timeslice_Yes,
     1087    RtemsSignalReqCatch_Post_ASR_Yes,
     1088    RtemsSignalReqCatch_Post_IntLvl_Zero
     1089  }, {
     1090    RtemsSignalReqCatch_Post_Status_NotImplIntLvl,
     1091    RtemsSignalReqCatch_Post_Send_NotDef,
     1092    RtemsSignalReqCatch_Post_Preempt_No,
     1093    RtemsSignalReqCatch_Post_Timeslice_Yes,
     1094    RtemsSignalReqCatch_Post_ASR_Yes,
     1095    RtemsSignalReqCatch_Post_IntLvl_Positive
     1096  }, {
     1097    RtemsSignalReqCatch_Post_Status_NotImplNoPreempt,
     1098    RtemsSignalReqCatch_Post_Send_NotDef,
     1099    RtemsSignalReqCatch_Post_Preempt_No,
     1100    RtemsSignalReqCatch_Post_Timeslice_Yes,
     1101    RtemsSignalReqCatch_Post_ASR_No,
     1102    RtemsSignalReqCatch_Post_IntLvl_Zero
     1103  }, {
     1104    RtemsSignalReqCatch_Post_Status_NotImplIntLvl,
     1105    RtemsSignalReqCatch_Post_Send_NotDef,
     1106    RtemsSignalReqCatch_Post_Preempt_No,
     1107    RtemsSignalReqCatch_Post_Timeslice_Yes,
     1108    RtemsSignalReqCatch_Post_ASR_No,
     1109    RtemsSignalReqCatch_Post_IntLvl_Positive
     1110  }, {
     1111    RtemsSignalReqCatch_Post_Status_NotImplNoPreempt,
     1112    RtemsSignalReqCatch_Post_Send_NotDef,
     1113    RtemsSignalReqCatch_Post_Preempt_No,
     1114    RtemsSignalReqCatch_Post_Timeslice_No,
     1115    RtemsSignalReqCatch_Post_ASR_Yes,
     1116    RtemsSignalReqCatch_Post_IntLvl_Zero
     1117  }, {
     1118    RtemsSignalReqCatch_Post_Status_NotImplIntLvl,
     1119    RtemsSignalReqCatch_Post_Send_NotDef,
     1120    RtemsSignalReqCatch_Post_Preempt_No,
     1121    RtemsSignalReqCatch_Post_Timeslice_No,
     1122    RtemsSignalReqCatch_Post_ASR_Yes,
     1123    RtemsSignalReqCatch_Post_IntLvl_Positive
     1124  }, {
     1125    RtemsSignalReqCatch_Post_Status_NotImplNoPreempt,
     1126    RtemsSignalReqCatch_Post_Send_NotDef,
     1127    RtemsSignalReqCatch_Post_Preempt_No,
     1128    RtemsSignalReqCatch_Post_Timeslice_No,
     1129    RtemsSignalReqCatch_Post_ASR_No,
     1130    RtemsSignalReqCatch_Post_IntLvl_Zero
     1131  }, {
     1132    RtemsSignalReqCatch_Post_Status_NotImplIntLvl,
     1133    RtemsSignalReqCatch_Post_Send_NotDef,
     1134    RtemsSignalReqCatch_Post_Preempt_No,
     1135    RtemsSignalReqCatch_Post_Timeslice_No,
     1136    RtemsSignalReqCatch_Post_ASR_No,
     1137    RtemsSignalReqCatch_Post_IntLvl_Positive
     1138  }, {
     1139    RtemsSignalReqCatch_Post_Status_Ok,
     1140    RtemsSignalReqCatch_Post_Send_New,
     1141    RtemsSignalReqCatch_Post_Preempt_Yes,
     1142    RtemsSignalReqCatch_Post_Timeslice_Yes,
     1143    RtemsSignalReqCatch_Post_ASR_Yes,
     1144    RtemsSignalReqCatch_Post_IntLvl_Zero
     1145  }, {
     1146    RtemsSignalReqCatch_Post_Status_NotImplIntLvl,
     1147    RtemsSignalReqCatch_Post_Send_New,
     1148    RtemsSignalReqCatch_Post_Preempt_Yes,
     1149    RtemsSignalReqCatch_Post_Timeslice_Yes,
     1150    RtemsSignalReqCatch_Post_ASR_Yes,
     1151    RtemsSignalReqCatch_Post_IntLvl_Positive
     1152  }, {
     1153    RtemsSignalReqCatch_Post_Status_Ok,
     1154    RtemsSignalReqCatch_Post_Send_New,
     1155    RtemsSignalReqCatch_Post_Preempt_Yes,
     1156    RtemsSignalReqCatch_Post_Timeslice_Yes,
     1157    RtemsSignalReqCatch_Post_ASR_No,
     1158    RtemsSignalReqCatch_Post_IntLvl_Zero
     1159  }, {
     1160    RtemsSignalReqCatch_Post_Status_NotImplIntLvl,
     1161    RtemsSignalReqCatch_Post_Send_New,
     1162    RtemsSignalReqCatch_Post_Preempt_Yes,
     1163    RtemsSignalReqCatch_Post_Timeslice_Yes,
     1164    RtemsSignalReqCatch_Post_ASR_No,
     1165    RtemsSignalReqCatch_Post_IntLvl_Positive
     1166  }, {
     1167    RtemsSignalReqCatch_Post_Status_Ok,
     1168    RtemsSignalReqCatch_Post_Send_New,
     1169    RtemsSignalReqCatch_Post_Preempt_Yes,
     1170    RtemsSignalReqCatch_Post_Timeslice_No,
     1171    RtemsSignalReqCatch_Post_ASR_Yes,
     1172    RtemsSignalReqCatch_Post_IntLvl_Zero
     1173  }, {
     1174    RtemsSignalReqCatch_Post_Status_NotImplIntLvl,
     1175    RtemsSignalReqCatch_Post_Send_New,
     1176    RtemsSignalReqCatch_Post_Preempt_Yes,
     1177    RtemsSignalReqCatch_Post_Timeslice_No,
     1178    RtemsSignalReqCatch_Post_ASR_Yes,
     1179    RtemsSignalReqCatch_Post_IntLvl_Positive
     1180  }, {
     1181    RtemsSignalReqCatch_Post_Status_Ok,
     1182    RtemsSignalReqCatch_Post_Send_New,
     1183    RtemsSignalReqCatch_Post_Preempt_Yes,
     1184    RtemsSignalReqCatch_Post_Timeslice_No,
     1185    RtemsSignalReqCatch_Post_ASR_No,
     1186    RtemsSignalReqCatch_Post_IntLvl_Zero
     1187  }, {
     1188    RtemsSignalReqCatch_Post_Status_NotImplIntLvl,
     1189    RtemsSignalReqCatch_Post_Send_New,
     1190    RtemsSignalReqCatch_Post_Preempt_Yes,
     1191    RtemsSignalReqCatch_Post_Timeslice_No,
     1192    RtemsSignalReqCatch_Post_ASR_No,
     1193    RtemsSignalReqCatch_Post_IntLvl_Positive
     1194  }, {
     1195    RtemsSignalReqCatch_Post_Status_NotImplNoPreempt,
     1196    RtemsSignalReqCatch_Post_Send_New,
     1197    RtemsSignalReqCatch_Post_Preempt_No,
     1198    RtemsSignalReqCatch_Post_Timeslice_Yes,
     1199    RtemsSignalReqCatch_Post_ASR_Yes,
     1200    RtemsSignalReqCatch_Post_IntLvl_Zero
     1201  }, {
     1202    RtemsSignalReqCatch_Post_Status_NotImplIntLvl,
     1203    RtemsSignalReqCatch_Post_Send_New,
     1204    RtemsSignalReqCatch_Post_Preempt_No,
     1205    RtemsSignalReqCatch_Post_Timeslice_Yes,
     1206    RtemsSignalReqCatch_Post_ASR_Yes,
     1207    RtemsSignalReqCatch_Post_IntLvl_Positive
     1208  }, {
     1209    RtemsSignalReqCatch_Post_Status_NotImplNoPreempt,
     1210    RtemsSignalReqCatch_Post_Send_New,
     1211    RtemsSignalReqCatch_Post_Preempt_No,
     1212    RtemsSignalReqCatch_Post_Timeslice_Yes,
     1213    RtemsSignalReqCatch_Post_ASR_No,
     1214    RtemsSignalReqCatch_Post_IntLvl_Zero
     1215  }, {
     1216    RtemsSignalReqCatch_Post_Status_NotImplIntLvl,
     1217    RtemsSignalReqCatch_Post_Send_New,
     1218    RtemsSignalReqCatch_Post_Preempt_No,
     1219    RtemsSignalReqCatch_Post_Timeslice_Yes,
     1220    RtemsSignalReqCatch_Post_ASR_No,
     1221    RtemsSignalReqCatch_Post_IntLvl_Positive
     1222  }, {
     1223    RtemsSignalReqCatch_Post_Status_NotImplNoPreempt,
     1224    RtemsSignalReqCatch_Post_Send_New,
     1225    RtemsSignalReqCatch_Post_Preempt_No,
     1226    RtemsSignalReqCatch_Post_Timeslice_No,
     1227    RtemsSignalReqCatch_Post_ASR_Yes,
     1228    RtemsSignalReqCatch_Post_IntLvl_Zero
     1229  }, {
     1230    RtemsSignalReqCatch_Post_Status_NotImplIntLvl,
     1231    RtemsSignalReqCatch_Post_Send_New,
     1232    RtemsSignalReqCatch_Post_Preempt_No,
     1233    RtemsSignalReqCatch_Post_Timeslice_No,
     1234    RtemsSignalReqCatch_Post_ASR_Yes,
     1235    RtemsSignalReqCatch_Post_IntLvl_Positive
     1236  }, {
     1237    RtemsSignalReqCatch_Post_Status_NotImplNoPreempt,
     1238    RtemsSignalReqCatch_Post_Send_New,
     1239    RtemsSignalReqCatch_Post_Preempt_No,
     1240    RtemsSignalReqCatch_Post_Timeslice_No,
     1241    RtemsSignalReqCatch_Post_ASR_No,
     1242    RtemsSignalReqCatch_Post_IntLvl_Zero
     1243  }, {
     1244    RtemsSignalReqCatch_Post_Status_NotImplIntLvl,
     1245    RtemsSignalReqCatch_Post_Send_New,
     1246    RtemsSignalReqCatch_Post_Preempt_No,
     1247    RtemsSignalReqCatch_Post_Timeslice_No,
     1248    RtemsSignalReqCatch_Post_ASR_No,
     1249    RtemsSignalReqCatch_Post_IntLvl_Positive
    8931250  }
    8941251};
     
    8961253static const struct {
    8971254  uint8_t Skip : 1;
     1255  uint8_t Pre_Pending_NA : 1;
    8981256  uint8_t Pre_Handler_NA : 1;
    8991257  uint8_t Pre_Preempt_NA : 1;
     
    9031261} RtemsSignalReqCatch_TransitionInfo[] = {
    9041262  {
    905     0, 0, 0, 0, 0, 0
    906   }, {
    907     0, 0, 0, 0, 0, 0
    908   }, {
    909     0, 0, 0, 0, 0, 0
    910   }, {
    911     0, 0, 0, 0, 0, 0
    912   }, {
    913     0, 0, 0, 0, 0, 0
    914   }, {
    915     0, 0, 0, 0, 0, 0
    916   }, {
    917     0, 0, 0, 0, 0, 0
    918   }, {
    919     0, 0, 0, 0, 0, 0
    920   }, {
    921     0, 0, 0, 0, 0, 0
    922   }, {
    923     0, 0, 0, 0, 0, 0
    924   }, {
    925     0, 0, 0, 0, 0, 0
    926   }, {
    927     0, 0, 0, 0, 0, 0
    928   }, {
    929     0, 0, 0, 0, 0, 0
    930   }, {
    931     0, 0, 0, 0, 0, 0
    932   }, {
    933     0, 0, 0, 0, 0, 0
    934   }, {
    935     0, 0, 0, 0, 0, 0
    936   }, {
    937     0, 0, 0, 0, 0, 0
    938   }, {
    939     0, 0, 0, 0, 0, 0
    940   }, {
    941     0, 0, 0, 0, 0, 0
    942   }, {
    943     0, 0, 0, 0, 0, 0
    944   }, {
    945     0, 0, 0, 0, 0, 0
    946   }, {
    947     0, 0, 0, 0, 0, 0
    948   }, {
    949     0, 0, 0, 0, 0, 0
    950   }, {
    951     0, 0, 0, 0, 0, 0
    952   }, {
    953     0, 0, 0, 0, 0, 0
    954   }, {
    955     0, 0, 0, 0, 0, 0
    956   }, {
    957     0, 0, 0, 0, 0, 0
    958   }, {
    959     0, 0, 0, 0, 0, 0
    960   }, {
    961     0, 0, 0, 0, 0, 0
    962   }, {
    963     0, 0, 0, 0, 0, 0
    964   }, {
    965     0, 0, 0, 0, 0, 0
    966   }, {
    967     0, 0, 0, 0, 0, 0
     1263    0, 0, 0, 0, 0, 0, 0
     1264  }, {
     1265    0, 0, 0, 0, 0, 0, 0
     1266  }, {
     1267    0, 0, 0, 0, 0, 0, 0
     1268  }, {
     1269    0, 0, 0, 0, 0, 0, 0
     1270  }, {
     1271    0, 0, 0, 0, 0, 0, 0
     1272  }, {
     1273    0, 0, 0, 0, 0, 0, 0
     1274  }, {
     1275    0, 0, 0, 0, 0, 0, 0
     1276  }, {
     1277    0, 0, 0, 0, 0, 0, 0
     1278  }, {
     1279    0, 0, 0, 0, 0, 0, 0
     1280  }, {
     1281    0, 0, 0, 0, 0, 0, 0
     1282  }, {
     1283    0, 0, 0, 0, 0, 0, 0
     1284  }, {
     1285    0, 0, 0, 0, 0, 0, 0
     1286  }, {
     1287    0, 0, 0, 0, 0, 0, 0
     1288  }, {
     1289    0, 0, 0, 0, 0, 0, 0
     1290  }, {
     1291    0, 0, 0, 0, 0, 0, 0
     1292  }, {
     1293    0, 0, 0, 0, 0, 0, 0
     1294  }, {
     1295    0, 0, 0, 0, 0, 0, 0
     1296  }, {
     1297    0, 0, 0, 0, 0, 0, 0
     1298  }, {
     1299    0, 0, 0, 0, 0, 0, 0
     1300  }, {
     1301    0, 0, 0, 0, 0, 0, 0
     1302  }, {
     1303    0, 0, 0, 0, 0, 0, 0
     1304  }, {
     1305    0, 0, 0, 0, 0, 0, 0
     1306  }, {
     1307    0, 0, 0, 0, 0, 0, 0
     1308  }, {
     1309    0, 0, 0, 0, 0, 0, 0
     1310  }, {
     1311    0, 0, 0, 0, 0, 0, 0
     1312  }, {
     1313    0, 0, 0, 0, 0, 0, 0
     1314  }, {
     1315    0, 0, 0, 0, 0, 0, 0
     1316  }, {
     1317    0, 0, 0, 0, 0, 0, 0
     1318  }, {
     1319    0, 0, 0, 0, 0, 0, 0
     1320  }, {
     1321    0, 0, 0, 0, 0, 0, 0
     1322  }, {
     1323    0, 0, 0, 0, 0, 0, 0
     1324  }, {
     1325    0, 0, 0, 0, 0, 0, 0
     1326  }, {
     1327    0, 0, 0, 0, 0, 0, 0
     1328  }, {
     1329    0, 0, 0, 0, 0, 0, 0
     1330  }, {
     1331    0, 0, 0, 0, 0, 0, 0
     1332  }, {
     1333    0, 0, 0, 0, 0, 0, 0
     1334  }, {
     1335    0, 0, 0, 0, 0, 0, 0
     1336  }, {
     1337    0, 0, 0, 0, 0, 0, 0
     1338  }, {
     1339    0, 0, 0, 0, 0, 0, 0
     1340  }, {
     1341    0, 0, 0, 0, 0, 0, 0
     1342  }, {
     1343    0, 0, 0, 0, 0, 0, 0
     1344  }, {
     1345    0, 0, 0, 0, 0, 0, 0
     1346  }, {
     1347    0, 0, 0, 0, 0, 0, 0
     1348  }, {
     1349    0, 0, 0, 0, 0, 0, 0
     1350  }, {
     1351    0, 0, 0, 0, 0, 0, 0
     1352  }, {
     1353    0, 0, 0, 0, 0, 0, 0
     1354  }, {
     1355    0, 0, 0, 0, 0, 0, 0
     1356  }, {
     1357    0, 0, 0, 0, 0, 0, 0
     1358  }, {
     1359    0, 0, 0, 0, 0, 0, 0
     1360  }, {
     1361    0, 0, 0, 0, 0, 0, 0
     1362  }, {
     1363    0, 0, 0, 0, 0, 0, 0
     1364  }, {
     1365    0, 0, 0, 0, 0, 0, 0
     1366  }, {
     1367    0, 0, 0, 0, 0, 0, 0
     1368  }, {
     1369    0, 0, 0, 0, 0, 0, 0
     1370  }, {
     1371    0, 0, 0, 0, 0, 0, 0
     1372  }, {
     1373    0, 0, 0, 0, 0, 0, 0
     1374  }, {
     1375    0, 0, 0, 0, 0, 0, 0
     1376  }, {
     1377    0, 0, 0, 0, 0, 0, 0
     1378  }, {
     1379    0, 0, 0, 0, 0, 0, 0
     1380  }, {
     1381    0, 0, 0, 0, 0, 0, 0
     1382  }, {
     1383    0, 0, 0, 0, 0, 0, 0
     1384  }, {
     1385    0, 0, 0, 0, 0, 0, 0
     1386  }, {
     1387    0, 0, 0, 0, 0, 0, 0
     1388  }, {
     1389    0, 0, 0, 0, 0, 0, 0
    9681390  }
    9691391};
     
    9891411  rtems_mode        mode;
    9901412
    991   ctx->catch_status = rtems_signal_catch( ctx->handler, ctx->mode );
     1413  if ( ctx->pending_signals != 0 ) {
     1414    rtems_interrupt_level level;
     1415
     1416    rtems_interrupt_local_disable(level);
     1417    _SMP_barrier_Wait( &ctx->barrier, &ctx->runner_barrier_state, 2 );
     1418    _SMP_barrier_Wait( &ctx->barrier, &ctx->runner_barrier_state, 2 );
     1419    ctx->catch_status = rtems_signal_catch( ctx->handler, ctx->mode );
     1420    rtems_interrupt_local_enable(level);
     1421  } else {
     1422    ctx->catch_status = rtems_signal_catch( ctx->handler, ctx->mode );
     1423  }
    9921424
    9931425  sc = rtems_task_mode( ctx->normal_mode, RTEMS_ALL_MODE_MASKS, &mode );
     
    10131445
    10141446  for (
    1015     ctx->pcs[ 0 ] = RtemsSignalReqCatch_Pre_Handler_Invalid;
    1016     ctx->pcs[ 0 ] < RtemsSignalReqCatch_Pre_Handler_NA;
     1447    ctx->pcs[ 0 ] = RtemsSignalReqCatch_Pre_Pending_Yes;
     1448    ctx->pcs[ 0 ] < RtemsSignalReqCatch_Pre_Pending_NA;
    10171449    ++ctx->pcs[ 0 ]
    10181450  ) {
    1019     if ( RtemsSignalReqCatch_TransitionInfo[ index ].Pre_Handler_NA ) {
    1020       ctx->pcs[ 0 ] = RtemsSignalReqCatch_Pre_Handler_NA;
    1021       index += ( RtemsSignalReqCatch_Pre_Handler_NA - 1 )
     1451    if ( RtemsSignalReqCatch_TransitionInfo[ index ].Pre_Pending_NA ) {
     1452      ctx->pcs[ 0 ] = RtemsSignalReqCatch_Pre_Pending_NA;
     1453      index += ( RtemsSignalReqCatch_Pre_Pending_NA - 1 )
     1454        * RtemsSignalReqCatch_Pre_Handler_NA
    10221455        * RtemsSignalReqCatch_Pre_Preempt_NA
    10231456        * RtemsSignalReqCatch_Pre_Timeslice_NA
     
    10271460
    10281461    for (
    1029       ctx->pcs[ 1 ] = RtemsSignalReqCatch_Pre_Preempt_Yes;
    1030       ctx->pcs[ 1 ] < RtemsSignalReqCatch_Pre_Preempt_NA;
     1462      ctx->pcs[ 1 ] = RtemsSignalReqCatch_Pre_Handler_Invalid;
     1463      ctx->pcs[ 1 ] < RtemsSignalReqCatch_Pre_Handler_NA;
    10311464      ++ctx->pcs[ 1 ]
    10321465    ) {
    1033       if ( RtemsSignalReqCatch_TransitionInfo[ index ].Pre_Preempt_NA ) {
    1034         ctx->pcs[ 1 ] = RtemsSignalReqCatch_Pre_Preempt_NA;
    1035         index += ( RtemsSignalReqCatch_Pre_Preempt_NA - 1 )
     1466      if ( RtemsSignalReqCatch_TransitionInfo[ index ].Pre_Handler_NA ) {
     1467        ctx->pcs[ 1 ] = RtemsSignalReqCatch_Pre_Handler_NA;
     1468        index += ( RtemsSignalReqCatch_Pre_Handler_NA - 1 )
     1469          * RtemsSignalReqCatch_Pre_Preempt_NA
    10361470          * RtemsSignalReqCatch_Pre_Timeslice_NA
    10371471          * RtemsSignalReqCatch_Pre_ASR_NA
     
    10401474
    10411475      for (
    1042         ctx->pcs[ 2 ] = RtemsSignalReqCatch_Pre_Timeslice_Yes;
    1043         ctx->pcs[ 2 ] < RtemsSignalReqCatch_Pre_Timeslice_NA;
     1476        ctx->pcs[ 2 ] = RtemsSignalReqCatch_Pre_Preempt_Yes;
     1477        ctx->pcs[ 2 ] < RtemsSignalReqCatch_Pre_Preempt_NA;
    10441478        ++ctx->pcs[ 2 ]
    10451479      ) {
    1046         if ( RtemsSignalReqCatch_TransitionInfo[ index ].Pre_Timeslice_NA ) {
    1047           ctx->pcs[ 2 ] = RtemsSignalReqCatch_Pre_Timeslice_NA;
    1048           index += ( RtemsSignalReqCatch_Pre_Timeslice_NA - 1 )
     1480        if ( RtemsSignalReqCatch_TransitionInfo[ index ].Pre_Preempt_NA ) {
     1481          ctx->pcs[ 2 ] = RtemsSignalReqCatch_Pre_Preempt_NA;
     1482          index += ( RtemsSignalReqCatch_Pre_Preempt_NA - 1 )
     1483            * RtemsSignalReqCatch_Pre_Timeslice_NA
    10491484            * RtemsSignalReqCatch_Pre_ASR_NA
    10501485            * RtemsSignalReqCatch_Pre_IntLvl_NA;
     
    10521487
    10531488        for (
    1054           ctx->pcs[ 3 ] = RtemsSignalReqCatch_Pre_ASR_Yes;
    1055           ctx->pcs[ 3 ] < RtemsSignalReqCatch_Pre_ASR_NA;
     1489          ctx->pcs[ 3 ] = RtemsSignalReqCatch_Pre_Timeslice_Yes;
     1490          ctx->pcs[ 3 ] < RtemsSignalReqCatch_Pre_Timeslice_NA;
    10561491          ++ctx->pcs[ 3 ]
    10571492        ) {
    1058           if ( RtemsSignalReqCatch_TransitionInfo[ index ].Pre_ASR_NA ) {
    1059             ctx->pcs[ 3 ] = RtemsSignalReqCatch_Pre_ASR_NA;
    1060             index += ( RtemsSignalReqCatch_Pre_ASR_NA - 1 )
     1493          if ( RtemsSignalReqCatch_TransitionInfo[ index ].Pre_Timeslice_NA ) {
     1494            ctx->pcs[ 3 ] = RtemsSignalReqCatch_Pre_Timeslice_NA;
     1495            index += ( RtemsSignalReqCatch_Pre_Timeslice_NA - 1 )
     1496              * RtemsSignalReqCatch_Pre_ASR_NA
    10611497              * RtemsSignalReqCatch_Pre_IntLvl_NA;
    10621498          }
    10631499
    10641500          for (
    1065             ctx->pcs[ 4 ] = RtemsSignalReqCatch_Pre_IntLvl_Zero;
    1066             ctx->pcs[ 4 ] < RtemsSignalReqCatch_Pre_IntLvl_NA;
     1501            ctx->pcs[ 4 ] = RtemsSignalReqCatch_Pre_ASR_Yes;
     1502            ctx->pcs[ 4 ] < RtemsSignalReqCatch_Pre_ASR_NA;
    10671503            ++ctx->pcs[ 4 ]
    10681504          ) {
    1069             if ( RtemsSignalReqCatch_TransitionInfo[ index ].Pre_IntLvl_NA ) {
    1070               ctx->pcs[ 4 ] = RtemsSignalReqCatch_Pre_IntLvl_NA;
    1071               index += ( RtemsSignalReqCatch_Pre_IntLvl_NA - 1 );
     1505            if ( RtemsSignalReqCatch_TransitionInfo[ index ].Pre_ASR_NA ) {
     1506              ctx->pcs[ 4 ] = RtemsSignalReqCatch_Pre_ASR_NA;
     1507              index += ( RtemsSignalReqCatch_Pre_ASR_NA - 1 )
     1508                * RtemsSignalReqCatch_Pre_IntLvl_NA;
    10721509            }
    10731510
    1074             if ( RtemsSignalReqCatch_TransitionInfo[ index ].Skip ) {
     1511            for (
     1512              ctx->pcs[ 5 ] = RtemsSignalReqCatch_Pre_IntLvl_Zero;
     1513              ctx->pcs[ 5 ] < RtemsSignalReqCatch_Pre_IntLvl_NA;
     1514              ++ctx->pcs[ 5 ]
     1515            ) {
     1516              if ( RtemsSignalReqCatch_TransitionInfo[ index ].Pre_IntLvl_NA ) {
     1517                ctx->pcs[ 5 ] = RtemsSignalReqCatch_Pre_IntLvl_NA;
     1518                index += ( RtemsSignalReqCatch_Pre_IntLvl_NA - 1 );
     1519              }
     1520
     1521              if ( RtemsSignalReqCatch_TransitionInfo[ index ].Skip ) {
     1522                ++index;
     1523                continue;
     1524              }
     1525
     1526              RtemsSignalReqCatch_Prepare( ctx );
     1527              RtemsSignalReqCatch_Pre_Pending_Prepare( ctx, ctx->pcs[ 0 ] );
     1528              RtemsSignalReqCatch_Pre_Handler_Prepare( ctx, ctx->pcs[ 1 ] );
     1529              RtemsSignalReqCatch_Pre_Preempt_Prepare( ctx, ctx->pcs[ 2 ] );
     1530              RtemsSignalReqCatch_Pre_Timeslice_Prepare( ctx, ctx->pcs[ 3 ] );
     1531              RtemsSignalReqCatch_Pre_ASR_Prepare( ctx, ctx->pcs[ 4 ] );
     1532              RtemsSignalReqCatch_Pre_IntLvl_Prepare( ctx, ctx->pcs[ 5 ] );
     1533              RtemsSignalReqCatch_Action( ctx );
     1534              RtemsSignalReqCatch_Post_Status_Check(
     1535                ctx,
     1536                RtemsSignalReqCatch_TransitionMap[ index ][ 0 ]
     1537              );
     1538              RtemsSignalReqCatch_Post_Send_Check(
     1539                ctx,
     1540                RtemsSignalReqCatch_TransitionMap[ index ][ 1 ]
     1541              );
     1542              RtemsSignalReqCatch_Post_Preempt_Check(
     1543                ctx,
     1544                RtemsSignalReqCatch_TransitionMap[ index ][ 2 ]
     1545              );
     1546              RtemsSignalReqCatch_Post_Timeslice_Check(
     1547                ctx,
     1548                RtemsSignalReqCatch_TransitionMap[ index ][ 3 ]
     1549              );
     1550              RtemsSignalReqCatch_Post_ASR_Check(
     1551                ctx,
     1552                RtemsSignalReqCatch_TransitionMap[ index ][ 4 ]
     1553              );
     1554              RtemsSignalReqCatch_Post_IntLvl_Check(
     1555                ctx,
     1556                RtemsSignalReqCatch_TransitionMap[ index ][ 5 ]
     1557              );
    10751558              ++index;
    1076               continue;
    10771559            }
    1078 
    1079             RtemsSignalReqCatch_Prepare( ctx );
    1080             RtemsSignalReqCatch_Pre_Handler_Prepare( ctx, ctx->pcs[ 0 ] );
    1081             RtemsSignalReqCatch_Pre_Preempt_Prepare( ctx, ctx->pcs[ 1 ] );
    1082             RtemsSignalReqCatch_Pre_Timeslice_Prepare( ctx, ctx->pcs[ 2 ] );
    1083             RtemsSignalReqCatch_Pre_ASR_Prepare( ctx, ctx->pcs[ 3 ] );
    1084             RtemsSignalReqCatch_Pre_IntLvl_Prepare( ctx, ctx->pcs[ 4 ] );
    1085             RtemsSignalReqCatch_Action( ctx );
    1086             RtemsSignalReqCatch_Post_Status_Check(
    1087               ctx,
    1088               RtemsSignalReqCatch_TransitionMap[ index ][ 0 ]
    1089             );
    1090             RtemsSignalReqCatch_Post_Send_Check(
    1091               ctx,
    1092               RtemsSignalReqCatch_TransitionMap[ index ][ 1 ]
    1093             );
    1094             RtemsSignalReqCatch_Post_Preempt_Check(
    1095               ctx,
    1096               RtemsSignalReqCatch_TransitionMap[ index ][ 2 ]
    1097             );
    1098             RtemsSignalReqCatch_Post_Timeslice_Check(
    1099               ctx,
    1100               RtemsSignalReqCatch_TransitionMap[ index ][ 3 ]
    1101             );
    1102             RtemsSignalReqCatch_Post_ASR_Check(
    1103               ctx,
    1104               RtemsSignalReqCatch_TransitionMap[ index ][ 4 ]
    1105             );
    1106             RtemsSignalReqCatch_Post_IntLvl_Check(
    1107               ctx,
    1108               RtemsSignalReqCatch_TransitionMap[ index ][ 5 ]
    1109             );
    1110             ++index;
    11111560          }
    11121561        }
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