Index: c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_glue.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_glue.c	(revision 9ac98838d6b795fe8ec395cb385d9cca9cfc55b6)
+++ c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_glue.c	(revision 82bd8d9d6619d7fd1a9a96dd9aa9e4e0047a1f49)
@@ -20,5 +20,5 @@
 #include <rtems/error.h>
 #include <bsp.h>
-#include "../irq/irq.h"
+#include <bsp/irq.h>
 #include "../include/mpc5200.h"
 #include "include/ppctypes.h"			/* uint32, et. al.		   */
Index: c/src/lib/libbsp/powerpc/gen5200/bestcomm/load_task.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen5200/bestcomm/load_task.c	(revision 9ac98838d6b795fe8ec395cb385d9cca9cfc55b6)
+++ c/src/lib/libbsp/powerpc/gen5200/bestcomm/load_task.c	(revision 82bd8d9d6619d7fd1a9a96dd9aa9e4e0047a1f49)
@@ -40,5 +40,5 @@
 __declspec(section ".text") extern const uint32 offsetEntry;
 #else
-extern const uint32 taskTable;
+extern const uint32 taskTable [];
 extern const uint32 taskTableBytes;
 extern const uint32 taskTableTasks;
@@ -72,5 +72,5 @@
 
 	/* copy task table from source to destination */
-	memcpy((void *)((uint8 *)(sdma->taskBar) - MBarPhysOffsetGlobal), &taskTable, taskTableBytes);
+	memcpy((void *)((uint8 *)(sdma->taskBar) - MBarPhysOffsetGlobal), taskTable, taskTableBytes);
 	/* adjust addresses in task table */
 	for (i=0; i < (uint32) taskTableTasks; i++) {
Index: c/src/lib/libbsp/powerpc/gen5200/clock/clock.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen5200/clock/clock.c	(revision 9ac98838d6b795fe8ec395cb385d9cca9cfc55b6)
+++ c/src/lib/libbsp/powerpc/gen5200/clock/clock.c	(revision 82bd8d9d6619d7fd1a9a96dd9aa9e4e0047a1f49)
@@ -104,5 +104,5 @@
 #include <bsp.h>
 #include <rtems/bspIo.h>
-#include "../irq/irq.h"
+#include <bsp/irq.h>
 
 #include <rtems.h>
@@ -114,4 +114,6 @@
 
 #define GPT (BSP_PERIODIC_TIMER - BSP_SIU_IRQ_TMR0)
+
+extern uint32_t bsp_clicks_per_usec;
 
 /* this lets us do nanoseconds since last tick */
@@ -123,5 +125,5 @@
  *  ISR Handlers
  */
-void mpc5200_gpt_clock_isr(rtems_irq_hdl_param handle)
+void mpc5200_gpt_clock_isr(rtems_vector_number vector, void *handle)
 {
   uint32_t status;
@@ -219,42 +221,29 @@
 }
 
-void clockOn(const rtems_irq_connect_data* irq)
+void clockOn()
 {
   uint32_t gpt_no;
-  extern uint32_t bsp_clicks_per_usec;
-
-  gpt_no = BSP_SIU_IRQ_TMR0 - (irq->name);
+
+  gpt_no = BSP_SIU_IRQ_TMR0 - BSP_PERIODIC_TIMER;
 
   counter_value = rtems_configuration_get_microseconds_per_tick() *
                       bsp_clicks_per_usec;
 
-  mpc5200_set_gpt_count(counter_value, (uint32_t)gpt_no);
-  mpc5200_enable_gpt_int((uint32_t)gpt_no);
+  mpc5200_set_gpt_count(counter_value, gpt_no);
+  mpc5200_enable_gpt_int(gpt_no);
 
   ClockInitialized = 1;
 }
 
-void clockOff(const rtems_irq_connect_data* irq)
+void clockOff()
 {
   uint32_t gpt_no;
 
-  gpt_no = BSP_SIU_IRQ_TMR0 - (irq->name);
-
-  mpc5200_disable_gpt_int((uint32_t)gpt_no);
+  gpt_no = BSP_SIU_IRQ_TMR0 - BSP_PERIODIC_TIMER;
+
+  mpc5200_disable_gpt_int(gpt_no);
 
   ClockInitialized = 0;
 }
-
-int clockIsOn(const rtems_irq_connect_data* irq)
-{
-  uint32_t gpt_no;
-
-  gpt_no = BSP_SIU_IRQ_TMR0 - (irq->name);
-
-  if (mpc5200_check_gpt_status(gpt_no) && ClockInitialized)
-    return ClockInitialized;
-  return 0;
-}
-
 
 int BSP_get_clock_irq_level(void)
@@ -267,54 +256,49 @@
 }
 
-
-int BSP_disconnect_clock_handler (void)
-{
-  rtems_irq_connect_data clockIrqData;
-  clockIrqData.name   = BSP_PERIODIC_TIMER;
-
-
-  if (!BSP_get_current_rtems_irq_handler(&clockIrqData)) {
-    printk("Unable to stop system clock\n");
-    rtems_fatal_error_occurred(1);
-  }
-
-  return BSP_remove_rtems_irq_handler (&clockIrqData);
-}
-
-
-int BSP_connect_clock_handler (uint32_t gpt_no)
-{
-  rtems_irq_hdl hdl = 0;
-  rtems_irq_connect_data clockIrqData;
-
-  /*
-   * Reinit structure
-   */
-  clockIrqData.name   = BSP_PERIODIC_TIMER;
-
-  if (!BSP_get_current_rtems_irq_handler(&clockIrqData)) {
-    printk("Unable to get system clock handler\n");
-    rtems_fatal_error_occurred(1);
-  }
-
-  if (!BSP_remove_rtems_irq_handler (&clockIrqData)) {
-    printk("Unable to remove current system clock handler\n");
-    rtems_fatal_error_occurred(1);
-  }
-
-  if ((gpt_no >= GPT0) || (gpt_no <= GPT7)) {
-    hdl = (rtems_irq_hdl_param )&mpc5200.gpt[gpt_no];
-  } else {
+int BSP_disconnect_clock_handler (unsigned gpt_no)
+{
+  rtems_status_code sc = RTEMS_SUCCESSFUL;
+
+  if ((gpt_no < GPT0) || (gpt_no > GPT7)) {
+    return 0;
+  }
+
+  clockOff( BSP_PERIODIC_TIMER);
+
+  sc = rtems_interrupt_handler_remove(
+    BSP_PERIODIC_TIMER,
+    mpc5200_gpt_clock_isr,
+    &mpc5200.gpt [gpt_no]
+  );
+  if (sc != RTEMS_SUCCESSFUL) {
+    return 0;
+  }
+
+  return 1;
+}
+
+int BSP_connect_clock_handler (unsigned gpt_no)
+{
+  rtems_status_code sc = RTEMS_SUCCESSFUL;
+
+  if ((gpt_no < GPT0) || (gpt_no > GPT7)) {
     printk("Unable to set system clock handler\n");
     rtems_fatal_error_occurred(1);
   }
 
-  clockIrqData.hdl    = mpc5200_gpt_clock_isr;
-  clockIrqData.handle = (rtems_irq_hdl_param) hdl;
-  clockIrqData.on     = clockOn;
-  clockIrqData.off    = clockOff;
-  clockIrqData.isOn   = clockIsOn;
-
-  return BSP_install_rtems_irq_handler (&clockIrqData);
+  sc = rtems_interrupt_handler_install(
+    BSP_PERIODIC_TIMER,
+    "Clock",
+    RTEMS_INTERRUPT_UNIQUE,
+    mpc5200_gpt_clock_isr,
+    &mpc5200.gpt [gpt_no]
+  );
+  if (sc != RTEMS_SUCCESSFUL) {
+    return 0;
+  }
+
+  clockOn();
+
+  return 1;
 }
 
@@ -343,5 +327,4 @@
 #define Clock_driver_support_initialize_hardware() \
   do {        \
-    extern uint32_t bsp_clicks_per_usec; \
     counter_value = rtems_configuration_get_microseconds_per_tick() * \
                     bsp_clicks_per_usec; \
@@ -355,5 +338,5 @@
 #define Clock_driver_support_shutdown_hardware() \
   do { \
-    (void) BSP_disconnect_clock_handler (); \
+    (void) BSP_disconnect_clock_handler (GPT); \
   } while (0)
 
Index: c/src/lib/libbsp/powerpc/gen5200/console/console.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen5200/console/console.c	(revision 9ac98838d6b795fe8ec395cb385d9cca9cfc55b6)
+++ c/src/lib/libbsp/powerpc/gen5200/console/console.c	(revision 82bd8d9d6619d7fd1a9a96dd9aa9e4e0047a1f49)
@@ -99,5 +99,5 @@
 #include "../include/mpc5200.h"
 #include <bsp.h>
-#include "../irq/irq.h"
+#include <bsp/irq.h>
 
 #include <rtems/bspIo.h>
Index: c/src/lib/libbsp/powerpc/gen5200/i2c/mpc5200mbus.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen5200/i2c/mpc5200mbus.c	(revision 9ac98838d6b795fe8ec395cb385d9cca9cfc55b6)
+++ c/src/lib/libbsp/powerpc/gen5200/i2c/mpc5200mbus.c	(revision 82bd8d9d6619d7fd1a9a96dd9aa9e4e0047a1f49)
@@ -35,5 +35,5 @@
 #include "mpc5200mbus.h"
 #include "../include/mpc5200.h"
-#include "../irq/irq.h"
+#include <bsp/irq.h>
 #include "../include/i2c.h"
 
Index: c/src/lib/libbsp/powerpc/gen5200/ide/idecfg.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen5200/ide/idecfg.c	(revision 9ac98838d6b795fe8ec395cb385d9cca9cfc55b6)
+++ c/src/lib/libbsp/powerpc/gen5200/ide/idecfg.c	(revision 82bd8d9d6619d7fd1a9a96dd9aa9e4e0047a1f49)
@@ -19,5 +19,5 @@
 #include <rtems.h>
 #include <bsp.h>
-#include "../irq/irq.h"
+#include <bsp/irq.h>
 #include "../include/mpc5200.h"
 #include "./pcmcia_ide.h"
Index: c/src/lib/libbsp/powerpc/gen5200/ide/pcmcia_ide.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen5200/ide/pcmcia_ide.c	(revision 9ac98838d6b795fe8ec395cb385d9cca9cfc55b6)
+++ c/src/lib/libbsp/powerpc/gen5200/ide/pcmcia_ide.c	(revision 82bd8d9d6619d7fd1a9a96dd9aa9e4e0047a1f49)
@@ -79,5 +79,5 @@
 #include <rtems/error.h>
 #include <bsp.h>
-#include "../irq/irq.h"
+#include <bsp/irq.h>
 #include "../include/mpc5200.h"
 #include "./pcmcia_ide.h"
Index: c/src/lib/libbsp/powerpc/gen5200/include/bsp.h
===================================================================
--- c/src/lib/libbsp/powerpc/gen5200/include/bsp.h	(revision 9ac98838d6b795fe8ec395cb385d9cca9cfc55b6)
+++ c/src/lib/libbsp/powerpc/gen5200/include/bsp.h	(revision 82bd8d9d6619d7fd1a9a96dd9aa9e4e0047a1f49)
@@ -24,4 +24,42 @@
 #define __GEN5200_BSP_h
 
+#include <libcpu/powerpc-utility.h> 
+
+/*
+ * Some symbols defined in the linker command file.
+ */
+
+LINKER_SYMBOL(bsp_ram_start);
+LINKER_SYMBOL(bsp_ram_end);
+LINKER_SYMBOL(bsp_ram_size);
+
+LINKER_SYMBOL(bsp_rom_start);
+LINKER_SYMBOL(bsp_rom_end);
+LINKER_SYMBOL(bsp_rom_size);
+
+LINKER_SYMBOL(bsp_dpram_start);
+LINKER_SYMBOL(bsp_dpram_end);
+LINKER_SYMBOL(bsp_dpram_size);
+
+LINKER_SYMBOL(bsp_section_text_start);
+LINKER_SYMBOL(bsp_section_text_end);
+LINKER_SYMBOL(bsp_section_text_size);
+
+LINKER_SYMBOL(bsp_section_data_start);
+LINKER_SYMBOL(bsp_section_data_end);
+LINKER_SYMBOL(bsp_section_data_size);
+
+LINKER_SYMBOL(bsp_section_bss_start);
+LINKER_SYMBOL(bsp_section_bss_end);
+LINKER_SYMBOL(bsp_section_bss_size);
+
+LINKER_SYMBOL(bsp_interrupt_stack_start);
+LINKER_SYMBOL(bsp_interrupt_stack_end);
+LINKER_SYMBOL(bsp_interrupt_stack_size);
+
+LINKER_SYMBOL(bsp_work_area_start);
+
+LINKER_SYMBOL(MBAR);
+
 /*
  * distinguish board characteristics
@@ -57,25 +95,4 @@
 /* we have PSC1/2/3 */
 #define GEN5200_UART_AVAIL_MASK 0x07
-/*
- * address range definitions
- */
-/* ROM definitions (2 MB) */
-#define	ROM_START	0xFFE00000
-#define ROM_SIZE        0x00200000
-#define	ROM_END		(ROM_START+ROM_SIZE-1)
-#define	BOOT_START      ROM_START
-#define	BOOT_END        ROM_END
-
-/* SDRAM definitions (256 MB) */
-#define	RAM_START       0x00000000
-#define RAM_SIZE        0x10000000
-#define	RAM_END		(RAM_START+RAM_SIZE-1)
-
-/* DPRAM definitions (64 KB) */
-#define	DPRAM_START  0xFF000000
-#define	DPRAM_END    0xFF0003FF
-
-/* internal memory map definitions (64 KB) */
-#define	MBAR         0xF0000000
 
 /* we need the low level initialization in start.S*/
@@ -85,8 +102,4 @@
 #elif defined (PM520)
 
-/* 
- * MicroSys PM520 internal memory map definitions
- */
-#define	MBAR         0xF0000000
 #define HAS_UBOOT
 
@@ -107,6 +120,4 @@
 /* we only have PSC1 */
 #define GEN5200_UART_AVAIL_MASK 0x01
-
-#define	MBAR         0xF0000000
 
 /* We want to prompt for a reset and then reset the board */
@@ -270,4 +281,6 @@
 #endif
 
+void cpu_init(void);
+
 #ifdef __cplusplus
 }
Index: c/src/lib/libbsp/powerpc/gen5200/irq/irq.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen5200/irq/irq.c	(revision 9ac98838d6b795fe8ec395cb385d9cca9cfc55b6)
+++ c/src/lib/libbsp/powerpc/gen5200/irq/irq.c	(revision 82bd8d9d6619d7fd1a9a96dd9aa9e4e0047a1f49)
@@ -74,27 +74,15 @@
 /***********************************************************************/
 
+#include <rtems.h>
+
+#include <libcpu/powerpc-utility.h>
+#include <libcpu/raw_exception.h>
+
 #include <bsp.h>
-#include <rtems.h>
-#include "../irq/irq.h"
-#include <rtems/score/apiext.h>
-#include <rtems/bspIo.h>
-#include <libcpu/raw_exception.h>
-#include "../vectors/vectors.h"
-#include "../include/mpc5200.h"
-
-
-extern uint32_t irqMaskTable[];
-
-/*
- * default handler connected on each irq after bsp initialization
- */
-static rtems_irq_connect_data  default_rtems_entry;
-
-/*
- * location used to store initial tables used for interrupt
- * management.
- */
-static rtems_irq_global_settings*   internal_config;
-static rtems_irq_connect_data*      rtems_hdl_tbl;
+#include <bsp/irq.h>
+#include <bsp/vectors.h>
+#include <bsp/ppc_exc_bspsupp.h>
+#include <bsp/irq-generic.h>
+#include <bsp/mpc5200.h>
 
 /*
@@ -103,27 +91,51 @@
  *
  */
-const static unsigned int SIU_MaskBit[BSP_SIU_IRQ_NUMBER] =
-  {
-  0, 1, 2, 3,       /* smart_comm, psc1, psc2, psc3            */
-  4, 5, 6, 7,       /* irda/psc6, eth, usb, ata                */
-  8, 9, 10, 11,     /* pci_ctrl, pci_sc_rx, pci_sc_tx, psc4    */
-  12, 13, 14, 15,   /* psc5,spi_modf, spi_spif, i2c1           */
-  16, 17, 18, 19,   /* i2c, can1, can2, ir_rx                  */
-  20, 21, 15, 16,   /* ir_rx, xlb_arb, slice_tim2, irq1,       */
-  17, 18, 19, 20,   /* irq2, irq3, lo_int, rtc_pint            */
-  21, 22, 23, 24,   /* rtc_sint, gpio_std, gpio_wkup, tmr0     */
-  25, 26, 27, 28,   /* tmr1, tmr2, tmr3, tmr4                  */
-  29, 30, 31, 32,   /* tmr5, tmr6, tmr7, res                   */
-  32, 32, 32        /* res, res, res                           */
-  };
+const static unsigned int SIU_MaskBit [BSP_SIU_IRQ_NUMBER] = {
+  0, 1, 2, 3,                   /* smart_comm, psc1, psc2, psc3            */
+  4, 5, 6, 7,                   /* irda/psc6, eth, usb, ata                */
+  8, 9, 10, 11,                 /* pci_ctrl, pci_sc_rx, pci_sc_tx, psc4    */
+  12, 13, 14, 15,               /* psc5,spi_modf, spi_spif, i2c1           */
+  16, 17, 18, 19,               /* i2c, can1, can2, ir_rx                  */
+  20, 21, 15, 16,               /* ir_rx, xlb_arb, slice_tim2, irq1,       */
+  17, 18, 19, 20,               /* irq2, irq3, lo_int, rtc_pint            */
+  21, 22, 23, 24,               /* rtc_sint, gpio_std, gpio_wkup, tmr0     */
+  25, 26, 27, 28,               /* tmr1, tmr2, tmr3, tmr4                  */
+  29, 30, 31, 32,               /* tmr5, tmr6, tmr7, res                   */
+  32, 32, 32                    /* res, res, res                           */
+};
+
+static unsigned char irqPrioTable [BSP_SIU_IRQ_NUMBER] = {
+/* per. int. priorities (0-7) / 4bit coding / msb is HI/LO selection               */
+/* msb = 0 -> non-critical per. int. is routed to main int. (LO_int)               */
+/* msb = 1 -> critical per. int. is routed to critical int. (HI_int)               */
+  0xF, 0, 0, 0,                 /* smart_comm (do not change!), psc1, psc2, psc3             */
+  0, 0, 0, 0,                   /* irda, eth, usb, ata                                       */
+  0, 0, 0, 0,                   /* pci_ctrl, pci_sc_rx, pci_sc_tx, res                       */
+  0, 0, 0, 0,                   /* res, spi_modf, spi_spif, i2c1                             */
+  0, 0, 0, 0,                   /* i2c, can1, can2, ir_rx                                    */
+  0, 0,                         /* ir_rx, xlb_arb                                            */
+/* main interrupt priorities (0-7) / 4bit coding / msb is INT/SMI selection        */
+/* msb = 0 -> main int. is routed to processor INT (low vector base 0x500 )        */
+/* msb = 1 -> main int. is routed to processor SMI (low vector base 0x1400 )       */
+  0, 0,                         /* slice_tim2, irq1                                          */
+  0, 0, 0, 0,                   /* irq2, irq3, lo_int, rtc_pint                              */
+  0, 0, 0, 0,                   /* rtc_sint, gpio_std, gpio_wkup, tmr0                       */
+  0, 0, 0, 0,                   /* tmr1, tmr2, tmr3, tmr4                                    */
+  0, 0, 0,                      /* tmr5, tmr6, tmr7                                          */
+  /* critical interrupt priorities (0-3) / 2bit coding / no special purpose of msb */
+  0,                            /* irq0                                                      */
+  0, 0, 0                       /* slice_tim1, hi_int, ccs_wkup                              */
+};
+
+static uint32_t irqMaskTable [BSP_PER_IRQ_NUMBER + BSP_MAIN_IRQ_NUMBER];
 
 /*
  * Check if symbolic IRQ name is a Processor IRQ
  */
-static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine)
-{
-
-  return (((int)irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) &
-          ((int)irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET));
+static inline bool is_processor_irq( rtems_vector_number irqLine)
+{
+
+  return ((irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET)
+    && (irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET));
 }
 
@@ -131,19 +143,16 @@
  * Check for SIU IRQ and return base index
  */
-static inline int is_siu_irq(const rtems_irq_symbolic_name irqLine)
-{
-
-  return (((int)irqLine <= BSP_SIU_IRQ_MAX_OFFSET) &&
-           ((int)irqLine >= BSP_SIU_IRQ_LOWEST_OFFSET));
-
-}
-
+static inline bool is_siu_irq( rtems_vector_number irqLine)
+{
+
+  return ((irqLine <= BSP_SIU_IRQ_MAX_OFFSET)
+    && (irqLine >= BSP_SIU_IRQ_LOWEST_OFFSET));
+}
 
 /*
  * Check for SIU IRQ and return base index
  */
-static inline int get_siu_irq_base_index(const rtems_irq_symbolic_name irqLine)
-{
-
+static inline int get_siu_irq_base_index( rtems_vector_number irqLine)
+{
   if (irqLine <= BSP_PER_IRQ_MAX_OFFSET)
     return BSP_PER_IRQ_LOWEST_OFFSET;
@@ -151,4 +160,5 @@
   if (irqLine <= BSP_MAIN_IRQ_MAX_OFFSET)
     return BSP_MAIN_IRQ_LOWEST_OFFSET;
+
   if (irqLine <= BSP_CRIT_IRQ_MAX_OFFSET)
     return BSP_CRIT_IRQ_LOWEST_OFFSET;
@@ -157,13 +167,15 @@
 }
 
-
 static inline void BSP_enable_per_irq_at_siu(
-  const rtems_irq_symbolic_name irqLine
+  rtems_vector_number irqLine
 )
 {
-  uint8_t lo_hi_ind = 0, prio_index_offset;
+  uint8_t lo_hi_ind = 0,
+    prio_index_offset;
   uint32_t *reg;
-  rtems_irq_prio *irqPrioTable = internal_config->irqPrioTbl;
-  volatile uint32_t per_pri_1,main_pri_1, crit_pri_main_mask, per_mask;
+  volatile uint32_t per_pri_1,
+    main_pri_1,
+    crit_pri_main_mask,
+    per_mask;
 
   /* calculate the index offset of priority value bit field */
@@ -171,8 +183,8 @@
 
   /* set interrupt priorities */
-  if (irqPrioTable[irqLine] <= 15) {
+  if (irqPrioTable [irqLine] <= 15) {
 
     /* set peripheral int priority */
-    reg = (uint32_t *)(&(mpc5200.per_pri_1));
+    reg = (uint32_t *) (&(mpc5200.per_pri_1));
 
     /* choose proper register */
@@ -180,12 +192,12 @@
 
     /* set priority as given in priority table */
-    *reg |= (irqPrioTable[irqLine] << (28 - (prio_index_offset<< 2)));
+    *reg |= (irqPrioTable [irqLine] << (28 - (prio_index_offset << 2)));
 
     /* test msb (hash-bit) and set LO_/HI_int indicator */
-    if ((lo_hi_ind = (irqPrioTable[irqLine] >> 3))) {
+    if ((lo_hi_ind = (irqPrioTable [irqLine] >> 3))) {
 
       /* set critical HI_int priority */
-      reg = (uint32_t *)(&(mpc5200.crit_pri_main_mask));
-      *reg |= (irqPrioTable[BSP_SIU_IRQ_HI_INT] << 26);
+      reg = (uint32_t *) (&(mpc5200.crit_pri_main_mask));
+      *reg |= (irqPrioTable [BSP_SIU_IRQ_HI_INT] << 26);
 
       /*
@@ -194,11 +206,11 @@
        * to core_int (bit 31 / CEb)
        */
-       mpc5200.ext_en_type |= 1;
+      mpc5200.ext_en_type |= 1;
 
     } else {
-      if (irqPrioTable[irqLine] <= 15) {
+      if (irqPrioTable [irqLine] <= 15) {
         /* set main LO_int priority */
-        reg = (uint32_t *)(&(mpc5200.main_pri_1));
-        *reg |= (irqPrioTable[BSP_SIU_IRQ_LO_INT] << 16);
+        reg = (uint32_t *) (&(mpc5200.main_pri_1));
+        *reg |= (irqPrioTable [BSP_SIU_IRQ_LO_INT] << 16);
       }
     }
@@ -208,22 +220,19 @@
   if (!lo_hi_ind) {
     mpc5200.crit_pri_main_mask &=
-      ~(0x80000000 >> SIU_MaskBit[BSP_SIU_IRQ_LO_INT]);
-  }
-
+      ~(0x80000000 >> SIU_MaskBit [BSP_SIU_IRQ_LO_INT]);
+  }
 
   /* enable (unmask) peripheral interrupt */
-  mpc5200.per_mask &= ~(0x80000000 >> SIU_MaskBit[irqLine]);
-
-  main_pri_1         = mpc5200.main_pri_1;
+  mpc5200.per_mask &= ~(0x80000000 >> SIU_MaskBit [irqLine]);
+
+  main_pri_1 = mpc5200.main_pri_1;
   crit_pri_main_mask = mpc5200.crit_pri_main_mask;
-  per_pri_1          = mpc5200.per_pri_1;
-  per_mask           = mpc5200.per_mask;
-
-
-}
-
+  per_pri_1 = mpc5200.per_pri_1;
+  per_mask = mpc5200.per_mask;
+
+}
 
 static inline void BSP_enable_main_irq_at_siu(
-  const rtems_irq_symbolic_name irqLine
+  rtems_vector_number irqLine
 )
 {
@@ -231,5 +240,4 @@
   uint8_t prio_index_offset;
   uint32_t *reg;
-  rtems_irq_prio *irqPrioTable = internal_config->irqPrioTbl;
 
   /* calculate the index offset of priority value bit field */
@@ -237,8 +245,8 @@
 
   /* set main interrupt priority */
-  if (irqPrioTable[irqLine] <= 15) {
+  if (irqPrioTable [irqLine] <= 15) {
 
     /* set main int priority */
-    reg = (uint32_t *)(&(mpc5200.main_pri_1));
+    reg = (uint32_t *) (&(mpc5200.main_pri_1));
 
     /* choose proper register */
@@ -246,5 +254,5 @@
 
     /* set priority as given in priority table */
-    *reg |= (irqPrioTable[irqLine] << (28 - (prio_index_offset << 2)));
+    *reg |= (irqPrioTable [irqLine] << (28 - (prio_index_offset << 2)));
 
     if ((irqLine >= BSP_SIU_IRQ_IRQ1) && (irqLine <= BSP_SIU_IRQ_IRQ3)) {
@@ -255,16 +263,14 @@
 
   /* enable (unmask) main interrupt */
-  mpc5200.crit_pri_main_mask &= ~(0x80000000 >> SIU_MaskBit[irqLine]);
-
-}
-
+  mpc5200.crit_pri_main_mask &= ~(0x80000000 >> SIU_MaskBit [irqLine]);
+
+}
 
 static inline void BSP_enable_crit_irq_at_siu(
-  const rtems_irq_symbolic_name irqLine
+  rtems_vector_number irqLine
 )
 {
   uint8_t prio_index_offset;
   uint32_t *reg;
-  rtems_irq_prio *irqPrioTable = internal_config->irqPrioTbl;
 
   prio_index_offset = irqLine - BSP_CRIT_IRQ_LOWEST_OFFSET;
@@ -277,13 +283,12 @@
   mpc5200.ext_en_type |= 1;
 
-
   /* set critical interrupt priorities */
-  if (irqPrioTable[irqLine] <= 3) {
+  if (irqPrioTable [irqLine] <= 3) {
 
     /* choose proper register */
-    reg = (uint32_t *)(&(mpc5200.crit_pri_main_mask));
+    reg = (uint32_t *) (&(mpc5200.crit_pri_main_mask));
 
     /* set priority as given in priority table */
-    *reg |= (irqPrioTable[irqLine] << (30 - (prio_index_offset << 1)));
+    *reg |= (irqPrioTable [irqLine] << (30 - (prio_index_offset << 1)));
 
     /* external irq0-pin */
@@ -295,7 +300,6 @@
 }
 
-
 static inline void BSP_disable_per_irq_at_siu(
-  const rtems_irq_symbolic_name irqLine
+  rtems_vector_number irqLine
 )
 {
@@ -307,15 +311,14 @@
 
   /* disable (mask) peripheral interrupt */
-  mpc5200.per_mask |= (0x80000000 >> SIU_MaskBit[irqLine]);
+  mpc5200.per_mask |= (0x80000000 >> SIU_MaskBit [irqLine]);
 
   /* reset priority to lowest level (reset value) */
-  reg = (uint32_t *)(&(mpc5200.per_pri_1));
+  reg = (uint32_t *) (&(mpc5200.per_pri_1));
   reg += (irqLine >> 3);
   *reg &= ~(15 << (28 - (prio_index_offset << 2)));
 }
 
-
 static inline void BSP_disable_main_irq_at_siu(
-  const rtems_irq_symbolic_name irqLine
+  rtems_vector_number irqLine
 )
 {
@@ -327,5 +330,5 @@
 
   /* disable (mask) main interrupt */
-  mpc5200.crit_pri_main_mask |= (0x80000000 >> SIU_MaskBit[irqLine]);
+  mpc5200.crit_pri_main_mask |= (0x80000000 >> SIU_MaskBit [irqLine]);
 
   if ((irqLine >= BSP_SIU_IRQ_IRQ1) && (irqLine <= BSP_SIU_IRQ_IRQ3)) {
@@ -335,13 +338,11 @@
 
   /* reset priority to lowest level (reset value) */
-  reg = (uint32_t *)(&(mpc5200.main_pri_1));
-  reg  += (irqLine >> 3);
+  reg = (uint32_t *) (&(mpc5200.main_pri_1));
+  reg += (irqLine >> 3);
   *reg &= ~(15 << (28 - (prio_index_offset << 2)));
 }
 
-
-static inline void BSP_disable_crit_irq_at_siu(
-  const rtems_irq_symbolic_name irqLine
-)
+static inline void BSP_disable_crit_irq_at_siu( rtems_vector_number
+                                               irqLine)
 {
   uint8_t prio_index_offset;
@@ -351,5 +352,5 @@
 
   /* reset critical int priority to lowest level (reset value) */
-  reg = (uint32_t *)(&(mpc5200.crit_pri_main_mask));
+  reg = (uint32_t *) (&(mpc5200.crit_pri_main_mask));
   *reg &= ~(3 << (30 - (prio_index_offset << 1)));
 
@@ -360,49 +361,36 @@
 }
 
-
 /*
- * ------------------------ RTEMS Irq helper functions ----------------
+ * This function enables a given siu interrupt
  */
-
-
-/*
- * This function check that the value given for the irq line
- * is valid.
- */
-static int isValidInterrupt(int irq)
-{
-  if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET) )
-    return 0;
-  return 1;
-}
-
-
- /*
-  * This function enables a given siu interrupt
-  */
-int BSP_irq_enable_at_siu(const rtems_irq_symbolic_name irqLine)
-{
-  int base_index;
-
-  if (is_siu_irq(irqLine)) {
-    if ((base_index = get_siu_irq_base_index(irqLine)) != -1) {
-
-      switch(base_index) {
-        case BSP_PER_IRQ_LOWEST_OFFSET:
-          BSP_enable_per_irq_at_siu(irqLine);
-          break;
-        case BSP_MAIN_IRQ_LOWEST_OFFSET:
-          BSP_enable_main_irq_at_siu(irqLine);
-          break;
-        case BSP_CRIT_IRQ_LOWEST_OFFSET:
-          BSP_enable_crit_irq_at_siu(irqLine);
-          break;
-        default:
-          printk("No valid base index\n");
-          break;
-      }
+rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number irqLine)
+{
+  int base_index = get_siu_irq_base_index( irqLine);
+
+  if (is_siu_irq( irqLine)) {
+    rtems_interrupt_level level;
+
+    rtems_interrupt_disable( level);
+
+    switch (base_index) {
+      case BSP_PER_IRQ_LOWEST_OFFSET:
+        BSP_enable_per_irq_at_siu( irqLine);
+        break;
+      case BSP_MAIN_IRQ_LOWEST_OFFSET:
+        BSP_enable_main_irq_at_siu( irqLine);
+        break;
+      case BSP_CRIT_IRQ_LOWEST_OFFSET:
+        BSP_enable_crit_irq_at_siu( irqLine);
+        break;
+      default:
+        rtems_interrupt_enable( level);
+        printk( "No valid base index\n");
+        return RTEMS_INVALID_NUMBER;
     }
-  }
-  return 0;
+
+    rtems_interrupt_enable( level);
+  }
+
+  return RTEMS_SUCCESSFUL;
 }
 
@@ -410,231 +398,40 @@
  * This function disables a given siu interrupt
  */
-int BSP_irq_disable_at_siu(const rtems_irq_symbolic_name irqLine)
-{
-  int base_index;
-
-  if ( (base_index = get_siu_irq_base_index(irqLine)) == -1)
-    return 1;
-
-  switch(base_index) {
-    case BSP_PER_IRQ_LOWEST_OFFSET:
-      BSP_disable_per_irq_at_siu(irqLine);
-      break;
-    case BSP_MAIN_IRQ_LOWEST_OFFSET:
-      BSP_disable_main_irq_at_siu(irqLine);
-      break;
-    case BSP_CRIT_IRQ_LOWEST_OFFSET:
-      BSP_disable_crit_irq_at_siu(irqLine);
-      break;
-    default:
-      printk("No valid base index\n");
-      break;
-  }
-  return 0;
-}
-
-
-/*
- * --------------------- RTEMS Single Irq Handler Mngt Routines -------------
- */
-
- /*
-  * This function removes the default entry and installs a device
-  * interrupt handler
-  */
-int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
-{
-  rtems_interrupt_level level;
-
-  if (!isValidInterrupt(irq->name)) {
-    printk("not a valid interrupt\n");
-    return 0;
-  }
-
-  /*
-   * Check if default handler is actually connected. If not issue an error.
-   * RATIONALE : to always have the same transition by forcing the user
-   * to get the previous handler before accepting to disconnect.
-   */
-  if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) {
-    printk( "Default handler not there\n" );
-    return 0;
-  }
-
-  rtems_interrupt_disable(level);
-
-  /*
-   * store the data provided by user
-   */
-  rtems_hdl_tbl[irq->name] = *irq;
-
-  if (is_siu_irq(irq->name)) {
-    /*
-     * Enable interrupt at siu level
-     */
-    BSP_irq_enable_at_siu(irq->name);
-  } else {
-    if (is_processor_irq(irq->name)) {
-      /*
-       * Should Enable exception at processor level but not needed. 
-       * Will restore EE flags at the end of the routine anyway.
-       */
-    } else {
-      printk("not a valid interrupt\n");
-      return 0;
+rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number irqLine)
+{
+  int base_index = get_siu_irq_base_index( irqLine);
+
+  if (is_siu_irq( irqLine)) {
+    rtems_interrupt_level level;
+
+    rtems_interrupt_disable( level);
+
+    switch (base_index) {
+      case BSP_PER_IRQ_LOWEST_OFFSET:
+        BSP_disable_per_irq_at_siu( irqLine);
+        break;
+      case BSP_MAIN_IRQ_LOWEST_OFFSET:
+        BSP_disable_main_irq_at_siu( irqLine);
+        break;
+      case BSP_CRIT_IRQ_LOWEST_OFFSET:
+        BSP_disable_crit_irq_at_siu( irqLine);
+        break;
+      default:
+        rtems_interrupt_enable( level);
+        printk( "No valid base index\n");
+        return RTEMS_INVALID_NUMBER;
     }
-  }
-
-  /*
-   * Enable interrupt on device
-   */
-  if (irq->on)
-    irq->on(irq);
-
-  rtems_interrupt_enable(level);
-  return 1;
-}
-
-
- /*
-  * This function procures the current interrupt handler
-  */
-int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq)
-{
-  if (!isValidInterrupt(irq->name)) {
-    return 0;
-  }
-  *irq = rtems_hdl_tbl[irq->name];
-  return 1;
-}
-
-
- /*
-  * This function removes a device interrupt handler and restores
-  * the default entry
-  */
-int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
-{
-  rtems_interrupt_level level;
-
-  if (!isValidInterrupt(irq->name)) { 
-    return 0;
-  }
-
-  /*
-   * Check if default handler is actually connected. If not issue an error.
-   * RATIONALE : to always have the same transition by forcing the user
-   * to get the previous handler before accepting to disconnect.
-   */
-  if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {
-    return 0;
-  }
-
-  rtems_interrupt_disable(level);
-
-  if (is_siu_irq(irq->name)) {
-    /*
-     * disable interrupt at PIC level
-     */
-    BSP_irq_disable_at_siu(irq->name);
-  }
-
-  if (is_processor_irq(irq->name)) {
-    /*
-     * disable exception at processor level
-     */
-  }
-
-  /*
-   * Disable interrupt on device
-   */
-  if (irq->off)
-    irq->off(irq);
-
-  /*
-   * restore the default irq value
-   */
-  rtems_hdl_tbl[irq->name] = default_rtems_entry;
-
-  rtems_interrupt_enable(level);
-
-  return 1;
-}
-
-
-/*
- * --------------------- RTEMS Global Irq Handler Mngt Routines -------------
- */
-
-/*
- * This function set up interrupt management dependent on the
- * given configuration
- */
-int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
-{
-  int                   i;
-  rtems_interrupt_level level;
-
-  /*
-   * Store various code accelerators
-   */
-  internal_config   = config;
-  default_rtems_entry   = config->defaultEntry;
-  rtems_hdl_tbl   = config->irqHdlTbl;
-
-  rtems_interrupt_disable(level);
-
-  /*
-   * start with SIU IRQs
-   */
-  for (i=BSP_SIU_IRQ_LOWEST_OFFSET;
-       i < BSP_SIU_IRQ_LOWEST_OFFSET + BSP_SIU_IRQ_NUMBER ;
-       i++) {
-
-    if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
-      BSP_irq_enable_at_siu(i);
-      if (rtems_hdl_tbl[i].on)
-	rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
-
-    } else {
-      if (rtems_hdl_tbl[i].off)
-	rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
-      BSP_irq_disable_at_siu(i);
-    }
-  }
-
-  /*
-   * finish with Processor exceptions handled like IRQs
-   */
-  for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET;
-       i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER;
-       i++) {
-
-    if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
-      if (rtems_hdl_tbl[i].on)
-	rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
-
-    } else {
-      if (rtems_hdl_tbl[i].off)
-	rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
-    }
-  }
-
-  rtems_interrupt_enable(level);
-  return 1;
-}
-
-
-int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config)
-{
-  *config = internal_config;
-  return 0;
+
+    rtems_interrupt_enable( level);
+  }
+
+  return RTEMS_SUCCESSFUL;
 }
 
 #if (BENCHMARK_IRQ_PROCESSING == 0)
-void BSP_IRQ_Benchmarking_Reset(void)
-{
-}
-void BSP_IRQ_Benchmarking_Report(void)
+void BSP_IRQ_Benchmarking_Reset( void)
+{
+}
+void BSP_IRQ_Benchmarking_Report( void)
 {
 }
@@ -645,43 +442,42 @@
 uint32_t BSP_ISR_Count;
 uint32_t BSP_Worst_ISR;
+
 #define BSP_COUNTED_IRQ 16
-uint32_t BSP_ISR_Count_Per[BSP_COUNTED_IRQ + 1];
-
-void BSP_IRQ_Benchmarking_Reset(void)
+uint32_t BSP_ISR_Count_Per [BSP_COUNTED_IRQ + 1];
+
+void BSP_IRQ_Benchmarking_Reset( void)
 {
   int i;
+
   BSP_Starting_TBR = PPC_Get_timebase_register();
   BSP_Total_in_ISR = 0;
   BSP_ISR_Count = 0;
   BSP_Worst_ISR = 0;
-  for ( i=0 ; i<BSP_COUNTED_IRQ ; i++ )
-    BSP_ISR_Count_Per[i] = 0;
-}
-
-static const char * u64tostring(
-  char *buffer,
-  uint64_t v
-)
-{
-  sprintf( buffer, "%lld cycles %lld usecs", v, (v / 33) );
+  for (i = 0; i < BSP_COUNTED_IRQ; i++)
+    BSP_ISR_Count_Per [i] = 0;
+}
+
+static const char *u64tostring( char *buffer, uint64_t v)
+{
+  sprintf( buffer, "%lld cycles %lld usecs", v, (v / 33));
   return buffer;
 }
 
-void BSP_IRQ_Benchmarking_Report(void)
+void BSP_IRQ_Benchmarking_Report( void)
 {
   uint64_t now;
-  char buffer[96];
+  char buffer [96];
   int i;
 
   now = PPC_Get_timebase_register();
-  printk( "Started at: %s\n", u64tostring(buffer, BSP_Starting_TBR) );
-  printk( "Current   : %s\n", u64tostring(buffer, now) );
-  printk( "System up : %s\n", u64tostring(buffer, now - BSP_Starting_TBR) );
-  printk( "ISRs      : %d\n", BSP_ISR_Count );
-  printk( "ISRs ran  : %s\n", u64tostring(buffer, BSP_Total_in_ISR) );
-  printk( "Worst ISR : %s\n", u64tostring(buffer, BSP_Worst_ISR) );
-  for ( i=0 ; i<BSP_COUNTED_IRQ ; i++ )
-    printk( "IRQ %d: %d\n", i, BSP_ISR_Count_Per[i] );
-  printk( "Ticks     : %d\n",  Clock_driver_ticks );
+  printk( "Started at: %s\n", u64tostring( buffer, BSP_Starting_TBR));
+  printk( "Current   : %s\n", u64tostring( buffer, now));
+  printk( "System up : %s\n", u64tostring( buffer, now - BSP_Starting_TBR));
+  printk( "ISRs      : %d\n", BSP_ISR_Count);
+  printk( "ISRs ran  : %s\n", u64tostring( buffer, BSP_Total_in_ISR));
+  printk( "Worst ISR : %s\n", u64tostring( buffer, BSP_Worst_ISR));
+  for (i = 0; i < BSP_COUNTED_IRQ; i++)
+    printk( "IRQ %d: %d\n", i, BSP_ISR_Count_Per [i]);
+  printk( "Ticks     : %d\n", Clock_driver_ticks);
 }
 #endif
@@ -690,18 +486,22 @@
  * High level IRQ handler called from shared_raw_irq_code_entry
  */
-int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
+int C_dispatch_irq_handler( CPU_Interrupt_frame * frame, unsigned int excNum)
 {
   register unsigned int irq;
-  register unsigned int msr;
-  register unsigned int new_msr;
   register unsigned int pmce;
-  register unsigned int crit_pri_main_mask, per_mask;
+  register unsigned int crit_pri_main_mask,
+    per_mask;
+
+  uint32_t msr;
+
 #if (BENCHMARK_IRQ_PROCESSING == 1)
-  uint64_t start, stop, thisTime;
+  uint64_t start,
+    stop,
+    thisTime;
 
   start = PPC_Get_timebase_register();
   BSP_ISR_Count++;
-  if ( excNum < BSP_COUNTED_IRQ )
-    BSP_ISR_Count_Per[excNum]++;
+  if (excNum < BSP_COUNTED_IRQ)
+    BSP_ISR_Count_Per [excNum]++;
   else
     printk( "not counting %d\n", excNum);
@@ -709,11 +509,11 @@
 
   switch (excNum) {
-    /*
-     * Handle decrementer interrupt
-     */
+      /*
+       * Handle decrementer interrupt
+       */
     case ASM_DEC_VECTOR:
 
-      /* call the module specific handler and pass the specific handler */
-      rtems_hdl_tbl[BSP_DECREMENTER].hdl(0);
+      /* Dispatch interrupt handlers */
+      bsp_interrupt_handler_dispatch( BSP_DECREMENTER);
 
       break;
@@ -722,23 +522,23 @@
 
       /* get the content of main interrupt status register */
-      pmce =  mpc5200.pmce;
+      pmce = mpc5200.pmce;
 
       /* main interrupts may be routed to SMI, see bit SMI/INT select
        * bit in main int. priorities
        */
-      while (CHK_MSE_STICKY(pmce)) {
+      while (CHK_MSE_STICKY( pmce)) {
 
         /* check for main interrupt sources (hirarchical order)
          * -> LO_int indicates peripheral sources
          */
-        if (CHK_MSE_STICKY(pmce)) {
+        if (CHK_MSE_STICKY( pmce)) {
           /* get source of main interrupt */
-	  irq = MSE_SOURCE(pmce);
-	  switch(irq) {
-
-            /* irq1-3, RTC, GPIO, TMR0-7 detected (attention:
-	     * slice timer 2 is always routed to SMI)
-	     */
-            case 0: /* slice timer 2 */
+          irq = MSE_SOURCE( pmce);
+          switch (irq) {
+
+              /* irq1-3, RTC, GPIO, TMR0-7 detected (attention:
+               * slice timer 2 is always routed to SMI)
+               */
+            case 0:            /* slice timer 2 */
             case 1:
             case 2:
@@ -758,29 +558,25 @@
 
               /* add proper offset for main interrupts in
-	       * the siu handler array
-	       */
-	      irq += BSP_MAIN_IRQ_LOWEST_OFFSET;
+               * the siu handler array
+               */
+              irq += BSP_MAIN_IRQ_LOWEST_OFFSET;
 
               /* save original mask and disable all lower
-	       * priorized main interrupts
-	       */
-	      crit_pri_main_mask =  mpc5200.crit_pri_main_mask;
-	      mpc5200.crit_pri_main_mask |= irqMaskTable[irq];
+               * priorized main interrupts
+               */
+              crit_pri_main_mask = mpc5200.crit_pri_main_mask;
+              mpc5200.crit_pri_main_mask |= irqMaskTable [irq];
 
 #if (ALLOW_IRQ_NESTING == 1)
               /* enable interrupt nesting */
-	      _CPU_MSR_GET(msr);
-	      new_msr = msr | MSR_EE;
-	      _CPU_MSR_SET(new_msr);
-#endif
-
-              /* call the module specific handler and pass the
-	       * specific handler
-	       */
-              rtems_hdl_tbl[irq].hdl(0);
+              msr = ppc_external_exceptions_enable();
+#endif
+
+              /* Dispatch interrupt handlers */
+              bsp_interrupt_handler_dispatch( irq);
 
 #if (ALLOW_IRQ_NESTING == 1)
               /* disable interrupt nesting */
-              _CPU_MSR_SET(msr);
+              ppc_external_exceptions_disable( msr);
 #endif
 
@@ -790,64 +586,60 @@
               break;
 
-            /* peripheral LO_int interrupt source detected */
+              /* peripheral LO_int interrupt source detected */
             case 4:
 
               /* check for valid peripheral interrupt source */
-	      if (CHK_PSE_STICKY(pmce)) {
+              if (CHK_PSE_STICKY( pmce)) {
                 /* get source of peripheral interrupt */
-		irq = PSE_SOURCE(pmce);
-
-		/* add proper offset for peripheral interrupts
-		 * in the siu handler array
-		 */
-		irq += BSP_PER_IRQ_LOWEST_OFFSET;
-
-		/* save original mask and disable all lower
-		 * priorized main interrupts
-		 */
-                per_mask =  mpc5200.per_mask;
-                mpc5200.per_mask |= irqMaskTable[irq];
+                irq = PSE_SOURCE( pmce);
+
+                /* add proper offset for peripheral interrupts
+                 * in the siu handler array
+                 */
+                irq += BSP_PER_IRQ_LOWEST_OFFSET;
+
+                /* save original mask and disable all lower
+                 * priorized main interrupts
+                 */
+                per_mask = mpc5200.per_mask;
+                mpc5200.per_mask |= irqMaskTable [irq];
 
 #if (ALLOW_IRQ_NESTING == 1)
                 /* enable interrupt nesting */
-		_CPU_MSR_GET(msr);
-		new_msr = msr | MSR_EE;
-		_CPU_MSR_SET(new_msr);
-#endif
-
-                /* call the module specific handler and pass
-		 * the specific handler
-		 */
-		rtems_hdl_tbl[irq].hdl(0);
+                msr = ppc_external_exceptions_enable();
+#endif
+
+                /* Dispatch interrupt handlers */
+                bsp_interrupt_handler_dispatch( irq);
 
 #if (ALLOW_IRQ_NESTING == 1)
-		/* disable interrupt nesting */
-		_CPU_MSR_SET(msr);
-#endif
-
-		/* restore original interrupt mask */
-		mpc5200.per_mask = per_mask;
-
-		/* force re-evaluation of peripheral interrupts */
-		CLR_PSE_STICKY(mpc5200.pmce);
-	      } else {
+                /* disable interrupt nesting */
+                ppc_external_exceptions_disable( msr);
+#endif
+
+                /* restore original interrupt mask */
+                mpc5200.per_mask = per_mask;
+
+                /* force re-evaluation of peripheral interrupts */
+                CLR_PSE_STICKY( mpc5200.pmce);
+              } else {
                 /* this case may not occur: no valid peripheral
-		 * interrupt source
-		 */
-		printk("No valid peripheral LO_int interrupt source\n");
-	      }
+                 * interrupt source
+                 */
+                printk( "No valid peripheral LO_int interrupt source\n");
+              }
               break;
               /* error: unknown interrupt source */
             default:
-              printk("Unknown peripheral LO_int interrupt source\n");
+              printk( "Unknown peripheral LO_int interrupt source\n");
               break;
           }
 
-	  /* force re-evaluation of main interrupts */
-          CLR_MSE_STICKY(mpc5200.pmce);
-	}
+          /* force re-evaluation of main interrupts */
+          CLR_MSE_STICKY( mpc5200.pmce);
+        }
 
         /* get the content of main interrupt status register */
-	pmce =  mpc5200.pmce;
+        pmce = mpc5200.pmce;
       }
       break;
@@ -855,20 +647,20 @@
     case ASM_EXT_VECTOR:
       /* get the content of main interrupt status register */
-      pmce =  mpc5200.pmce;
+      pmce = mpc5200.pmce;
 
       /* critical interrupts may be routed to the core_int
        * dependent on premature initialization, see bit 31 (CEbsH)
        */
-      while((CHK_CE_SHADOW(pmce) && CHK_CSE_STICKY(pmce)) ||
-             CHK_MSE_STICKY(pmce) || CHK_PSE_STICKY(pmce) ) {
+      while ((CHK_CE_SHADOW( pmce) && CHK_CSE_STICKY( pmce))
+             || CHK_MSE_STICKY( pmce) || CHK_PSE_STICKY( pmce)) {
 
         /* first: check for critical interrupt sources (hierarchical order)
-	 * -> HI_int indicates peripheral sources
-	 */
-        if (CHK_CE_SHADOW(pmce) && CHK_CSE_STICKY(pmce)) {
+         * -> HI_int indicates peripheral sources
+         */
+        if (CHK_CE_SHADOW( pmce) && CHK_CSE_STICKY( pmce)) {
           /* get source of critical interrupt */
-	  irq = CSE_SOURCE(pmce);
-	  switch(irq) {
-            /* irq0, slice timer 1 or ccs wakeup detected */
+          irq = CSE_SOURCE( pmce);
+          switch (irq) {
+              /* irq0, slice timer 1 or ccs wakeup detected */
             case 0:
             case 1:
@@ -876,18 +668,18 @@
 
               /* add proper offset for critical interrupts in the siu
-	       * handler array */
-	      irq += BSP_CRIT_IRQ_LOWEST_OFFSET;
-
-              /* call the module specific handler and pass the
-	       * specific handler */
-              rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle);
+               * handler array */
+              irq += BSP_CRIT_IRQ_LOWEST_OFFSET;
+
+              /* Dispatch interrupt handlers */
+              bsp_interrupt_handler_dispatch( irq);
+
               break;
 
-            /* peripheral HI_int interrupt source detected */
+              /* peripheral HI_int interrupt source detected */
             case 2:
               /* check for valid peripheral interrupt source */
-	      if (CHK_PSE_STICKY(pmce)) {
+              if (CHK_PSE_STICKY( pmce)) {
                 /* get source of peripheral interrupt */
-                irq = PSE_SOURCE(pmce);
+                irq = PSE_SOURCE( pmce);
 
                 /* add proper offset for peripheral interrupts in the
@@ -897,20 +689,18 @@
                 /* save original mask and disable all lower
                  * priorized main interrupts */
-                per_mask =  mpc5200.per_mask;
-                mpc5200.per_mask |= irqMaskTable[irq];
+                per_mask = mpc5200.per_mask;
+                mpc5200.per_mask |= irqMaskTable [irq];
 
 #if (ALLOW_IRQ_NESTING == 1)
                 /* enable interrupt nesting */
-                _CPU_MSR_GET(msr);
-                new_msr = msr | MSR_EE;
-                _CPU_MSR_SET(new_msr);
-#endif
-
-                /* call the module specific handler and pass the
-                 * specific handler */
-                rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle);
+                msr = ppc_external_exceptions_enable();
+#endif
+
+                /* Dispatch interrupt handlers */
+                bsp_interrupt_handler_dispatch( irq);
 
 #if (ALLOW_IRQ_NESTING == 1)
-                _CPU_MSR_SET(msr);
+                /* disable interrupt nesting */
+                ppc_external_exceptions_disable( msr);
 #endif
 
@@ -919,30 +709,30 @@
 
                 /* force re-evaluation of peripheral interrupts */
-                CLR_PSE_STICKY(mpc5200.pmce);
-	      } else {
-		/* this case may not occur: no valid peripheral
-		 * interrupt source */
-		printk("No valid peripheral HI_int interrupt source\n");
-	      }
-	      break;
+                CLR_PSE_STICKY( mpc5200.pmce);
+              } else {
+                /* this case may not occur: no valid peripheral
+                 * interrupt source */
+                printk( "No valid peripheral HI_int interrupt source\n");
+              }
+              break;
             default:
               /* error: unknown interrupt source */
-              printk("Unknown HI_int interrupt source\n");
+              printk( "Unknown HI_int interrupt source\n");
               break;
           }
           /* force re-evaluation of critical interrupts */
-          CLR_CSE_STICKY(mpc5200.pmce);
+          CLR_CSE_STICKY( mpc5200.pmce);
         }
 
         /* second: check for main interrupt sources (hierarchical order)
          * -> LO_int indicates peripheral sources */
-        if (CHK_MSE_STICKY(pmce)) {
+        if (CHK_MSE_STICKY( pmce)) {
           /* get source of main interrupt */
-          irq = MSE_SOURCE(pmce);
+          irq = MSE_SOURCE( pmce);
 
           switch (irq) {
 
-            /* irq1-3, RTC, GPIO, TMR0-7 detected (attention: slice timer
-             * 2 is always routed to SMI) */
+              /* irq1-3, RTC, GPIO, TMR0-7 detected (attention: slice timer
+               * 2 is always routed to SMI) */
             case 1:
             case 2:
@@ -961,124 +751,202 @@
             case 16:
               /* add proper offset for main interrupts in the siu
-	       * handler array */
+               * handler array */
               irq += BSP_MAIN_IRQ_LOWEST_OFFSET;
 
-	      /* save original mask and disable all lower priorized
-	       * main interrupts*/
-	      crit_pri_main_mask =  mpc5200.crit_pri_main_mask;
-	      mpc5200.crit_pri_main_mask |= irqMaskTable[irq];
+              /* save original mask and disable all lower priorized
+               * main interrupts*/
+              crit_pri_main_mask = mpc5200.crit_pri_main_mask;
+              mpc5200.crit_pri_main_mask |= irqMaskTable [irq];
 
 #if (ALLOW_IRQ_NESTING == 1)
-	      /* enable interrupt nesting */
-	      _CPU_MSR_GET(msr);
-	      new_msr = msr | MSR_EE;
-	      _CPU_MSR_SET(new_msr);
-#endif
-
-	      /* call the module specific handler and pass the specific
-	       * handler */
-	      rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle);
+              /* enable interrupt nesting */
+              msr = ppc_external_exceptions_enable();
+#endif
+
+              /* Dispatch interrupt handlers */
+              bsp_interrupt_handler_dispatch( irq);
 
 #if (ALLOW_IRQ_NESTING == 1)
-	      /* disable interrupt nesting */
-	      _CPU_MSR_SET(msr);
-#endif
-
-	      /* restore original interrupt mask */
-	      mpc5200.crit_pri_main_mask = crit_pri_main_mask;
-	      break;
-
-          /* peripheral LO_int interrupt source detected */
-	    case 4:
-	      /* check for valid peripheral interrupt source */
-	      if (CHK_PSE_STICKY(pmce)) {
-		/* get source of peripheral interrupt */
-		irq = PSE_SOURCE(pmce);
-
-		/* add proper offset for peripheral interrupts in the siu
-		 * handler array */
-		irq += BSP_PER_IRQ_LOWEST_OFFSET;
-
-		/* save original mask and disable all lower priorized main
-		 * interrupts */
-		per_mask =  mpc5200.per_mask;
-		mpc5200.per_mask |= irqMaskTable[irq];
+              /* disable interrupt nesting */
+              ppc_external_exceptions_disable( msr);
+#endif
+
+              /* restore original interrupt mask */
+              mpc5200.crit_pri_main_mask = crit_pri_main_mask;
+              break;
+
+              /* peripheral LO_int interrupt source detected */
+            case 4:
+              /* check for valid peripheral interrupt source */
+              if (CHK_PSE_STICKY( pmce)) {
+                /* get source of peripheral interrupt */
+                irq = PSE_SOURCE( pmce);
+
+                /* add proper offset for peripheral interrupts in the siu
+                 * handler array */
+                irq += BSP_PER_IRQ_LOWEST_OFFSET;
+
+                /* save original mask and disable all lower priorized main
+                 * interrupts */
+                per_mask = mpc5200.per_mask;
+                mpc5200.per_mask |= irqMaskTable [irq];
 
 #if (ALLOW_IRQ_NESTING == 1)
-		/* enable interrupt nesting */
-		_CPU_MSR_GET(msr);
-		new_msr = msr | MSR_EE;
-		_CPU_MSR_SET(new_msr);
-#endif
-
-		/* call the module specific handler and pass the
-		 * specific handler */
-		rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle);
+                /* enable interrupt nesting */
+                msr = ppc_external_exceptions_enable();
+#endif
+
+                /* Dispatch interrupt handlers */
+                bsp_interrupt_handler_dispatch( irq);
 
 #if (ALLOW_IRQ_NESTING == 1)
-		/* disable interrupt nesting */
-		_CPU_MSR_SET(msr);
-#endif
-
-		/* restore original interrupt mask */
-		mpc5200.per_mask = per_mask;
-
-		/* force re-evaluation of peripheral interrupts */
-		CLR_PSE_STICKY(mpc5200.pmce);
-	      } else {
-		/* this case may not occur: no valid peripheral
-		 * interrupt source */
-		printk("No valid peripheral LO_int interrupt source\n");
-	      }
+                /* disable interrupt nesting */
+                ppc_external_exceptions_disable( msr);
+#endif
+
+                /* restore original interrupt mask */
+                mpc5200.per_mask = per_mask;
+
+                /* force re-evaluation of peripheral interrupts */
+                CLR_PSE_STICKY( mpc5200.pmce);
+              } else {
+                /* this case may not occur: no valid peripheral
+                 * interrupt source */
+                printk( "No valid peripheral LO_int interrupt source\n");
+              }
               break;
 
-	    /* error: unknown interrupt source */
-	    default:
-	      printk("Unknown peripheral LO_int interrupt source\n");
-	      break;
+              /* error: unknown interrupt source */
+            default:
+              printk( "Unknown peripheral LO_int interrupt source\n");
+              break;
           }
-	  /* force re-evaluation of main interrupts */
-	  CLR_MSE_STICKY(mpc5200.pmce);
+          /* force re-evaluation of main interrupts */
+          CLR_MSE_STICKY( mpc5200.pmce);
         }
         /* get the content of main interrupt status register */
-        pmce =  mpc5200.pmce;
+        pmce = mpc5200.pmce;
       }
       break;
 
     default:
-      printk("Unknown processor exception\n");
+      printk( "Unknown processor exception\n");
       break;
 
-  } /* end of switch(excNum) */
+  }                             /* end of switch( excNum) */
+
 #if (BENCHMARK_IRQ_PROCESSING == 1)
   stop = PPC_Get_timebase_register();
   thisTime = stop - start;
   BSP_Total_in_ISR += thisTime;
-  if ( thisTime > BSP_Worst_ISR )
+  if (thisTime > BSP_Worst_ISR)
     BSP_Worst_ISR = thisTime;
 #endif
+
   return 0;
 }
 
-
-void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
-{
-  /*
-   * Process pending signals that have not already been
-   * processed by _Thread_Displatch. This happens quite
-   * unfrequently : the ISR must have posted an action
-   * to the current running thread.
-   */
-  if ( _Thread_Do_post_task_switch_extension ||
-       _Thread_Executing->do_post_task_switch_extension )
-    {
-
-    _Thread_Executing->do_post_task_switch_extension = FALSE;
-    _API_extensions_Run_postswitch();
-
+/*
+ * setup irqMaskTable to support a priorized/nested interrupt environment
+ */
+void setup_irqMaskTable( void)
+{
+  rtems_irq_prio prio = 0;
+  uint32_t i = 0,
+    j = 0,
+    mask = 0;
+
+  /* set up the priority dependent masks for peripheral interrupts */
+  for (i = BSP_PER_IRQ_LOWEST_OFFSET; i <= BSP_PER_IRQ_MAX_OFFSET; i++) {
+    prio = irqPrioTable [i];
+    mask = 0;
+
+    for (j = BSP_PER_IRQ_LOWEST_OFFSET; j <= BSP_PER_IRQ_MAX_OFFSET; j++) {
+      if (prio > irqPrioTable [j]) {
+        mask |= (1 << (31 - j + BSP_PER_IRQ_LOWEST_OFFSET));
+      }
+
+      if ((prio == irqPrioTable [j]) && (j >= i)) {
+        mask |= (1 << (31 - j + BSP_PER_IRQ_LOWEST_OFFSET));
+      }
     }
-  /*
-   * I plan to process other thread related events here.
-   * This will include DEBUG session requested from keyboard...
-   */
-}
+
+    irqMaskTable [i] = mask;
+  }
+
+  /* set up the priority dependent masks for main interrupts */
+  for (i = BSP_MAIN_IRQ_LOWEST_OFFSET; i <= BSP_MAIN_IRQ_MAX_OFFSET; i++) {
+    prio = irqPrioTable [i];
+    mask = 0;
+
+    for (j = BSP_MAIN_IRQ_LOWEST_OFFSET; j <= BSP_MAIN_IRQ_MAX_OFFSET; j++) {
+      if (prio > irqPrioTable [j]) {
+        mask |= (1 << (16 - j + BSP_MAIN_IRQ_LOWEST_OFFSET));
+      }
+
+      if ((prio == irqPrioTable [j]) && (j >= i)) {
+        mask |= (1 << (16 - j + BSP_MAIN_IRQ_LOWEST_OFFSET));
+      }
+    }
+
+    irqMaskTable [i] = mask;
+  }
+}
+
+/*
+ * Initialize MPC5x00 SIU interrupt management
+ */
+void BSP_SIU_irq_init( void)
+{
+
+  /* disable all peripheral interrupts */
+  mpc5200.per_mask = 0xFFFFFC00;
+
+  /* peripheral interrupt priorities according to reset value */
+  mpc5200.per_pri_1 = 0xF0000000;
+  mpc5200.per_pri_2 = 0x00000000;
+  mpc5200.per_pri_3 = 0x00000000;
+
+  /* disable external interrupts IRQ0-4 / critical interrupts are routed to core_int */
+  mpc5200.ext_en_type = 0x0F000001;
+
+  /* disable main interrupts / crit. int. priorities according to reset values */
+  mpc5200.crit_pri_main_mask = 0x0001FFFF;
+
+  /* main priorities according to reset value */
+  mpc5200.main_pri_1 = 0;
+  mpc5200.main_pri_2 = 0;
+
+  /* reset all status indicators */
+  mpc5200.csa = 0x0001FFFF;
+  mpc5200.msa = 0x0001FFFF;
+  mpc5200.psa = 0x003FFFFF;
+  mpc5200.psa_be = 0x03000000;
+
+  setup_irqMaskTable();
+}
+
+rtems_status_code bsp_interrupt_facility_initialize( void)
+{
+  BSP_SIU_irq_init();
+
+  /* Install exception handler */
+  if (ppc_exc_set_handler( ASM_EXT_VECTOR, C_dispatch_irq_handler)) {
+    return RTEMS_IO_ERROR;
+  }
+  if (ppc_exc_set_handler( ASM_DEC_VECTOR, C_dispatch_irq_handler)) {
+    return RTEMS_IO_ERROR;
+  }
+  if (ppc_exc_set_handler( ASM_E300_SYSMGMT_VECTOR, C_dispatch_irq_handler)) {
+    return RTEMS_IO_ERROR;
+  }
+
+  return RTEMS_SUCCESSFUL;
+}
+
+void bsp_interrupt_handler_default( rtems_vector_number vector)
+{
+  if (vector != BSP_DECREMENTER) {
+    printk( "Spurious interrupt: 0x%08x\n", vector);
+  }
+}
Index: c/src/lib/libbsp/powerpc/gen5200/network_5200/network.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen5200/network_5200/network.c	(revision 9ac98838d6b795fe8ec395cb385d9cca9cfc55b6)
+++ c/src/lib/libbsp/powerpc/gen5200/network_5200/network.c	(revision 82bd8d9d6619d7fd1a9a96dd9aa9e4e0047a1f49)
@@ -66,5 +66,5 @@
 #include <netinet/if_ether.h>
 #include <bsp.h>
-#include "../irq/irq.h"
+#include <bsp/irq.h>
 #include "../include/mpc5200.h"
 #include <net/if_var.h>
Index: c/src/lib/libbsp/powerpc/gen5200/slicetimer/slicetimer.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen5200/slicetimer/slicetimer.c	(revision 9ac98838d6b795fe8ec395cb385d9cca9cfc55b6)
+++ c/src/lib/libbsp/powerpc/gen5200/slicetimer/slicetimer.c	(revision 82bd8d9d6619d7fd1a9a96dd9aa9e4e0047a1f49)
@@ -100,5 +100,5 @@
 #include <bsp.h>
 #include <rtems/bspIo.h>
-#include "../irq/irq.h"
+#include <bsp/irq.h>
 
 #include <rtems.h>
@@ -106,5 +106,5 @@
 #include <rtems/libio.h>
 
-#include "../irq/irq.h"
+#include <bsp/irq.h>
 #include "../include/mpc5200.h"
 #include "../slicetimer/slicetimer.h"
Index: c/src/lib/libbsp/powerpc/gen5200/start/start.S
===================================================================
--- c/src/lib/libbsp/powerpc/gen5200/start/start.S	(revision 9ac98838d6b795fe8ec395cb385d9cca9cfc55b6)
+++ c/src/lib/libbsp/powerpc/gen5200/start/start.S	(revision 82bd8d9d6619d7fd1a9a96dd9aa9e4e0047a1f49)
@@ -91,54 +91,8 @@
 /***********************************************************************/
    
-#include <rtems/asm.h> 
 #include <rtems/powerpc/cache.h>
-#include <rtems/powerpc/registers.h>
-#include "../include/mpc5200.h"
-#include "../include/bsp.h"
-
-/* Macro definitions to load a register with a 32-bit address.
-   Both functions identically.  Sometimes one mnemonic is more
-   appropriate than the other.
-   reg 		-> register to load
-   value 	-> value to be loaded
-   LA  reg,value    ("Load Address")
-   LWI reg,value    ("Load Word Immediate") */
-
-.macro LA reg, value
-	lis \reg , \value@h
-	ori \reg , \reg, \value@l
-	sync
-.endm
-
-.macro LWI reg, value
-	lis \reg , (\value)@h
-	ori \reg , \reg, (\value)@l
-	sync
-.endm 
-
-/* Macro definitions to test, set or clear a single 
-   bit or bit pattern in a given 32bit GPR. 
-   reg1		-> register content to be tested
-   reg2		-> 2nd register only needed for computation
-   mask		-> any bit pattern */
-
-.macro	TSTBITS	reg1, reg2, mask	/* Match is indicated by EQ=0 (CR) */ 
-	LWI 	\reg2, \mask		/* Unmatch is indicated by EQ=1 (CR) */
-	and	\reg1, \reg1, \reg2
-	cmplw	\reg1, \reg2
-	sync
-.endm	
-	
-.macro 	SETBITS reg1, reg2, mask
-	LWI 	\reg2, \mask
-	or	\reg1, \reg1, \reg2 
-	sync
-.endm
-
-.macro 	CLRBITS reg1, reg2, mask
-	LWI 	\reg2, \mask
-	andc	\reg1, \reg1, \reg2
-	sync
-.endm
+
+#include <bsp.h>
+#include <bsp/mpc5200.h>
 
 /* Some register offsets of MPC5x00 memory map registers */
@@ -201,13 +155,5 @@
 .set	CFG_VAL,		0x00000100
 
-.extern	_bss_start
-.extern	_bss_size
-.extern	_data_start
-.extern	_data_size
-.extern	_text_start
-.extern	_text_size
-/*.extern _s_got*/
 .extern boot_card
-.extern MBAR   
 
 .section ".entry"  
@@ -263,5 +209,5 @@
 #if defined(NEED_LOW_LEVEL_INIT)
 /* detect RAM/ROM startup (common for RAM/ROM startup) */
-   	LWI     r20, ROM_START			/* set the relocation offset */
+   	LWI     r20, bsp_rom_start		/* set the relocation offset */
    	
    	
@@ -296,10 +242,9 @@
 
 	/* FIXME: map BOOT ROM into final location with CS0 registers */
-	LWI	r30, ROM_START
+	LWI	r30, bsp_rom_start
 	rlwinm	r30, r30,17,15,31
 	stw	r30, CS0STR(r31) 		/* Set CS0STR */	
 			
-	lis	r30, ROM_END@h
-	ori	r30, r30, ROM_END@l
+	LWI	r30, bsp_rom_end
 	
 	rlwinm	r30, r30,17,15,31
@@ -312,7 +257,7 @@
 	/* jump to same code in final BOOT ROM location */
 	LWI	r30, reloc_in_CS0
-	LWI	r29, RAM_START
+	LWI	r29, bsp_ram_start
 	sub	r30,r30,r29
-	LWI	r29, ROM_START
+	LWI	r29, bsp_rom_start
 	add	r30,r30,r29
 	mtctr	r30
@@ -326,10 +271,11 @@
 	
 	/* init SDRAM */
-	LWI	r30, RAM_START
-	ori	r30,r30,0x1a                    /* size code: bank is 128MByte */
-	stw	r30,SDRAMCS0(r31) 		/* Set SDRAMCS0 */
-
-	LWI	r30,(RAM_SIZE)>>1 
-	ori	r30,r30,0x1a                    /* size code: bank is 128MByte */
+	LWI	r30, bsp_ram_start
+	ori	r30, r30, 0x1a			/* size code: bank is 128MByte */
+	stw	r30, SDRAMCS0(r31) 		/* Set SDRAMCS0 */
+
+	LWI	r30, bsp_ram_size
+	srawi	r30, r30, 1
+	ori	r30, r30, 0x1a			/* size code: bank is 128MByte */
 	stw	r30, SDRAMCS1(r31) 		/* Set SDRAMCS1 */
 	
@@ -349,5 +295,5 @@
 	stw	r30, ARBSNOOP(r31) 		/* Set ARBSNOOP */	
 /* copy .text section from ROM to RAM location (unique for ROM startup) */
-	LA	r30, _text_start		/* get start address of text section in RAM */
+	LA	r30, bsp_section_text_start	/* get start address of text section in RAM */
 	
 	
@@ -355,8 +301,8 @@
 	
 	
-	LA	r29, _text_start		/* get start address of text section in RAM */
-	
-
-	LA	r28, _text_size          	/* get size of RAM image */
+	LA	r29, bsp_section_text_start	/* get start address of text section in RAM */
+	
+
+	LA	r28, bsp_section_text_size	/* get size of RAM image */
 		
 	
@@ -365,5 +311,5 @@
 
 /* copy .data section from ROM to RAM location (unique for ROM startup) */
-	LA	r30, _data_start		/* get start address of data section in RAM */
+	LA	r30, bsp_section_data_start	/* get start address of data section in RAM */
 	
 		
@@ -371,8 +317,8 @@
 	
 		
-	LA	r29, _data_start		/* get start address of data section in RAM */
-	
-	
-	LA	r28, _data_size  		/* get size of RAM image */
+	LA	r29, bsp_section_data_start	/* get start address of data section in RAM */
+	
+	
+	LA	r28, bsp_section_data_size  	/* get size of RAM image */
 		
 	
@@ -426,24 +372,26 @@
 skip_ROM_start:
 /* configure external DPRAM CS1 */
-    LWI r30,0xFFFFFB10
-	stw r30,CS1CONF(r31)
+	LWI	r30, 0xFFFFFB10
+	stw	r30, CS1CONF(r31)
 
 /* map external DPRAM (CS1) */
-    LWI r30,(DPRAM_START>>16)
-	stw r30,CS1STR(r31)
-
-    LWI r30,((DPRAM_END)>>16)
-	stw r30,CS1STP(r31)
+	LWI	r30, bsp_dpram_start
+	srawi	r30, r30, 16
+	stw	r30, CS1STR(r31)
+
+	LWI	r30, bsp_dpram_end
+	srawi	r30, r30, 16
+	stw	r30, CS1STP(r31)
 
 	lwz	r30, ADREN(r31)			/* get content of ADREN */
 			
 	LWI	r29, ADREN_CS1_EN		/* unmask ADREN_CS1_EN */
-	or	r30,r30,r29	
-	
-	stw	r30,ADREN(r31)			/* enable CS1 */
+	or	r30, r30,r29	
+	
+	stw	r30, ADREN(r31)			/* enable CS1 */
 
 /* clear entire on chip SRAM (unique for ROM startup) */
 	lis	r30, (MBAR+ONCHIP_SRAM_OFFSET)@h	/* get start address of onchip SRAM */
-	ori	r30,r30,(MBAR+ONCHIP_SRAM_OFFSET)@l
+	ori	r30, r30,(MBAR+ONCHIP_SRAM_OFFSET)@l
         LWI	r29, ONCHIP_SRAM_SIZE		/* get size of onchip SRAM */
 	
@@ -452,6 +400,6 @@
 #endif /* defined(BRS5L) */
 /* clear .bss section (unique for ROM startup) */
-	LWI	r30, _bss_start			/* get start address of bss section */
-        LWI	r29, _bss_size  		/* get size of bss section */
+	LWI	r30, bsp_section_bss_start	/* get start address of bss section */
+        LWI	r29, bsp_section_bss_size  	/* get size of bss section */
         
 
@@ -460,7 +408,8 @@
 
 /* set stack pointer (common for RAM/ROM startup) */
-	LA	r1, _text_start  
+	LA	r1, bsp_section_text_start  
         addi    r1, r1, -0x10			/* Set up stack pointer = beginning of text section - 0x10 */
-        
+
+	bl	__eabi				/* Set up EABI and SYSV environment */
      
 /* enable dynamic power management(common for RAM/ROM startup) */
@@ -623,5 +572,5 @@
 
 	li   	r29, PPC_D_CACHE		/* 16 Kb data cache on 603e */
-	LWI	r28, _text_start		/* Load base address (begin of RAM) */
+	LWI	r28, bsp_section_text_start	/* Load base address (begin of RAM) */
 
 FID_DCache_loop_1:
@@ -634,5 +583,5 @@
 
 	li   	r29, PPC_D_CACHE		/* 16 Kb data cache on 603e */
-	LWI	r28, _text_start		/* Reload base address (begin of RAM) */
+	LWI	r28, bsp_section_text_start	/* Reload base address (begin of RAM) */
 	xor	r27, r27, r27
 FID_DCache_loop_2:
@@ -698,5 +647,5 @@
 	
 #if 0	
-	LA	r29, RAM_START
+	LA	r29, bsp_ram_start
 	stw	r29, 0x0(r29)
 #endif	
Index: c/src/lib/libbsp/powerpc/gen5200/startup/bspclean.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen5200/startup/bspclean.c	(revision 9ac98838d6b795fe8ec395cb385d9cca9cfc55b6)
+++ c/src/lib/libbsp/powerpc/gen5200/startup/bspclean.c	(revision 82bd8d9d6619d7fd1a9a96dd9aa9e4e0047a1f49)
@@ -15,5 +15,6 @@
 #include <rtems/bspIo.h>
 #include <bsp.h>
-#include <mpc5200.h>
+#include <bsp/mpc5200.h>
+#include <bsp/bootcard.h>
 
 extern int mpc5200_uart_pollRead(int minor);
Index: c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c	(revision 9ac98838d6b795fe8ec395cb385d9cca9cfc55b6)
+++ c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c	(revision 82bd8d9d6619d7fd1a9a96dd9aa9e4e0047a1f49)
@@ -97,17 +97,18 @@
 #warning The interrupt disable mask is now stored in SPRG0, please verify that this is compatible to this BSP (see also bootcard.c).
 
-#include <bsp.h>
+#include <string.h>
 
 #include <rtems/libio.h>
 #include <rtems/libcsupport.h>
-#include <rtems/powerpc/powerpc.h>
 #include <rtems/score/thread.h>
 
-#include <rtems/bspIo.h>
-#include <libcpu/cpuIdent.h>
-#include <libcpu/spr.h>
-#include "../irq/irq.h"
-
-#include <string.h>
+#include <libcpu/powerpc-utility.h>
+#include <libcpu/raw_exception.h>
+
+#include <bsp.h>
+#include <bsp/bootcard.h>
+#include <bsp/ppc_exc_bspsupp.h>
+
+#include <bsp/irq.h>
 
 #if defined(HAS_UBOOT)
@@ -115,8 +116,4 @@
 bd_t uboot_bdinfo_copy;             /* will be overwritten with copy of bdinfo */
 #endif
-
-SPR_RW(SPRG1)
-
-extern unsigned long intrStackPtr;
 
 /*
@@ -125,12 +122,4 @@
 uint32_t   bsp_clicks_per_usec;
 
-/*
- *  Use the shared implementations of the following routines.
- *  Look in rtems/c/src/lib/libbsp/shared/bsplibc.c.
- */
-void bsp_libc_init( void *, uint32_t, int );
-extern void initialize_exceptions(void);
-extern void cpu_init(void);
-
 void BSP_panic(char *s)
   {
@@ -145,46 +134,21 @@
   }
 
-/*
- *  Function:   bsp_pretasking_hook
- *  Created:    95/03/10
- *
- *  Description:
- *      BSP pretasking hook.  Called just before drivers are initialized.
- *      Used to setup libc and install any BSP extensions.
- *
- *  NOTES:
- *      Must not use libc (to do io) from here, since drivers are
- *      not yet initialized.
- *
- */
-
-void
-bsp_pretasking_hook(void)
+void bsp_get_work_area(
+  void   **work_area_start,
+  size_t  *work_area_size,
+  void   **heap_start,
+  size_t  *heap_size)
 {
-  /*
-   *  These are assigned addresses in the linkcmds file for the BSP. This
-   *  approach is better than having these defined as manifest constants and
-   *  compiled into the kernel, but it is still not ideal when dealing with
-   *  multiprocessor configuration in which each board as a different memory
-   *  map. A better place for defining these symbols might be the makefiles.
-   *  Consideration should also be given to developing an approach in which
-   *  the kernel and the application can be linked and burned into ROM
-   *  independently of each other.
-   */
-
-#if defined(HAS_UBOOT)
-    extern unsigned char _HeapStart;
-
-    bsp_libc_init( &_HeapStart, 
-		   uboot_bdinfo_ptr->bi_memstart 
-		   + uboot_bdinfo_ptr->bi_memsize 
-		   - (uint32_t)&_HeapStart
-		   , 0 );
-#else
-    extern unsigned char _HeapStart;
-    extern unsigned char _HeapEnd;
-
-    bsp_libc_init( &_HeapStart, &_HeapEnd - &_HeapStart, 0 );
-#endif
+#ifdef HAS_UBOOT
+  char *ram_end = (char *) uboot_bdinfo_ptr->bi_memstart +
+                                 uboot_bdinfo_ptr->bi_memsize;
+#else /* HAS_UBOOT */
+  char *ram_end = bsp_ram_end;
+#endif /* HAS_UBOOT */
+
+  *work_area_start = bsp_work_area_start;
+  *work_area_size = ram_end - bsp_work_area_start;
+  *heap_start = BSP_BOOTCARD_HEAP_USES_WORK_AREA;
+  *heap_size = BSP_BOOTCARD_HEAP_SIZE_DEFAULT;
 }
 
@@ -220,8 +184,6 @@
 void bsp_start(void)
 {
-  extern void *_WorkspaceBase;
   ppc_cpu_id_t myCpu;
   ppc_cpu_revision_t myCpuRevision;
-  register unsigned char* intrStack;
 
   /*
@@ -247,19 +209,5 @@
   cpu_init();
 
-  /*
-   * Initialize some SPRG registers related to irq handling
-   */
-
-  intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE);
-
-  _write_SPRG1((unsigned int)intrStack);
-
  bsp_clicks_per_usec    = (IPB_CLOCK/1000000);
-
- /*
-  * Install our own set of exception vectors
-  */
-
-  initialize_exceptions();
 
   /*
@@ -273,19 +221,16 @@
   #endif
 
-  /*
-   *  Need to "allocate" the memory for the RTEMS Workspace and
-   *  tell the RTEMS configuration where it is.  This memory is
-   *  not malloc'ed.  It is just "pulled from the air".
-   */
-  Configuration.work_space_start = (void *)&_WorkspaceBase;
-  #ifdef SHOW_MORE_INIT_SETTINGS
-    printk( "workspace=%p\n", Configuration.work_space_start );
-    printk( "workspace size=%d\n", Configuration.work_space_size );
-  #endif
-
-  /*
-   * Initalize RTEMS IRQ system
-   */
-  BSP_rtems_irq_mng_init(0);
+  /* Initialize exception handler */
+  ppc_exc_cache_wb_check = 0;
+  ppc_exc_initialize(
+    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
+    (uint32_t) bsp_interrupt_stack_start,
+    (uint32_t) bsp_interrupt_stack_size
+  );
+
+  /* Initalize interrupt support */
+  if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
+    BSP_panic( "Cannot intitialize interrupt support\n");
+  }
 
   /*
Index: c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c
===================================================================
--- c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c	(revision 9ac98838d6b795fe8ec395cb385d9cca9cfc55b6)
+++ c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c	(revision 82bd8d9d6619d7fd1a9a96dd9aa9e4e0047a1f49)
@@ -118,14 +118,50 @@
   BAT dbat;
 
-  calc_dbat_regvals(&dbat,RAM_START,RAM_SIZE,1,0,0,0,BPP_RW);
+  calc_dbat_regvals(
+    &dbat,
+    (uint32_t) bsp_ram_start,
+    (uint32_t) bsp_ram_size,
+    true,
+    false,
+    false,
+    false,
+    BPP_RW
+  );
   SET_DBAT(0,dbat.batu,dbat.batl);
 
-  calc_dbat_regvals(&dbat,ROM_START,ROM_SIZE,1,0,0,0,BPP_RX);
+  calc_dbat_regvals(
+    &dbat,
+    (uint32_t) bsp_rom_start,
+    (uint32_t) bsp_rom_size,
+    true,
+    false,
+    false,
+    false,
+    BPP_RX
+  );
   SET_DBAT(1,dbat.batu,dbat.batl);
 
-  calc_dbat_regvals(&dbat,MBAR,128*1024,1,1,1,1,BPP_RW);
+  calc_dbat_regvals(
+    &dbat,
+    (uint32_t) MBAR,
+    128 * 1024,
+    false,
+    true,
+    false,
+    true,
+    BPP_RW
+  );
   SET_DBAT(2,dbat.batu,dbat.batl);
 
-  calc_dbat_regvals(&dbat,DPRAM_START,128*1024,1,1,1,1,BPP_RW);
+  calc_dbat_regvals(
+    &dbat,
+    (uint32_t) bsp_dpram_start,
+    128 * 1024,
+    false,
+    true,
+    false,
+    true,
+    BPP_RW
+  );
   SET_DBAT(3,dbat.batu,dbat.batl);
 }
@@ -134,12 +170,19 @@
 {
   BAT dbat;
+  uint32_t start = 0;
   
   /*
    * Program BAT0 for RAM
    */
-  calc_dbat_regvals(&dbat,
-		    uboot_bdinfo_ptr->bi_memstart,
-		    uboot_bdinfo_ptr->bi_memsize,
-		    1,0,0,0,BPP_RW);
+  calc_dbat_regvals(
+    &dbat,
+    uboot_bdinfo_ptr->bi_memstart,
+    uboot_bdinfo_ptr->bi_memsize,
+    true,
+    false,
+    false,
+    false,
+    BPP_RW
+  );
   SET_DBAT(0,dbat.batu,dbat.batl);
 
@@ -151,15 +194,20 @@
    * corrects that.
    */
-  if ( (uboot_bdinfo_ptr->bi_flashstart + uboot_bdinfo_ptr->bi_flashsize) <
-	uboot_bdinfo_ptr->bi_flashstart ) {
-    uint32_t start = 0 - uboot_bdinfo_ptr->bi_flashsize;
-    calc_dbat_regvals(&dbat,
-		      start, uboot_bdinfo_ptr->bi_flashsize, 1,0,0,0,BPP_RX);
+  if ((uboot_bdinfo_ptr->bi_flashstart + uboot_bdinfo_ptr->bi_flashsize)
+    < uboot_bdinfo_ptr->bi_flashstart) {
+    start = 0 - uboot_bdinfo_ptr->bi_flashsize;
   } else {
-    calc_dbat_regvals(&dbat,
-		      uboot_bdinfo_ptr->bi_flashstart,
-		      uboot_bdinfo_ptr->bi_flashsize,
-		      1,0,0,0,BPP_RX);
+    start = uboot_bdinfo_ptr->bi_flashstart;
   }
+  calc_dbat_regvals(
+    &dbat,
+    start,
+    uboot_bdinfo_ptr->bi_flashsize,
+    true,
+    false,
+    false,
+    false,
+    BPP_RX
+  );
   SET_DBAT(1,dbat.batu,dbat.batl);
 
@@ -167,5 +215,14 @@
    * Program BAT2 for the MBAR
    */
-  calc_dbat_regvals(&dbat,MBAR,128*1024,1,1,1,1,BPP_RW);
+  calc_dbat_regvals(
+    &dbat,
+    (uint32_t) MBAR,
+    128 * 1024,
+    false,
+    true,
+    false,
+    true,
+    BPP_RW
+  );
   SET_DBAT(2,dbat.batu,dbat.batl);
 
@@ -174,8 +231,14 @@
    */
   if (uboot_bdinfo_ptr->bi_sramsize != 0) {
-    calc_dbat_regvals(&dbat,
-		      uboot_bdinfo_ptr->bi_sramstart,
-		      uboot_bdinfo_ptr->bi_sramsize,
-		      0,1,1,1,BPP_RW);
+    calc_dbat_regvals(
+      &dbat,
+      uboot_bdinfo_ptr->bi_sramstart,
+      uboot_bdinfo_ptr->bi_sramsize,
+      false,
+      true,
+      true,
+      true,
+      BPP_RW
+    );
     SET_DBAT(3,dbat.batu,dbat.batl);
   }
