Changeset 82bd8d9d in rtems


Ignore:
Timestamp:
Sep 3, 2008, 3:39:03 PM (11 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, 4.9, master
Children:
6f776e71
Parents:
9ac9883
Message:

Converted to use shared

exception and interrupt code.

Location:
c/src/lib/libbsp/powerpc/gen5200
Files:
15 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/gen5200/bestcomm/bestcomm_glue.c

    r9ac9883 r82bd8d9d  
    2020#include <rtems/error.h>
    2121#include <bsp.h>
    22 #include "../irq/irq.h"
     22#include <bsp/irq.h>
    2323#include "../include/mpc5200.h"
    2424#include "include/ppctypes.h"                   /* uint32, et. al.                 */
  • c/src/lib/libbsp/powerpc/gen5200/bestcomm/load_task.c

    r9ac9883 r82bd8d9d  
    4040__declspec(section ".text") extern const uint32 offsetEntry;
    4141#else
    42 extern const uint32 taskTable;
     42extern const uint32 taskTable [];
    4343extern const uint32 taskTableBytes;
    4444extern const uint32 taskTableTasks;
     
    7272
    7373        /* copy task table from source to destination */
    74         memcpy((void *)((uint8 *)(sdma->taskBar) - MBarPhysOffsetGlobal), &taskTable, taskTableBytes);
     74        memcpy((void *)((uint8 *)(sdma->taskBar) - MBarPhysOffsetGlobal), taskTable, taskTableBytes);
    7575        /* adjust addresses in task table */
    7676        for (i=0; i < (uint32) taskTableTasks; i++) {
  • c/src/lib/libbsp/powerpc/gen5200/clock/clock.c

    r9ac9883 r82bd8d9d  
    104104#include <bsp.h>
    105105#include <rtems/bspIo.h>
    106 #include "../irq/irq.h"
     106#include <bsp/irq.h>
    107107
    108108#include <rtems.h>
     
    114114
    115115#define GPT (BSP_PERIODIC_TIMER - BSP_SIU_IRQ_TMR0)
     116
     117extern uint32_t bsp_clicks_per_usec;
    116118
    117119/* this lets us do nanoseconds since last tick */
     
    123125 *  ISR Handlers
    124126 */
    125 void mpc5200_gpt_clock_isr(rtems_irq_hdl_param handle)
     127void mpc5200_gpt_clock_isr(rtems_vector_number vector, void *handle)
    126128{
    127129  uint32_t status;
     
    219221}
    220222
    221 void clockOn(const rtems_irq_connect_data* irq)
     223void clockOn()
    222224{
    223225  uint32_t gpt_no;
    224   extern uint32_t bsp_clicks_per_usec;
    225 
    226   gpt_no = BSP_SIU_IRQ_TMR0 - (irq->name);
     226
     227  gpt_no = BSP_SIU_IRQ_TMR0 - BSP_PERIODIC_TIMER;
    227228
    228229  counter_value = rtems_configuration_get_microseconds_per_tick() *
    229230                      bsp_clicks_per_usec;
    230231
    231   mpc5200_set_gpt_count(counter_value, (uint32_t)gpt_no);
    232   mpc5200_enable_gpt_int((uint32_t)gpt_no);
     232  mpc5200_set_gpt_count(counter_value, gpt_no);
     233  mpc5200_enable_gpt_int(gpt_no);
    233234
    234235  ClockInitialized = 1;
    235236}
    236237
    237 void clockOff(const rtems_irq_connect_data* irq)
     238void clockOff()
    238239{
    239240  uint32_t gpt_no;
    240241
    241   gpt_no = BSP_SIU_IRQ_TMR0 - (irq->name);
    242 
    243   mpc5200_disable_gpt_int((uint32_t)gpt_no);
     242  gpt_no = BSP_SIU_IRQ_TMR0 - BSP_PERIODIC_TIMER;
     243
     244  mpc5200_disable_gpt_int(gpt_no);
    244245
    245246  ClockInitialized = 0;
    246247}
    247 
    248 int clockIsOn(const rtems_irq_connect_data* irq)
    249 {
    250   uint32_t gpt_no;
    251 
    252   gpt_no = BSP_SIU_IRQ_TMR0 - (irq->name);
    253 
    254   if (mpc5200_check_gpt_status(gpt_no) && ClockInitialized)
    255     return ClockInitialized;
    256   return 0;
    257 }
    258 
    259248
    260249int BSP_get_clock_irq_level(void)
     
    267256}
    268257
    269 
    270 int BSP_disconnect_clock_handler (void)
    271 {
    272   rtems_irq_connect_data clockIrqData;
    273   clockIrqData.name   = BSP_PERIODIC_TIMER;
    274 
    275 
    276   if (!BSP_get_current_rtems_irq_handler(&clockIrqData)) {
    277     printk("Unable to stop system clock\n");
    278     rtems_fatal_error_occurred(1);
    279   }
    280 
    281   return BSP_remove_rtems_irq_handler (&clockIrqData);
    282 }
    283 
    284 
    285 int BSP_connect_clock_handler (uint32_t gpt_no)
    286 {
    287   rtems_irq_hdl hdl = 0;
    288   rtems_irq_connect_data clockIrqData;
    289 
    290   /*
    291    * Reinit structure
    292    */
    293   clockIrqData.name   = BSP_PERIODIC_TIMER;
    294 
    295   if (!BSP_get_current_rtems_irq_handler(&clockIrqData)) {
    296     printk("Unable to get system clock handler\n");
    297     rtems_fatal_error_occurred(1);
    298   }
    299 
    300   if (!BSP_remove_rtems_irq_handler (&clockIrqData)) {
    301     printk("Unable to remove current system clock handler\n");
    302     rtems_fatal_error_occurred(1);
    303   }
    304 
    305   if ((gpt_no >= GPT0) || (gpt_no <= GPT7)) {
    306     hdl = (rtems_irq_hdl_param )&mpc5200.gpt[gpt_no];
    307   } else {
     258int BSP_disconnect_clock_handler (unsigned gpt_no)
     259{
     260  rtems_status_code sc = RTEMS_SUCCESSFUL;
     261
     262  if ((gpt_no < GPT0) || (gpt_no > GPT7)) {
     263    return 0;
     264  }
     265
     266  clockOff( BSP_PERIODIC_TIMER);
     267
     268  sc = rtems_interrupt_handler_remove(
     269    BSP_PERIODIC_TIMER,
     270    mpc5200_gpt_clock_isr,
     271    &mpc5200.gpt [gpt_no]
     272  );
     273  if (sc != RTEMS_SUCCESSFUL) {
     274    return 0;
     275  }
     276
     277  return 1;
     278}
     279
     280int BSP_connect_clock_handler (unsigned gpt_no)
     281{
     282  rtems_status_code sc = RTEMS_SUCCESSFUL;
     283
     284  if ((gpt_no < GPT0) || (gpt_no > GPT7)) {
    308285    printk("Unable to set system clock handler\n");
    309286    rtems_fatal_error_occurred(1);
    310287  }
    311288
    312   clockIrqData.hdl    = mpc5200_gpt_clock_isr;
    313   clockIrqData.handle = (rtems_irq_hdl_param) hdl;
    314   clockIrqData.on     = clockOn;
    315   clockIrqData.off    = clockOff;
    316   clockIrqData.isOn   = clockIsOn;
    317 
    318   return BSP_install_rtems_irq_handler (&clockIrqData);
     289  sc = rtems_interrupt_handler_install(
     290    BSP_PERIODIC_TIMER,
     291    "Clock",
     292    RTEMS_INTERRUPT_UNIQUE,
     293    mpc5200_gpt_clock_isr,
     294    &mpc5200.gpt [gpt_no]
     295  );
     296  if (sc != RTEMS_SUCCESSFUL) {
     297    return 0;
     298  }
     299
     300  clockOn();
     301
     302  return 1;
    319303}
    320304
     
    343327#define Clock_driver_support_initialize_hardware() \
    344328  do {        \
    345     extern uint32_t bsp_clicks_per_usec; \
    346329    counter_value = rtems_configuration_get_microseconds_per_tick() * \
    347330                    bsp_clicks_per_usec; \
     
    355338#define Clock_driver_support_shutdown_hardware() \
    356339  do { \
    357     (void) BSP_disconnect_clock_handler (); \
     340    (void) BSP_disconnect_clock_handler (GPT); \
    358341  } while (0)
    359342
  • c/src/lib/libbsp/powerpc/gen5200/console/console.c

    r9ac9883 r82bd8d9d  
    9999#include "../include/mpc5200.h"
    100100#include <bsp.h>
    101 #include "../irq/irq.h"
     101#include <bsp/irq.h>
    102102
    103103#include <rtems/bspIo.h>
  • c/src/lib/libbsp/powerpc/gen5200/i2c/mpc5200mbus.c

    r9ac9883 r82bd8d9d  
    3535#include "mpc5200mbus.h"
    3636#include "../include/mpc5200.h"
    37 #include "../irq/irq.h"
     37#include <bsp/irq.h>
    3838#include "../include/i2c.h"
    3939
  • c/src/lib/libbsp/powerpc/gen5200/ide/idecfg.c

    r9ac9883 r82bd8d9d  
    1919#include <rtems.h>
    2020#include <bsp.h>
    21 #include "../irq/irq.h"
     21#include <bsp/irq.h>
    2222#include "../include/mpc5200.h"
    2323#include "./pcmcia_ide.h"
  • c/src/lib/libbsp/powerpc/gen5200/ide/pcmcia_ide.c

    r9ac9883 r82bd8d9d  
    7979#include <rtems/error.h>
    8080#include <bsp.h>
    81 #include "../irq/irq.h"
     81#include <bsp/irq.h>
    8282#include "../include/mpc5200.h"
    8383#include "./pcmcia_ide.h"
  • c/src/lib/libbsp/powerpc/gen5200/include/bsp.h

    r9ac9883 r82bd8d9d  
    2424#define __GEN5200_BSP_h
    2525
     26#include <libcpu/powerpc-utility.h>
     27
     28/*
     29 * Some symbols defined in the linker command file.
     30 */
     31
     32LINKER_SYMBOL(bsp_ram_start);
     33LINKER_SYMBOL(bsp_ram_end);
     34LINKER_SYMBOL(bsp_ram_size);
     35
     36LINKER_SYMBOL(bsp_rom_start);
     37LINKER_SYMBOL(bsp_rom_end);
     38LINKER_SYMBOL(bsp_rom_size);
     39
     40LINKER_SYMBOL(bsp_dpram_start);
     41LINKER_SYMBOL(bsp_dpram_end);
     42LINKER_SYMBOL(bsp_dpram_size);
     43
     44LINKER_SYMBOL(bsp_section_text_start);
     45LINKER_SYMBOL(bsp_section_text_end);
     46LINKER_SYMBOL(bsp_section_text_size);
     47
     48LINKER_SYMBOL(bsp_section_data_start);
     49LINKER_SYMBOL(bsp_section_data_end);
     50LINKER_SYMBOL(bsp_section_data_size);
     51
     52LINKER_SYMBOL(bsp_section_bss_start);
     53LINKER_SYMBOL(bsp_section_bss_end);
     54LINKER_SYMBOL(bsp_section_bss_size);
     55
     56LINKER_SYMBOL(bsp_interrupt_stack_start);
     57LINKER_SYMBOL(bsp_interrupt_stack_end);
     58LINKER_SYMBOL(bsp_interrupt_stack_size);
     59
     60LINKER_SYMBOL(bsp_work_area_start);
     61
     62LINKER_SYMBOL(MBAR);
     63
    2664/*
    2765 * distinguish board characteristics
     
    5795/* we have PSC1/2/3 */
    5896#define GEN5200_UART_AVAIL_MASK 0x07
    59 /*
    60  * address range definitions
    61  */
    62 /* ROM definitions (2 MB) */
    63 #define ROM_START       0xFFE00000
    64 #define ROM_SIZE        0x00200000
    65 #define ROM_END         (ROM_START+ROM_SIZE-1)
    66 #define BOOT_START      ROM_START
    67 #define BOOT_END        ROM_END
    68 
    69 /* SDRAM definitions (256 MB) */
    70 #define RAM_START       0x00000000
    71 #define RAM_SIZE        0x10000000
    72 #define RAM_END         (RAM_START+RAM_SIZE-1)
    73 
    74 /* DPRAM definitions (64 KB) */
    75 #define DPRAM_START  0xFF000000
    76 #define DPRAM_END    0xFF0003FF
    77 
    78 /* internal memory map definitions (64 KB) */
    79 #define MBAR         0xF0000000
    8097
    8198/* we need the low level initialization in start.S*/
     
    85102#elif defined (PM520)
    86103
    87 /*
    88  * MicroSys PM520 internal memory map definitions
    89  */
    90 #define MBAR         0xF0000000
    91104#define HAS_UBOOT
    92105
     
    107120/* we only have PSC1 */
    108121#define GEN5200_UART_AVAIL_MASK 0x01
    109 
    110 #define MBAR         0xF0000000
    111122
    112123/* We want to prompt for a reset and then reset the board */
     
    270281#endif
    271282
     283void cpu_init(void);
     284
    272285#ifdef __cplusplus
    273286}
  • c/src/lib/libbsp/powerpc/gen5200/irq/irq.c

    r9ac9883 r82bd8d9d  
    7474/***********************************************************************/
    7575
     76#include <rtems.h>
     77
     78#include <libcpu/powerpc-utility.h>
     79#include <libcpu/raw_exception.h>
     80
    7681#include <bsp.h>
    77 #include <rtems.h>
    78 #include "../irq/irq.h"
    79 #include <rtems/score/apiext.h>
    80 #include <rtems/bspIo.h>
    81 #include <libcpu/raw_exception.h>
    82 #include "../vectors/vectors.h"
    83 #include "../include/mpc5200.h"
    84 
    85 
    86 extern uint32_t irqMaskTable[];
    87 
    88 /*
    89  * default handler connected on each irq after bsp initialization
    90  */
    91 static rtems_irq_connect_data  default_rtems_entry;
    92 
    93 /*
    94  * location used to store initial tables used for interrupt
    95  * management.
    96  */
    97 static rtems_irq_global_settings*   internal_config;
    98 static rtems_irq_connect_data*      rtems_hdl_tbl;
     82#include <bsp/irq.h>
     83#include <bsp/vectors.h>
     84#include <bsp/ppc_exc_bspsupp.h>
     85#include <bsp/irq-generic.h>
     86#include <bsp/mpc5200.h>
    9987
    10088/*
     
    10391 *
    10492 */
    105 const static unsigned int SIU_MaskBit[BSP_SIU_IRQ_NUMBER] =
    106   {
    107   0, 1, 2, 3,       /* smart_comm, psc1, psc2, psc3            */
    108   4, 5, 6, 7,       /* irda/psc6, eth, usb, ata                */
    109   8, 9, 10, 11,     /* pci_ctrl, pci_sc_rx, pci_sc_tx, psc4    */
    110   12, 13, 14, 15,   /* psc5,spi_modf, spi_spif, i2c1           */
    111   16, 17, 18, 19,   /* i2c, can1, can2, ir_rx                  */
    112   20, 21, 15, 16,   /* ir_rx, xlb_arb, slice_tim2, irq1,       */
    113   17, 18, 19, 20,   /* irq2, irq3, lo_int, rtc_pint            */
    114   21, 22, 23, 24,   /* rtc_sint, gpio_std, gpio_wkup, tmr0     */
    115   25, 26, 27, 28,   /* tmr1, tmr2, tmr3, tmr4                  */
    116   29, 30, 31, 32,   /* tmr5, tmr6, tmr7, res                   */
    117   32, 32, 32        /* res, res, res                           */
    118   };
     93const static unsigned int SIU_MaskBit [BSP_SIU_IRQ_NUMBER] = {
     94  0, 1, 2, 3,                   /* smart_comm, psc1, psc2, psc3            */
     95  4, 5, 6, 7,                   /* irda/psc6, eth, usb, ata                */
     96  8, 9, 10, 11,                 /* pci_ctrl, pci_sc_rx, pci_sc_tx, psc4    */
     97  12, 13, 14, 15,               /* psc5,spi_modf, spi_spif, i2c1           */
     98  16, 17, 18, 19,               /* i2c, can1, can2, ir_rx                  */
     99  20, 21, 15, 16,               /* ir_rx, xlb_arb, slice_tim2, irq1,       */
     100  17, 18, 19, 20,               /* irq2, irq3, lo_int, rtc_pint            */
     101  21, 22, 23, 24,               /* rtc_sint, gpio_std, gpio_wkup, tmr0     */
     102  25, 26, 27, 28,               /* tmr1, tmr2, tmr3, tmr4                  */
     103  29, 30, 31, 32,               /* tmr5, tmr6, tmr7, res                   */
     104  32, 32, 32                    /* res, res, res                           */
     105};
     106
     107static unsigned char irqPrioTable [BSP_SIU_IRQ_NUMBER] = {
     108/* per. int. priorities (0-7) / 4bit coding / msb is HI/LO selection               */
     109/* msb = 0 -> non-critical per. int. is routed to main int. (LO_int)               */
     110/* msb = 1 -> critical per. int. is routed to critical int. (HI_int)               */
     111  0xF, 0, 0, 0,                 /* smart_comm (do not change!), psc1, psc2, psc3             */
     112  0, 0, 0, 0,                   /* irda, eth, usb, ata                                       */
     113  0, 0, 0, 0,                   /* pci_ctrl, pci_sc_rx, pci_sc_tx, res                       */
     114  0, 0, 0, 0,                   /* res, spi_modf, spi_spif, i2c1                             */
     115  0, 0, 0, 0,                   /* i2c, can1, can2, ir_rx                                    */
     116  0, 0,                         /* ir_rx, xlb_arb                                            */
     117/* main interrupt priorities (0-7) / 4bit coding / msb is INT/SMI selection        */
     118/* msb = 0 -> main int. is routed to processor INT (low vector base 0x500 )        */
     119/* msb = 1 -> main int. is routed to processor SMI (low vector base 0x1400 )       */
     120  0, 0,                         /* slice_tim2, irq1                                          */
     121  0, 0, 0, 0,                   /* irq2, irq3, lo_int, rtc_pint                              */
     122  0, 0, 0, 0,                   /* rtc_sint, gpio_std, gpio_wkup, tmr0                       */
     123  0, 0, 0, 0,                   /* tmr1, tmr2, tmr3, tmr4                                    */
     124  0, 0, 0,                      /* tmr5, tmr6, tmr7                                          */
     125  /* critical interrupt priorities (0-3) / 2bit coding / no special purpose of msb */
     126  0,                            /* irq0                                                      */
     127  0, 0, 0                       /* slice_tim1, hi_int, ccs_wkup                              */
     128};
     129
     130static uint32_t irqMaskTable [BSP_PER_IRQ_NUMBER + BSP_MAIN_IRQ_NUMBER];
    119131
    120132/*
    121133 * Check if symbolic IRQ name is a Processor IRQ
    122134 */
    123 static inline int is_processor_irq(const rtems_irq_symbolic_name irqLine)
    124 {
    125 
    126   return (((int)irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET) &
    127           ((int)irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET));
     135static inline bool is_processor_irq( rtems_vector_number irqLine)
     136{
     137
     138  return ((irqLine <= BSP_PROCESSOR_IRQ_MAX_OFFSET)
     139    && (irqLine >= BSP_PROCESSOR_IRQ_LOWEST_OFFSET));
    128140}
    129141
     
    131143 * Check for SIU IRQ and return base index
    132144 */
    133 static inline int is_siu_irq(const rtems_irq_symbolic_name irqLine)
    134 {
    135 
    136   return (((int)irqLine <= BSP_SIU_IRQ_MAX_OFFSET) &&
    137            ((int)irqLine >= BSP_SIU_IRQ_LOWEST_OFFSET));
    138 
    139 }
    140 
     145static inline bool is_siu_irq( rtems_vector_number irqLine)
     146{
     147
     148  return ((irqLine <= BSP_SIU_IRQ_MAX_OFFSET)
     149    && (irqLine >= BSP_SIU_IRQ_LOWEST_OFFSET));
     150}
    141151
    142152/*
    143153 * Check for SIU IRQ and return base index
    144154 */
    145 static inline int get_siu_irq_base_index(const rtems_irq_symbolic_name irqLine)
    146 {
    147 
     155static inline int get_siu_irq_base_index( rtems_vector_number irqLine)
     156{
    148157  if (irqLine <= BSP_PER_IRQ_MAX_OFFSET)
    149158    return BSP_PER_IRQ_LOWEST_OFFSET;
     
    151160  if (irqLine <= BSP_MAIN_IRQ_MAX_OFFSET)
    152161    return BSP_MAIN_IRQ_LOWEST_OFFSET;
     162
    153163  if (irqLine <= BSP_CRIT_IRQ_MAX_OFFSET)
    154164    return BSP_CRIT_IRQ_LOWEST_OFFSET;
     
    157167}
    158168
    159 
    160169static inline void BSP_enable_per_irq_at_siu(
    161   const rtems_irq_symbolic_name irqLine
     170  rtems_vector_number irqLine
    162171)
    163172{
    164   uint8_t lo_hi_ind = 0, prio_index_offset;
     173  uint8_t lo_hi_ind = 0,
     174    prio_index_offset;
    165175  uint32_t *reg;
    166   rtems_irq_prio *irqPrioTable = internal_config->irqPrioTbl;
    167   volatile uint32_t per_pri_1,main_pri_1, crit_pri_main_mask, per_mask;
     176  volatile uint32_t per_pri_1,
     177    main_pri_1,
     178    crit_pri_main_mask,
     179    per_mask;
    168180
    169181  /* calculate the index offset of priority value bit field */
     
    171183
    172184  /* set interrupt priorities */
    173   if (irqPrioTable[irqLine] <= 15) {
     185  if (irqPrioTable [irqLine] <= 15) {
    174186
    175187    /* set peripheral int priority */
    176     reg = (uint32_t *)(&(mpc5200.per_pri_1));
     188    reg = (uint32_t *) (&(mpc5200.per_pri_1));
    177189
    178190    /* choose proper register */
     
    180192
    181193    /* set priority as given in priority table */
    182     *reg |= (irqPrioTable[irqLine] << (28 - (prio_index_offset<< 2)));
     194    *reg |= (irqPrioTable [irqLine] << (28 - (prio_index_offset << 2)));
    183195
    184196    /* test msb (hash-bit) and set LO_/HI_int indicator */
    185     if ((lo_hi_ind = (irqPrioTable[irqLine] >> 3))) {
     197    if ((lo_hi_ind = (irqPrioTable [irqLine] >> 3))) {
    186198
    187199      /* set critical HI_int priority */
    188       reg = (uint32_t *)(&(mpc5200.crit_pri_main_mask));
    189       *reg |= (irqPrioTable[BSP_SIU_IRQ_HI_INT] << 26);
     200      reg = (uint32_t *) (&(mpc5200.crit_pri_main_mask));
     201      *reg |= (irqPrioTable [BSP_SIU_IRQ_HI_INT] << 26);
    190202
    191203      /*
     
    194206       * to core_int (bit 31 / CEb)
    195207       */
    196        mpc5200.ext_en_type |= 1;
     208      mpc5200.ext_en_type |= 1;
    197209
    198210    } else {
    199       if (irqPrioTable[irqLine] <= 15) {
     211      if (irqPrioTable [irqLine] <= 15) {
    200212        /* set main LO_int priority */
    201         reg = (uint32_t *)(&(mpc5200.main_pri_1));
    202         *reg |= (irqPrioTable[BSP_SIU_IRQ_LO_INT] << 16);
     213        reg = (uint32_t *) (&(mpc5200.main_pri_1));
     214        *reg |= (irqPrioTable [BSP_SIU_IRQ_LO_INT] << 16);
    203215      }
    204216    }
     
    208220  if (!lo_hi_ind) {
    209221    mpc5200.crit_pri_main_mask &=
    210       ~(0x80000000 >> SIU_MaskBit[BSP_SIU_IRQ_LO_INT]);
    211   }
    212 
     222      ~(0x80000000 >> SIU_MaskBit [BSP_SIU_IRQ_LO_INT]);
     223  }
    213224
    214225  /* enable (unmask) peripheral interrupt */
    215   mpc5200.per_mask &= ~(0x80000000 >> SIU_MaskBit[irqLine]);
    216 
    217   main_pri_1         = mpc5200.main_pri_1;
     226  mpc5200.per_mask &= ~(0x80000000 >> SIU_MaskBit [irqLine]);
     227
     228  main_pri_1 = mpc5200.main_pri_1;
    218229  crit_pri_main_mask = mpc5200.crit_pri_main_mask;
    219   per_pri_1          = mpc5200.per_pri_1;
    220   per_mask           = mpc5200.per_mask;
    221 
    222 
    223 }
    224 
     230  per_pri_1 = mpc5200.per_pri_1;
     231  per_mask = mpc5200.per_mask;
     232
     233}
    225234
    226235static inline void BSP_enable_main_irq_at_siu(
    227   const rtems_irq_symbolic_name irqLine
     236  rtems_vector_number irqLine
    228237)
    229238{
     
    231240  uint8_t prio_index_offset;
    232241  uint32_t *reg;
    233   rtems_irq_prio *irqPrioTable = internal_config->irqPrioTbl;
    234242
    235243  /* calculate the index offset of priority value bit field */
     
    237245
    238246  /* set main interrupt priority */
    239   if (irqPrioTable[irqLine] <= 15) {
     247  if (irqPrioTable [irqLine] <= 15) {
    240248
    241249    /* set main int priority */
    242     reg = (uint32_t *)(&(mpc5200.main_pri_1));
     250    reg = (uint32_t *) (&(mpc5200.main_pri_1));
    243251
    244252    /* choose proper register */
     
    246254
    247255    /* set priority as given in priority table */
    248     *reg |= (irqPrioTable[irqLine] << (28 - (prio_index_offset << 2)));
     256    *reg |= (irqPrioTable [irqLine] << (28 - (prio_index_offset << 2)));
    249257
    250258    if ((irqLine >= BSP_SIU_IRQ_IRQ1) && (irqLine <= BSP_SIU_IRQ_IRQ3)) {
     
    255263
    256264  /* enable (unmask) main interrupt */
    257   mpc5200.crit_pri_main_mask &= ~(0x80000000 >> SIU_MaskBit[irqLine]);
    258 
    259 }
    260 
     265  mpc5200.crit_pri_main_mask &= ~(0x80000000 >> SIU_MaskBit [irqLine]);
     266
     267}
    261268
    262269static inline void BSP_enable_crit_irq_at_siu(
    263   const rtems_irq_symbolic_name irqLine
     270  rtems_vector_number irqLine
    264271)
    265272{
    266273  uint8_t prio_index_offset;
    267274  uint32_t *reg;
    268   rtems_irq_prio *irqPrioTable = internal_config->irqPrioTbl;
    269275
    270276  prio_index_offset = irqLine - BSP_CRIT_IRQ_LOWEST_OFFSET;
     
    277283  mpc5200.ext_en_type |= 1;
    278284
    279 
    280285  /* set critical interrupt priorities */
    281   if (irqPrioTable[irqLine] <= 3) {
     286  if (irqPrioTable [irqLine] <= 3) {
    282287
    283288    /* choose proper register */
    284     reg = (uint32_t *)(&(mpc5200.crit_pri_main_mask));
     289    reg = (uint32_t *) (&(mpc5200.crit_pri_main_mask));
    285290
    286291    /* set priority as given in priority table */
    287     *reg |= (irqPrioTable[irqLine] << (30 - (prio_index_offset << 1)));
     292    *reg |= (irqPrioTable [irqLine] << (30 - (prio_index_offset << 1)));
    288293
    289294    /* external irq0-pin */
     
    295300}
    296301
    297 
    298302static inline void BSP_disable_per_irq_at_siu(
    299   const rtems_irq_symbolic_name irqLine
     303  rtems_vector_number irqLine
    300304)
    301305{
     
    307311
    308312  /* disable (mask) peripheral interrupt */
    309   mpc5200.per_mask |= (0x80000000 >> SIU_MaskBit[irqLine]);
     313  mpc5200.per_mask |= (0x80000000 >> SIU_MaskBit [irqLine]);
    310314
    311315  /* reset priority to lowest level (reset value) */
    312   reg = (uint32_t *)(&(mpc5200.per_pri_1));
     316  reg = (uint32_t *) (&(mpc5200.per_pri_1));
    313317  reg += (irqLine >> 3);
    314318  *reg &= ~(15 << (28 - (prio_index_offset << 2)));
    315319}
    316320
    317 
    318321static inline void BSP_disable_main_irq_at_siu(
    319   const rtems_irq_symbolic_name irqLine
     322  rtems_vector_number irqLine
    320323)
    321324{
     
    327330
    328331  /* disable (mask) main interrupt */
    329   mpc5200.crit_pri_main_mask |= (0x80000000 >> SIU_MaskBit[irqLine]);
     332  mpc5200.crit_pri_main_mask |= (0x80000000 >> SIU_MaskBit [irqLine]);
    330333
    331334  if ((irqLine >= BSP_SIU_IRQ_IRQ1) && (irqLine <= BSP_SIU_IRQ_IRQ3)) {
     
    335338
    336339  /* reset priority to lowest level (reset value) */
    337   reg = (uint32_t *)(&(mpc5200.main_pri_1));
    338   reg  += (irqLine >> 3);
     340  reg = (uint32_t *) (&(mpc5200.main_pri_1));
     341  reg += (irqLine >> 3);
    339342  *reg &= ~(15 << (28 - (prio_index_offset << 2)));
    340343}
    341344
    342 
    343 static inline void BSP_disable_crit_irq_at_siu(
    344   const rtems_irq_symbolic_name irqLine
    345 )
     345static inline void BSP_disable_crit_irq_at_siu( rtems_vector_number
     346                                               irqLine)
    346347{
    347348  uint8_t prio_index_offset;
     
    351352
    352353  /* reset critical int priority to lowest level (reset value) */
    353   reg = (uint32_t *)(&(mpc5200.crit_pri_main_mask));
     354  reg = (uint32_t *) (&(mpc5200.crit_pri_main_mask));
    354355  *reg &= ~(3 << (30 - (prio_index_offset << 1)));
    355356
     
    360361}
    361362
    362 
    363363/*
    364  * ------------------------ RTEMS Irq helper functions ----------------
     364 * This function enables a given siu interrupt
    365365 */
    366 
    367 
    368 /*
    369  * This function check that the value given for the irq line
    370  * is valid.
    371  */
    372 static int isValidInterrupt(int irq)
    373 {
    374   if ( (irq < BSP_LOWEST_OFFSET) || (irq > BSP_MAX_OFFSET) )
    375     return 0;
    376   return 1;
    377 }
    378 
    379 
    380  /*
    381   * This function enables a given siu interrupt
    382   */
    383 int BSP_irq_enable_at_siu(const rtems_irq_symbolic_name irqLine)
    384 {
    385   int base_index;
    386 
    387   if (is_siu_irq(irqLine)) {
    388     if ((base_index = get_siu_irq_base_index(irqLine)) != -1) {
    389 
    390       switch(base_index) {
    391         case BSP_PER_IRQ_LOWEST_OFFSET:
    392           BSP_enable_per_irq_at_siu(irqLine);
    393           break;
    394         case BSP_MAIN_IRQ_LOWEST_OFFSET:
    395           BSP_enable_main_irq_at_siu(irqLine);
    396           break;
    397         case BSP_CRIT_IRQ_LOWEST_OFFSET:
    398           BSP_enable_crit_irq_at_siu(irqLine);
    399           break;
    400         default:
    401           printk("No valid base index\n");
    402           break;
    403       }
     366rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number irqLine)
     367{
     368  int base_index = get_siu_irq_base_index( irqLine);
     369
     370  if (is_siu_irq( irqLine)) {
     371    rtems_interrupt_level level;
     372
     373    rtems_interrupt_disable( level);
     374
     375    switch (base_index) {
     376      case BSP_PER_IRQ_LOWEST_OFFSET:
     377        BSP_enable_per_irq_at_siu( irqLine);
     378        break;
     379      case BSP_MAIN_IRQ_LOWEST_OFFSET:
     380        BSP_enable_main_irq_at_siu( irqLine);
     381        break;
     382      case BSP_CRIT_IRQ_LOWEST_OFFSET:
     383        BSP_enable_crit_irq_at_siu( irqLine);
     384        break;
     385      default:
     386        rtems_interrupt_enable( level);
     387        printk( "No valid base index\n");
     388        return RTEMS_INVALID_NUMBER;
    404389    }
    405   }
    406   return 0;
     390
     391    rtems_interrupt_enable( level);
     392  }
     393
     394  return RTEMS_SUCCESSFUL;
    407395}
    408396
     
    410398 * This function disables a given siu interrupt
    411399 */
    412 int BSP_irq_disable_at_siu(const rtems_irq_symbolic_name irqLine)
    413 {
    414   int base_index;
    415 
    416   if ( (base_index = get_siu_irq_base_index(irqLine)) == -1)
    417     return 1;
    418 
    419   switch(base_index) {
    420     case BSP_PER_IRQ_LOWEST_OFFSET:
    421       BSP_disable_per_irq_at_siu(irqLine);
    422       break;
    423     case BSP_MAIN_IRQ_LOWEST_OFFSET:
    424       BSP_disable_main_irq_at_siu(irqLine);
    425       break;
    426     case BSP_CRIT_IRQ_LOWEST_OFFSET:
    427       BSP_disable_crit_irq_at_siu(irqLine);
    428       break;
    429     default:
    430       printk("No valid base index\n");
    431       break;
    432   }
    433   return 0;
    434 }
    435 
    436 
    437 /*
    438  * --------------------- RTEMS Single Irq Handler Mngt Routines -------------
    439  */
    440 
    441  /*
    442   * This function removes the default entry and installs a device
    443   * interrupt handler
    444   */
    445 int BSP_install_rtems_irq_handler (const rtems_irq_connect_data* irq)
    446 {
    447   rtems_interrupt_level level;
    448 
    449   if (!isValidInterrupt(irq->name)) {
    450     printk("not a valid interrupt\n");
    451     return 0;
    452   }
    453 
    454   /*
    455    * Check if default handler is actually connected. If not issue an error.
    456    * RATIONALE : to always have the same transition by forcing the user
    457    * to get the previous handler before accepting to disconnect.
    458    */
    459   if (rtems_hdl_tbl[irq->name].hdl != default_rtems_entry.hdl) {
    460     printk( "Default handler not there\n" );
    461     return 0;
    462   }
    463 
    464   rtems_interrupt_disable(level);
    465 
    466   /*
    467    * store the data provided by user
    468    */
    469   rtems_hdl_tbl[irq->name] = *irq;
    470 
    471   if (is_siu_irq(irq->name)) {
    472     /*
    473      * Enable interrupt at siu level
    474      */
    475     BSP_irq_enable_at_siu(irq->name);
    476   } else {
    477     if (is_processor_irq(irq->name)) {
    478       /*
    479        * Should Enable exception at processor level but not needed.
    480        * Will restore EE flags at the end of the routine anyway.
    481        */
    482     } else {
    483       printk("not a valid interrupt\n");
    484       return 0;
     400rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number irqLine)
     401{
     402  int base_index = get_siu_irq_base_index( irqLine);
     403
     404  if (is_siu_irq( irqLine)) {
     405    rtems_interrupt_level level;
     406
     407    rtems_interrupt_disable( level);
     408
     409    switch (base_index) {
     410      case BSP_PER_IRQ_LOWEST_OFFSET:
     411        BSP_disable_per_irq_at_siu( irqLine);
     412        break;
     413      case BSP_MAIN_IRQ_LOWEST_OFFSET:
     414        BSP_disable_main_irq_at_siu( irqLine);
     415        break;
     416      case BSP_CRIT_IRQ_LOWEST_OFFSET:
     417        BSP_disable_crit_irq_at_siu( irqLine);
     418        break;
     419      default:
     420        rtems_interrupt_enable( level);
     421        printk( "No valid base index\n");
     422        return RTEMS_INVALID_NUMBER;
    485423    }
    486   }
    487 
    488   /*
    489    * Enable interrupt on device
    490    */
    491   if (irq->on)
    492     irq->on(irq);
    493 
    494   rtems_interrupt_enable(level);
    495   return 1;
    496 }
    497 
    498 
    499  /*
    500   * This function procures the current interrupt handler
    501   */
    502 int BSP_get_current_rtems_irq_handler (rtems_irq_connect_data* irq)
    503 {
    504   if (!isValidInterrupt(irq->name)) {
    505     return 0;
    506   }
    507   *irq = rtems_hdl_tbl[irq->name];
    508   return 1;
    509 }
    510 
    511 
    512  /*
    513   * This function removes a device interrupt handler and restores
    514   * the default entry
    515   */
    516 int BSP_remove_rtems_irq_handler (const rtems_irq_connect_data* irq)
    517 {
    518   rtems_interrupt_level level;
    519 
    520   if (!isValidInterrupt(irq->name)) {
    521     return 0;
    522   }
    523 
    524   /*
    525    * Check if default handler is actually connected. If not issue an error.
    526    * RATIONALE : to always have the same transition by forcing the user
    527    * to get the previous handler before accepting to disconnect.
    528    */
    529   if (rtems_hdl_tbl[irq->name].hdl != irq->hdl) {
    530     return 0;
    531   }
    532 
    533   rtems_interrupt_disable(level);
    534 
    535   if (is_siu_irq(irq->name)) {
    536     /*
    537      * disable interrupt at PIC level
    538      */
    539     BSP_irq_disable_at_siu(irq->name);
    540   }
    541 
    542   if (is_processor_irq(irq->name)) {
    543     /*
    544      * disable exception at processor level
    545      */
    546   }
    547 
    548   /*
    549    * Disable interrupt on device
    550    */
    551   if (irq->off)
    552     irq->off(irq);
    553 
    554   /*
    555    * restore the default irq value
    556    */
    557   rtems_hdl_tbl[irq->name] = default_rtems_entry;
    558 
    559   rtems_interrupt_enable(level);
    560 
    561   return 1;
    562 }
    563 
    564 
    565 /*
    566  * --------------------- RTEMS Global Irq Handler Mngt Routines -------------
    567  */
    568 
    569 /*
    570  * This function set up interrupt management dependent on the
    571  * given configuration
    572  */
    573 int BSP_rtems_irq_mngt_set(rtems_irq_global_settings* config)
    574 {
    575   int                   i;
    576   rtems_interrupt_level level;
    577 
    578   /*
    579    * Store various code accelerators
    580    */
    581   internal_config   = config;
    582   default_rtems_entry   = config->defaultEntry;
    583   rtems_hdl_tbl   = config->irqHdlTbl;
    584 
    585   rtems_interrupt_disable(level);
    586 
    587   /*
    588    * start with SIU IRQs
    589    */
    590   for (i=BSP_SIU_IRQ_LOWEST_OFFSET;
    591        i < BSP_SIU_IRQ_LOWEST_OFFSET + BSP_SIU_IRQ_NUMBER ;
    592        i++) {
    593 
    594     if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
    595       BSP_irq_enable_at_siu(i);
    596       if (rtems_hdl_tbl[i].on)
    597         rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
    598 
    599     } else {
    600       if (rtems_hdl_tbl[i].off)
    601         rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
    602       BSP_irq_disable_at_siu(i);
    603     }
    604   }
    605 
    606   /*
    607    * finish with Processor exceptions handled like IRQs
    608    */
    609   for (i=BSP_PROCESSOR_IRQ_LOWEST_OFFSET;
    610        i < BSP_PROCESSOR_IRQ_LOWEST_OFFSET + BSP_PROCESSOR_IRQ_NUMBER;
    611        i++) {
    612 
    613     if (rtems_hdl_tbl[i].hdl != default_rtems_entry.hdl) {
    614       if (rtems_hdl_tbl[i].on)
    615         rtems_hdl_tbl[i].on(&rtems_hdl_tbl[i]);
    616 
    617     } else {
    618       if (rtems_hdl_tbl[i].off)
    619         rtems_hdl_tbl[i].off(&rtems_hdl_tbl[i]);
    620     }
    621   }
    622 
    623   rtems_interrupt_enable(level);
    624   return 1;
    625 }
    626 
    627 
    628 int BSP_rtems_irq_mngt_get(rtems_irq_global_settings** config)
    629 {
    630   *config = internal_config;
    631   return 0;
     424
     425    rtems_interrupt_enable( level);
     426  }
     427
     428  return RTEMS_SUCCESSFUL;
    632429}
    633430
    634431#if (BENCHMARK_IRQ_PROCESSING == 0)
    635 void BSP_IRQ_Benchmarking_Reset(void)
    636 {
    637 }
    638 void BSP_IRQ_Benchmarking_Report(void)
     432void BSP_IRQ_Benchmarking_Reset( void)
     433{
     434}
     435void BSP_IRQ_Benchmarking_Report( void)
    639436{
    640437}
     
    645442uint32_t BSP_ISR_Count;
    646443uint32_t BSP_Worst_ISR;
     444
    647445#define BSP_COUNTED_IRQ 16
    648 uint32_t BSP_ISR_Count_Per[BSP_COUNTED_IRQ + 1];
    649 
    650 void BSP_IRQ_Benchmarking_Reset(void)
     446uint32_t BSP_ISR_Count_Per [BSP_COUNTED_IRQ + 1];
     447
     448void BSP_IRQ_Benchmarking_Reset( void)
    651449{
    652450  int i;
     451
    653452  BSP_Starting_TBR = PPC_Get_timebase_register();
    654453  BSP_Total_in_ISR = 0;
    655454  BSP_ISR_Count = 0;
    656455  BSP_Worst_ISR = 0;
    657   for ( i=0 ; i<BSP_COUNTED_IRQ ; i++ )
    658     BSP_ISR_Count_Per[i] = 0;
    659 }
    660 
    661 static const char * u64tostring(
    662   char *buffer,
    663   uint64_t v
    664 )
    665 {
    666   sprintf( buffer, "%lld cycles %lld usecs", v, (v / 33) );
     456  for (i = 0; i < BSP_COUNTED_IRQ; i++)
     457    BSP_ISR_Count_Per [i] = 0;
     458}
     459
     460static const char *u64tostring( char *buffer, uint64_t v)
     461{
     462  sprintf( buffer, "%lld cycles %lld usecs", v, (v / 33));
    667463  return buffer;
    668464}
    669465
    670 void BSP_IRQ_Benchmarking_Report(void)
     466void BSP_IRQ_Benchmarking_Report( void)
    671467{
    672468  uint64_t now;
    673   char buffer[96];
     469  char buffer [96];
    674470  int i;
    675471
    676472  now = PPC_Get_timebase_register();
    677   printk( "Started at: %s\n", u64tostring(buffer, BSP_Starting_TBR) );
    678   printk( "Current   : %s\n", u64tostring(buffer, now) );
    679   printk( "System up : %s\n", u64tostring(buffer, now - BSP_Starting_TBR) );
    680   printk( "ISRs      : %d\n", BSP_ISR_Count );
    681   printk( "ISRs ran  : %s\n", u64tostring(buffer, BSP_Total_in_ISR) );
    682   printk( "Worst ISR : %s\n", u64tostring(buffer, BSP_Worst_ISR) );
    683   for ( i=0 ; i<BSP_COUNTED_IRQ ; i++ )
    684     printk( "IRQ %d: %d\n", i, BSP_ISR_Count_Per[i] );
    685   printk( "Ticks     : %d\n",  Clock_driver_ticks );
     473  printk( "Started at: %s\n", u64tostring( buffer, BSP_Starting_TBR));
     474  printk( "Current   : %s\n", u64tostring( buffer, now));
     475  printk( "System up : %s\n", u64tostring( buffer, now - BSP_Starting_TBR));
     476  printk( "ISRs      : %d\n", BSP_ISR_Count);
     477  printk( "ISRs ran  : %s\n", u64tostring( buffer, BSP_Total_in_ISR));
     478  printk( "Worst ISR : %s\n", u64tostring( buffer, BSP_Worst_ISR));
     479  for (i = 0; i < BSP_COUNTED_IRQ; i++)
     480    printk( "IRQ %d: %d\n", i, BSP_ISR_Count_Per [i]);
     481  printk( "Ticks     : %d\n", Clock_driver_ticks);
    686482}
    687483#endif
     
    690486 * High level IRQ handler called from shared_raw_irq_code_entry
    691487 */
    692 int C_dispatch_irq_handler (CPU_Interrupt_frame *frame, unsigned int excNum)
     488int C_dispatch_irq_handler( CPU_Interrupt_frame * frame, unsigned int excNum)
    693489{
    694490  register unsigned int irq;
    695   register unsigned int msr;
    696   register unsigned int new_msr;
    697491  register unsigned int pmce;
    698   register unsigned int crit_pri_main_mask, per_mask;
     492  register unsigned int crit_pri_main_mask,
     493    per_mask;
     494
     495  uint32_t msr;
     496
    699497#if (BENCHMARK_IRQ_PROCESSING == 1)
    700   uint64_t start, stop, thisTime;
     498  uint64_t start,
     499    stop,
     500    thisTime;
    701501
    702502  start = PPC_Get_timebase_register();
    703503  BSP_ISR_Count++;
    704   if ( excNum < BSP_COUNTED_IRQ )
    705     BSP_ISR_Count_Per[excNum]++;
     504  if (excNum < BSP_COUNTED_IRQ)
     505    BSP_ISR_Count_Per [excNum]++;
    706506  else
    707507    printk( "not counting %d\n", excNum);
     
    709509
    710510  switch (excNum) {
    711     /*
    712      * Handle decrementer interrupt
    713      */
     511      /*
     512       * Handle decrementer interrupt
     513       */
    714514    case ASM_DEC_VECTOR:
    715515
    716       /* call the module specific handler and pass the specific handler */
    717       rtems_hdl_tbl[BSP_DECREMENTER].hdl(0);
     516      /* Dispatch interrupt handlers */
     517      bsp_interrupt_handler_dispatch( BSP_DECREMENTER);
    718518
    719519      break;
     
    722522
    723523      /* get the content of main interrupt status register */
    724       pmce =  mpc5200.pmce;
     524      pmce = mpc5200.pmce;
    725525
    726526      /* main interrupts may be routed to SMI, see bit SMI/INT select
    727527       * bit in main int. priorities
    728528       */
    729       while (CHK_MSE_STICKY(pmce)) {
     529      while (CHK_MSE_STICKY( pmce)) {
    730530
    731531        /* check for main interrupt sources (hirarchical order)
    732532         * -> LO_int indicates peripheral sources
    733533         */
    734         if (CHK_MSE_STICKY(pmce)) {
     534        if (CHK_MSE_STICKY( pmce)) {
    735535          /* get source of main interrupt */
    736           irq = MSE_SOURCE(pmce);
    737           switch(irq) {
    738 
    739             /* irq1-3, RTC, GPIO, TMR0-7 detected (attention:
    740              * slice timer 2 is always routed to SMI)
    741              */
    742             case 0: /* slice timer 2 */
     536          irq = MSE_SOURCE( pmce);
     537          switch (irq) {
     538
     539              /* irq1-3, RTC, GPIO, TMR0-7 detected (attention:
     540               * slice timer 2 is always routed to SMI)
     541               */
     542            case 0:            /* slice timer 2 */
    743543            case 1:
    744544            case 2:
     
    758558
    759559              /* add proper offset for main interrupts in
    760                * the siu handler array
    761                */
    762               irq += BSP_MAIN_IRQ_LOWEST_OFFSET;
     560               * the siu handler array
     561               */
     562              irq += BSP_MAIN_IRQ_LOWEST_OFFSET;
    763563
    764564              /* save original mask and disable all lower
    765                * priorized main interrupts
    766                */
    767               crit_pri_main_mask = mpc5200.crit_pri_main_mask;
    768               mpc5200.crit_pri_main_mask |= irqMaskTable[irq];
     565               * priorized main interrupts
     566               */
     567              crit_pri_main_mask = mpc5200.crit_pri_main_mask;
     568              mpc5200.crit_pri_main_mask |= irqMaskTable [irq];
    769569
    770570#if (ALLOW_IRQ_NESTING == 1)
    771571              /* enable interrupt nesting */
    772               _CPU_MSR_GET(msr);
    773               new_msr = msr | MSR_EE;
    774               _CPU_MSR_SET(new_msr);
    775 #endif
    776 
    777               /* call the module specific handler and pass the
    778                * specific handler
    779                */
    780               rtems_hdl_tbl[irq].hdl(0);
     572              msr = ppc_external_exceptions_enable();
     573#endif
     574
     575              /* Dispatch interrupt handlers */
     576              bsp_interrupt_handler_dispatch( irq);
    781577
    782578#if (ALLOW_IRQ_NESTING == 1)
    783579              /* disable interrupt nesting */
    784               _CPU_MSR_SET(msr);
     580              ppc_external_exceptions_disable( msr);
    785581#endif
    786582
     
    790586              break;
    791587
    792             /* peripheral LO_int interrupt source detected */
     588              /* peripheral LO_int interrupt source detected */
    793589            case 4:
    794590
    795591              /* check for valid peripheral interrupt source */
    796               if (CHK_PSE_STICKY(pmce)) {
     592              if (CHK_PSE_STICKY( pmce)) {
    797593                /* get source of peripheral interrupt */
    798                 irq = PSE_SOURCE(pmce);
    799 
    800                 /* add proper offset for peripheral interrupts
    801                 * in the siu handler array
    802                 */
    803                 irq += BSP_PER_IRQ_LOWEST_OFFSET;
    804 
    805                 /* save original mask and disable all lower
    806                 * priorized main interrupts
    807                 */
    808                 per_mask =  mpc5200.per_mask;
    809                 mpc5200.per_mask |= irqMaskTable[irq];
     594                irq = PSE_SOURCE( pmce);
     595
     596                /* add proper offset for peripheral interrupts
     597                * in the siu handler array
     598                */
     599                irq += BSP_PER_IRQ_LOWEST_OFFSET;
     600
     601                /* save original mask and disable all lower
     602                * priorized main interrupts
     603                */
     604                per_mask = mpc5200.per_mask;
     605                mpc5200.per_mask |= irqMaskTable [irq];
    810606
    811607#if (ALLOW_IRQ_NESTING == 1)
    812608                /* enable interrupt nesting */
    813                 _CPU_MSR_GET(msr);
    814                 new_msr = msr | MSR_EE;
    815                 _CPU_MSR_SET(new_msr);
    816 #endif
    817 
    818                 /* call the module specific handler and pass
    819                  * the specific handler
    820                  */
    821                 rtems_hdl_tbl[irq].hdl(0);
     609                msr = ppc_external_exceptions_enable();
     610#endif
     611
     612                /* Dispatch interrupt handlers */
     613                bsp_interrupt_handler_dispatch( irq);
    822614
    823615#if (ALLOW_IRQ_NESTING == 1)
    824                 /* disable interrupt nesting */
    825                 _CPU_MSR_SET(msr);
    826 #endif
    827 
    828                 /* restore original interrupt mask */
    829                 mpc5200.per_mask = per_mask;
    830 
    831                 /* force re-evaluation of peripheral interrupts */
    832                 CLR_PSE_STICKY(mpc5200.pmce);
    833               } else {
     616                /* disable interrupt nesting */
     617                ppc_external_exceptions_disable( msr);
     618#endif
     619
     620                /* restore original interrupt mask */
     621                mpc5200.per_mask = per_mask;
     622
     623                /* force re-evaluation of peripheral interrupts */
     624                CLR_PSE_STICKY( mpc5200.pmce);
     625              } else {
    834626                /* this case may not occur: no valid peripheral
    835                 * interrupt source
    836                 */
    837                 printk("No valid peripheral LO_int interrupt source\n");
    838               }
     627                * interrupt source
     628                */
     629                printk( "No valid peripheral LO_int interrupt source\n");
     630              }
    839631              break;
    840632              /* error: unknown interrupt source */
    841633            default:
    842               printk("Unknown peripheral LO_int interrupt source\n");
     634              printk( "Unknown peripheral LO_int interrupt source\n");
    843635              break;
    844636          }
    845637
    846           /* force re-evaluation of main interrupts */
    847           CLR_MSE_STICKY(mpc5200.pmce);
    848         }
     638          /* force re-evaluation of main interrupts */
     639          CLR_MSE_STICKY( mpc5200.pmce);
     640        }
    849641
    850642        /* get the content of main interrupt status register */
    851         pmce = mpc5200.pmce;
     643        pmce = mpc5200.pmce;
    852644      }
    853645      break;
     
    855647    case ASM_EXT_VECTOR:
    856648      /* get the content of main interrupt status register */
    857       pmce =  mpc5200.pmce;
     649      pmce = mpc5200.pmce;
    858650
    859651      /* critical interrupts may be routed to the core_int
    860652       * dependent on premature initialization, see bit 31 (CEbsH)
    861653       */
    862       while((CHK_CE_SHADOW(pmce) && CHK_CSE_STICKY(pmce)) ||
    863              CHK_MSE_STICKY(pmce) || CHK_PSE_STICKY(pmce) ) {
     654      while ((CHK_CE_SHADOW( pmce) && CHK_CSE_STICKY( pmce))
     655             || CHK_MSE_STICKY( pmce) || CHK_PSE_STICKY( pmce)) {
    864656
    865657        /* first: check for critical interrupt sources (hierarchical order)
    866         * -> HI_int indicates peripheral sources
    867         */
    868         if (CHK_CE_SHADOW(pmce) && CHK_CSE_STICKY(pmce)) {
     658        * -> HI_int indicates peripheral sources
     659        */
     660        if (CHK_CE_SHADOW( pmce) && CHK_CSE_STICKY( pmce)) {
    869661          /* get source of critical interrupt */
    870           irq = CSE_SOURCE(pmce);
    871           switch(irq) {
    872             /* irq0, slice timer 1 or ccs wakeup detected */
     662          irq = CSE_SOURCE( pmce);
     663          switch (irq) {
     664              /* irq0, slice timer 1 or ccs wakeup detected */
    873665            case 0:
    874666            case 1:
     
    876668
    877669              /* add proper offset for critical interrupts in the siu
    878                * handler array */
    879               irq += BSP_CRIT_IRQ_LOWEST_OFFSET;
    880 
    881               /* call the module specific handler and pass the
    882                * specific handler */
    883               rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle);
     670               * handler array */
     671              irq += BSP_CRIT_IRQ_LOWEST_OFFSET;
     672
     673              /* Dispatch interrupt handlers */
     674              bsp_interrupt_handler_dispatch( irq);
     675
    884676              break;
    885677
    886             /* peripheral HI_int interrupt source detected */
     678              /* peripheral HI_int interrupt source detected */
    887679            case 2:
    888680              /* check for valid peripheral interrupt source */
    889               if (CHK_PSE_STICKY(pmce)) {
     681              if (CHK_PSE_STICKY( pmce)) {
    890682                /* get source of peripheral interrupt */
    891                 irq = PSE_SOURCE(pmce);
     683                irq = PSE_SOURCE( pmce);
    892684
    893685                /* add proper offset for peripheral interrupts in the
     
    897689                /* save original mask and disable all lower
    898690                 * priorized main interrupts */
    899                 per_mask =  mpc5200.per_mask;
    900                 mpc5200.per_mask |= irqMaskTable[irq];
     691                per_mask = mpc5200.per_mask;
     692                mpc5200.per_mask |= irqMaskTable [irq];
    901693
    902694#if (ALLOW_IRQ_NESTING == 1)
    903695                /* enable interrupt nesting */
    904                 _CPU_MSR_GET(msr);
    905                 new_msr = msr | MSR_EE;
    906                 _CPU_MSR_SET(new_msr);
    907 #endif
    908 
    909                 /* call the module specific handler and pass the
    910                  * specific handler */
    911                 rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle);
     696                msr = ppc_external_exceptions_enable();
     697#endif
     698
     699                /* Dispatch interrupt handlers */
     700                bsp_interrupt_handler_dispatch( irq);
    912701
    913702#if (ALLOW_IRQ_NESTING == 1)
    914                 _CPU_MSR_SET(msr);
     703                /* disable interrupt nesting */
     704                ppc_external_exceptions_disable( msr);
    915705#endif
    916706
     
    919709
    920710                /* force re-evaluation of peripheral interrupts */
    921                 CLR_PSE_STICKY(mpc5200.pmce);
    922               } else {
    923                 /* this case may not occur: no valid peripheral
    924                 * interrupt source */
    925                 printk("No valid peripheral HI_int interrupt source\n");
    926               }
    927               break;
     711                CLR_PSE_STICKY( mpc5200.pmce);
     712              } else {
     713                /* this case may not occur: no valid peripheral
     714                * interrupt source */
     715                printk( "No valid peripheral HI_int interrupt source\n");
     716              }
     717              break;
    928718            default:
    929719              /* error: unknown interrupt source */
    930               printk("Unknown HI_int interrupt source\n");
     720              printk( "Unknown HI_int interrupt source\n");
    931721              break;
    932722          }
    933723          /* force re-evaluation of critical interrupts */
    934           CLR_CSE_STICKY(mpc5200.pmce);
     724          CLR_CSE_STICKY( mpc5200.pmce);
    935725        }
    936726
    937727        /* second: check for main interrupt sources (hierarchical order)
    938728         * -> LO_int indicates peripheral sources */
    939         if (CHK_MSE_STICKY(pmce)) {
     729        if (CHK_MSE_STICKY( pmce)) {
    940730          /* get source of main interrupt */
    941           irq = MSE_SOURCE(pmce);
     731          irq = MSE_SOURCE( pmce);
    942732
    943733          switch (irq) {
    944734
    945             /* irq1-3, RTC, GPIO, TMR0-7 detected (attention: slice timer
    946              * 2 is always routed to SMI) */
     735              /* irq1-3, RTC, GPIO, TMR0-7 detected (attention: slice timer
     736               * 2 is always routed to SMI) */
    947737            case 1:
    948738            case 2:
     
    961751            case 16:
    962752              /* add proper offset for main interrupts in the siu
    963                * handler array */
     753               * handler array */
    964754              irq += BSP_MAIN_IRQ_LOWEST_OFFSET;
    965755
    966               /* save original mask and disable all lower priorized
    967                * main interrupts*/
    968               crit_pri_main_mask = mpc5200.crit_pri_main_mask;
    969               mpc5200.crit_pri_main_mask |= irqMaskTable[irq];
     756              /* save original mask and disable all lower priorized
     757               * main interrupts*/
     758              crit_pri_main_mask = mpc5200.crit_pri_main_mask;
     759              mpc5200.crit_pri_main_mask |= irqMaskTable [irq];
    970760
    971761#if (ALLOW_IRQ_NESTING == 1)
    972               /* enable interrupt nesting */
    973               _CPU_MSR_GET(msr);
    974               new_msr = msr | MSR_EE;
    975               _CPU_MSR_SET(new_msr);
    976 #endif
    977 
    978               /* call the module specific handler and pass the specific
    979                * handler */
    980               rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle);
     762              /* enable interrupt nesting */
     763              msr = ppc_external_exceptions_enable();
     764#endif
     765
     766              /* Dispatch interrupt handlers */
     767              bsp_interrupt_handler_dispatch( irq);
    981768
    982769#if (ALLOW_IRQ_NESTING == 1)
    983               /* disable interrupt nesting */
    984               _CPU_MSR_SET(msr);
    985 #endif
    986 
    987               /* restore original interrupt mask */
    988               mpc5200.crit_pri_main_mask = crit_pri_main_mask;
    989               break;
    990 
    991           /* peripheral LO_int interrupt source detected */
    992             case 4:
    993               /* check for valid peripheral interrupt source */
    994               if (CHK_PSE_STICKY(pmce)) {
    995                 /* get source of peripheral interrupt */
    996                 irq = PSE_SOURCE(pmce);
    997 
    998                 /* add proper offset for peripheral interrupts in the siu
    999                 * handler array */
    1000                 irq += BSP_PER_IRQ_LOWEST_OFFSET;
    1001 
    1002                 /* save original mask and disable all lower priorized main
    1003                 * interrupts */
    1004                 per_mask = mpc5200.per_mask;
    1005                 mpc5200.per_mask |= irqMaskTable[irq];
     770              /* disable interrupt nesting */
     771              ppc_external_exceptions_disable( msr);
     772#endif
     773
     774              /* restore original interrupt mask */
     775              mpc5200.crit_pri_main_mask = crit_pri_main_mask;
     776              break;
     777
     778              /* peripheral LO_int interrupt source detected */
     779            case 4:
     780              /* check for valid peripheral interrupt source */
     781              if (CHK_PSE_STICKY( pmce)) {
     782                /* get source of peripheral interrupt */
     783                irq = PSE_SOURCE( pmce);
     784
     785                /* add proper offset for peripheral interrupts in the siu
     786                * handler array */
     787                irq += BSP_PER_IRQ_LOWEST_OFFSET;
     788
     789                /* save original mask and disable all lower priorized main
     790                * interrupts */
     791                per_mask = mpc5200.per_mask;
     792                mpc5200.per_mask |= irqMaskTable [irq];
    1006793
    1007794#if (ALLOW_IRQ_NESTING == 1)
    1008                 /* enable interrupt nesting */
    1009                 _CPU_MSR_GET(msr);
    1010                 new_msr = msr | MSR_EE;
    1011                 _CPU_MSR_SET(new_msr);
    1012 #endif
    1013 
    1014                 /* call the module specific handler and pass the
    1015                  * specific handler */
    1016                 rtems_hdl_tbl[irq].hdl(rtems_hdl_tbl[irq].handle);
     795                /* enable interrupt nesting */
     796                msr = ppc_external_exceptions_enable();
     797#endif
     798
     799                /* Dispatch interrupt handlers */
     800                bsp_interrupt_handler_dispatch( irq);
    1017801
    1018802#if (ALLOW_IRQ_NESTING == 1)
    1019                 /* disable interrupt nesting */
    1020                 _CPU_MSR_SET(msr);
    1021 #endif
    1022 
    1023                 /* restore original interrupt mask */
    1024                 mpc5200.per_mask = per_mask;
    1025 
    1026                 /* force re-evaluation of peripheral interrupts */
    1027                 CLR_PSE_STICKY(mpc5200.pmce);
    1028               } else {
    1029                 /* this case may not occur: no valid peripheral
    1030                 * interrupt source */
    1031                 printk("No valid peripheral LO_int interrupt source\n");
    1032               }
     803                /* disable interrupt nesting */
     804                ppc_external_exceptions_disable( msr);
     805#endif
     806
     807                /* restore original interrupt mask */
     808                mpc5200.per_mask = per_mask;
     809
     810                /* force re-evaluation of peripheral interrupts */
     811                CLR_PSE_STICKY( mpc5200.pmce);
     812              } else {
     813                /* this case may not occur: no valid peripheral
     814                * interrupt source */
     815                printk( "No valid peripheral LO_int interrupt source\n");
     816              }
    1033817              break;
    1034818
    1035             /* error: unknown interrupt source */
    1036             default:
    1037               printk("Unknown peripheral LO_int interrupt source\n");
    1038               break;
     819              /* error: unknown interrupt source */
     820            default:
     821              printk( "Unknown peripheral LO_int interrupt source\n");
     822              break;
    1039823          }
    1040           /* force re-evaluation of main interrupts */
    1041           CLR_MSE_STICKY(mpc5200.pmce);
     824          /* force re-evaluation of main interrupts */
     825          CLR_MSE_STICKY( mpc5200.pmce);
    1042826        }
    1043827        /* get the content of main interrupt status register */
    1044         pmce =  mpc5200.pmce;
     828        pmce = mpc5200.pmce;
    1045829      }
    1046830      break;
    1047831
    1048832    default:
    1049       printk("Unknown processor exception\n");
     833      printk( "Unknown processor exception\n");
    1050834      break;
    1051835
    1052   } /* end of switch(excNum) */
     836  }                             /* end of switch( excNum) */
     837
    1053838#if (BENCHMARK_IRQ_PROCESSING == 1)
    1054839  stop = PPC_Get_timebase_register();
    1055840  thisTime = stop - start;
    1056841  BSP_Total_in_ISR += thisTime;
    1057   if ( thisTime > BSP_Worst_ISR )
     842  if (thisTime > BSP_Worst_ISR)
    1058843    BSP_Worst_ISR = thisTime;
    1059844#endif
     845
    1060846  return 0;
    1061847}
    1062848
    1063 
    1064 void _ThreadProcessSignalsFromIrq (BSP_Exception_frame* ctx)
    1065 {
    1066   /*
    1067    * Process pending signals that have not already been
    1068    * processed by _Thread_Displatch. This happens quite
    1069    * unfrequently : the ISR must have posted an action
    1070    * to the current running thread.
    1071    */
    1072   if ( _Thread_Do_post_task_switch_extension ||
    1073        _Thread_Executing->do_post_task_switch_extension )
    1074     {
    1075 
    1076     _Thread_Executing->do_post_task_switch_extension = FALSE;
    1077     _API_extensions_Run_postswitch();
    1078 
     849/*
     850 * setup irqMaskTable to support a priorized/nested interrupt environment
     851 */
     852void setup_irqMaskTable( void)
     853{
     854  rtems_irq_prio prio = 0;
     855  uint32_t i = 0,
     856    j = 0,
     857    mask = 0;
     858
     859  /* set up the priority dependent masks for peripheral interrupts */
     860  for (i = BSP_PER_IRQ_LOWEST_OFFSET; i <= BSP_PER_IRQ_MAX_OFFSET; i++) {
     861    prio = irqPrioTable [i];
     862    mask = 0;
     863
     864    for (j = BSP_PER_IRQ_LOWEST_OFFSET; j <= BSP_PER_IRQ_MAX_OFFSET; j++) {
     865      if (prio > irqPrioTable [j]) {
     866        mask |= (1 << (31 - j + BSP_PER_IRQ_LOWEST_OFFSET));
     867      }
     868
     869      if ((prio == irqPrioTable [j]) && (j >= i)) {
     870        mask |= (1 << (31 - j + BSP_PER_IRQ_LOWEST_OFFSET));
     871      }
    1079872    }
    1080   /*
    1081    * I plan to process other thread related events here.
    1082    * This will include DEBUG session requested from keyboard...
    1083    */
    1084 }
     873
     874    irqMaskTable [i] = mask;
     875  }
     876
     877  /* set up the priority dependent masks for main interrupts */
     878  for (i = BSP_MAIN_IRQ_LOWEST_OFFSET; i <= BSP_MAIN_IRQ_MAX_OFFSET; i++) {
     879    prio = irqPrioTable [i];
     880    mask = 0;
     881
     882    for (j = BSP_MAIN_IRQ_LOWEST_OFFSET; j <= BSP_MAIN_IRQ_MAX_OFFSET; j++) {
     883      if (prio > irqPrioTable [j]) {
     884        mask |= (1 << (16 - j + BSP_MAIN_IRQ_LOWEST_OFFSET));
     885      }
     886
     887      if ((prio == irqPrioTable [j]) && (j >= i)) {
     888        mask |= (1 << (16 - j + BSP_MAIN_IRQ_LOWEST_OFFSET));
     889      }
     890    }
     891
     892    irqMaskTable [i] = mask;
     893  }
     894}
     895
     896/*
     897 * Initialize MPC5x00 SIU interrupt management
     898 */
     899void BSP_SIU_irq_init( void)
     900{
     901
     902  /* disable all peripheral interrupts */
     903  mpc5200.per_mask = 0xFFFFFC00;
     904
     905  /* peripheral interrupt priorities according to reset value */
     906  mpc5200.per_pri_1 = 0xF0000000;
     907  mpc5200.per_pri_2 = 0x00000000;
     908  mpc5200.per_pri_3 = 0x00000000;
     909
     910  /* disable external interrupts IRQ0-4 / critical interrupts are routed to core_int */
     911  mpc5200.ext_en_type = 0x0F000001;
     912
     913  /* disable main interrupts / crit. int. priorities according to reset values */
     914  mpc5200.crit_pri_main_mask = 0x0001FFFF;
     915
     916  /* main priorities according to reset value */
     917  mpc5200.main_pri_1 = 0;
     918  mpc5200.main_pri_2 = 0;
     919
     920  /* reset all status indicators */
     921  mpc5200.csa = 0x0001FFFF;
     922  mpc5200.msa = 0x0001FFFF;
     923  mpc5200.psa = 0x003FFFFF;
     924  mpc5200.psa_be = 0x03000000;
     925
     926  setup_irqMaskTable();
     927}
     928
     929rtems_status_code bsp_interrupt_facility_initialize( void)
     930{
     931  BSP_SIU_irq_init();
     932
     933  /* Install exception handler */
     934  if (ppc_exc_set_handler( ASM_EXT_VECTOR, C_dispatch_irq_handler)) {
     935    return RTEMS_IO_ERROR;
     936  }
     937  if (ppc_exc_set_handler( ASM_DEC_VECTOR, C_dispatch_irq_handler)) {
     938    return RTEMS_IO_ERROR;
     939  }
     940  if (ppc_exc_set_handler( ASM_E300_SYSMGMT_VECTOR, C_dispatch_irq_handler)) {
     941    return RTEMS_IO_ERROR;
     942  }
     943
     944  return RTEMS_SUCCESSFUL;
     945}
     946
     947void bsp_interrupt_handler_default( rtems_vector_number vector)
     948{
     949  if (vector != BSP_DECREMENTER) {
     950    printk( "Spurious interrupt: 0x%08x\n", vector);
     951  }
     952}
  • c/src/lib/libbsp/powerpc/gen5200/network_5200/network.c

    r9ac9883 r82bd8d9d  
    6666#include <netinet/if_ether.h>
    6767#include <bsp.h>
    68 #include "../irq/irq.h"
     68#include <bsp/irq.h>
    6969#include "../include/mpc5200.h"
    7070#include <net/if_var.h>
  • c/src/lib/libbsp/powerpc/gen5200/slicetimer/slicetimer.c

    r9ac9883 r82bd8d9d  
    100100#include <bsp.h>
    101101#include <rtems/bspIo.h>
    102 #include "../irq/irq.h"
     102#include <bsp/irq.h>
    103103
    104104#include <rtems.h>
     
    106106#include <rtems/libio.h>
    107107
    108 #include "../irq/irq.h"
     108#include <bsp/irq.h>
    109109#include "../include/mpc5200.h"
    110110#include "../slicetimer/slicetimer.h"
  • c/src/lib/libbsp/powerpc/gen5200/start/start.S

    r9ac9883 r82bd8d9d  
    9191/***********************************************************************/
    9292   
    93 #include <rtems/asm.h>
    9493#include <rtems/powerpc/cache.h>
    95 #include <rtems/powerpc/registers.h>
    96 #include "../include/mpc5200.h"
    97 #include "../include/bsp.h"
    98 
    99 /* Macro definitions to load a register with a 32-bit address.
    100    Both functions identically.  Sometimes one mnemonic is more
    101    appropriate than the other.
    102    reg          -> register to load
    103    value        -> value to be loaded
    104    LA  reg,value    ("Load Address")
    105    LWI reg,value    ("Load Word Immediate") */
    106 
    107 .macro LA reg, value
    108         lis \reg , \value@h
    109         ori \reg , \reg, \value@l
    110         sync
    111 .endm
    112 
    113 .macro LWI reg, value
    114         lis \reg , (\value)@h
    115         ori \reg , \reg, (\value)@l
    116         sync
    117 .endm
    118 
    119 /* Macro definitions to test, set or clear a single
    120    bit or bit pattern in a given 32bit GPR.
    121    reg1         -> register content to be tested
    122    reg2         -> 2nd register only needed for computation
    123    mask         -> any bit pattern */
    124 
    125 .macro  TSTBITS reg1, reg2, mask        /* Match is indicated by EQ=0 (CR) */
    126         LWI     \reg2, \mask            /* Unmatch is indicated by EQ=1 (CR) */
    127         and     \reg1, \reg1, \reg2
    128         cmplw   \reg1, \reg2
    129         sync
    130 .endm   
    131        
    132 .macro  SETBITS reg1, reg2, mask
    133         LWI     \reg2, \mask
    134         or      \reg1, \reg1, \reg2
    135         sync
    136 .endm
    137 
    138 .macro  CLRBITS reg1, reg2, mask
    139         LWI     \reg2, \mask
    140         andc    \reg1, \reg1, \reg2
    141         sync
    142 .endm
     94
     95#include <bsp.h>
     96#include <bsp/mpc5200.h>
    14397
    14498/* Some register offsets of MPC5x00 memory map registers */
     
    201155.set    CFG_VAL,                0x00000100
    202156
    203 .extern _bss_start
    204 .extern _bss_size
    205 .extern _data_start
    206 .extern _data_size
    207 .extern _text_start
    208 .extern _text_size
    209 /*.extern _s_got*/
    210157.extern boot_card
    211 .extern MBAR   
    212158
    213159.section ".entry" 
     
    263209#if defined(NEED_LOW_LEVEL_INIT)
    264210/* detect RAM/ROM startup (common for RAM/ROM startup) */
    265         LWI     r20, ROM_START                  /* set the relocation offset */
     211        LWI     r20, bsp_rom_start              /* set the relocation offset */
    266212       
    267213       
     
    296242
    297243        /* FIXME: map BOOT ROM into final location with CS0 registers */
    298         LWI     r30, ROM_START
     244        LWI     r30, bsp_rom_start
    299245        rlwinm  r30, r30,17,15,31
    300246        stw     r30, CS0STR(r31)                /* Set CS0STR */       
    301247                       
    302         lis     r30, ROM_END@h
    303         ori     r30, r30, ROM_END@l
     248        LWI     r30, bsp_rom_end
    304249       
    305250        rlwinm  r30, r30,17,15,31
     
    312257        /* jump to same code in final BOOT ROM location */
    313258        LWI     r30, reloc_in_CS0
    314         LWI     r29, RAM_START
     259        LWI     r29, bsp_ram_start
    315260        sub     r30,r30,r29
    316         LWI     r29, ROM_START
     261        LWI     r29, bsp_rom_start
    317262        add     r30,r30,r29
    318263        mtctr   r30
     
    326271       
    327272        /* init SDRAM */
    328         LWI     r30, RAM_START
    329         ori     r30,r30,0x1a                    /* size code: bank is 128MByte */
    330         stw     r30,SDRAMCS0(r31)               /* Set SDRAMCS0 */
    331 
    332         LWI     r30,(RAM_SIZE)>>1
    333         ori     r30,r30,0x1a                    /* size code: bank is 128MByte */
     273        LWI     r30, bsp_ram_start
     274        ori     r30, r30, 0x1a                  /* size code: bank is 128MByte */
     275        stw     r30, SDRAMCS0(r31)              /* Set SDRAMCS0 */
     276
     277        LWI     r30, bsp_ram_size
     278        srawi   r30, r30, 1
     279        ori     r30, r30, 0x1a                  /* size code: bank is 128MByte */
    334280        stw     r30, SDRAMCS1(r31)              /* Set SDRAMCS1 */
    335281       
     
    349295        stw     r30, ARBSNOOP(r31)              /* Set ARBSNOOP */     
    350296/* copy .text section from ROM to RAM location (unique for ROM startup) */
    351         LA      r30, _text_start                /* get start address of text section in RAM */
     297        LA      r30, bsp_section_text_start     /* get start address of text section in RAM */
    352298       
    353299       
     
    355301       
    356302       
    357         LA      r29, _text_start                /* get start address of text section in RAM */
    358        
    359 
    360         LA      r28, _text_size                 /* get size of RAM image */
     303        LA      r29, bsp_section_text_start     /* get start address of text section in RAM */
     304       
     305
     306        LA      r28, bsp_section_text_size      /* get size of RAM image */
    361307               
    362308       
     
    365311
    366312/* copy .data section from ROM to RAM location (unique for ROM startup) */
    367         LA      r30, _data_start                /* get start address of data section in RAM */
     313        LA      r30, bsp_section_data_start     /* get start address of data section in RAM */
    368314       
    369315               
     
    371317       
    372318               
    373         LA      r29, _data_start                /* get start address of data section in RAM */
    374        
    375        
    376         LA      r28, _data_size                 /* get size of RAM image */
     319        LA      r29, bsp_section_data_start     /* get start address of data section in RAM */
     320       
     321       
     322        LA      r28, bsp_section_data_size      /* get size of RAM image */
    377323               
    378324       
     
    426372skip_ROM_start:
    427373/* configure external DPRAM CS1 */
    428     LWI r30,0xFFFFFB10
    429         stw r30,CS1CONF(r31)
     374        LWI     r30, 0xFFFFFB10
     375        stw     r30, CS1CONF(r31)
    430376
    431377/* map external DPRAM (CS1) */
    432     LWI r30,(DPRAM_START>>16)
    433         stw r30,CS1STR(r31)
    434 
    435     LWI r30,((DPRAM_END)>>16)
    436         stw r30,CS1STP(r31)
     378        LWI     r30, bsp_dpram_start
     379        srawi   r30, r30, 16
     380        stw     r30, CS1STR(r31)
     381
     382        LWI     r30, bsp_dpram_end
     383        srawi   r30, r30, 16
     384        stw     r30, CS1STP(r31)
    437385
    438386        lwz     r30, ADREN(r31)                 /* get content of ADREN */
    439387                       
    440388        LWI     r29, ADREN_CS1_EN               /* unmask ADREN_CS1_EN */
    441         or      r30,r30,r29     
    442        
    443         stw     r30,ADREN(r31)                  /* enable CS1 */
     389        or      r30, r30,r29   
     390       
     391        stw     r30, ADREN(r31)                 /* enable CS1 */
    444392
    445393/* clear entire on chip SRAM (unique for ROM startup) */
    446394        lis     r30, (MBAR+ONCHIP_SRAM_OFFSET)@h        /* get start address of onchip SRAM */
    447         ori     r30,r30,(MBAR+ONCHIP_SRAM_OFFSET)@l
     395        ori     r30, r30,(MBAR+ONCHIP_SRAM_OFFSET)@l
    448396        LWI     r29, ONCHIP_SRAM_SIZE           /* get size of onchip SRAM */
    449397       
     
    452400#endif /* defined(BRS5L) */
    453401/* clear .bss section (unique for ROM startup) */
    454         LWI     r30, _bss_start                 /* get start address of bss section */
    455         LWI     r29, _bss_size                  /* get size of bss section */
     402        LWI     r30, bsp_section_bss_start      /* get start address of bss section */
     403        LWI     r29, bsp_section_bss_size       /* get size of bss section */
    456404       
    457405
     
    460408
    461409/* set stack pointer (common for RAM/ROM startup) */
    462         LA      r1, _text_start 
     410        LA      r1, bsp_section_text_start 
    463411        addi    r1, r1, -0x10                   /* Set up stack pointer = beginning of text section - 0x10 */
    464        
     412
     413        bl      __eabi                          /* Set up EABI and SYSV environment */
    465414     
    466415/* enable dynamic power management(common for RAM/ROM startup) */
     
    623572
    624573        li      r29, PPC_D_CACHE                /* 16 Kb data cache on 603e */
    625         LWI     r28, _text_start                /* Load base address (begin of RAM) */
     574        LWI     r28, bsp_section_text_start     /* Load base address (begin of RAM) */
    626575
    627576FID_DCache_loop_1:
     
    634583
    635584        li      r29, PPC_D_CACHE                /* 16 Kb data cache on 603e */
    636         LWI     r28, _text_start                /* Reload base address (begin of RAM) */
     585        LWI     r28, bsp_section_text_start     /* Reload base address (begin of RAM) */
    637586        xor     r27, r27, r27
    638587FID_DCache_loop_2:
     
    698647       
    699648#if 0   
    700         LA      r29, RAM_START
     649        LA      r29, bsp_ram_start
    701650        stw     r29, 0x0(r29)
    702651#endif 
  • c/src/lib/libbsp/powerpc/gen5200/startup/bspclean.c

    r9ac9883 r82bd8d9d  
    1515#include <rtems/bspIo.h>
    1616#include <bsp.h>
    17 #include <mpc5200.h>
     17#include <bsp/mpc5200.h>
     18#include <bsp/bootcard.h>
    1819
    1920extern int mpc5200_uart_pollRead(int minor);
  • c/src/lib/libbsp/powerpc/gen5200/startup/bspstart.c

    r9ac9883 r82bd8d9d  
    9797#warning The interrupt disable mask is now stored in SPRG0, please verify that this is compatible to this BSP (see also bootcard.c).
    9898
    99 #include <bsp.h>
     99#include <string.h>
    100100
    101101#include <rtems/libio.h>
    102102#include <rtems/libcsupport.h>
    103 #include <rtems/powerpc/powerpc.h>
    104103#include <rtems/score/thread.h>
    105104
    106 #include <rtems/bspIo.h>
    107 #include <libcpu/cpuIdent.h>
    108 #include <libcpu/spr.h>
    109 #include "../irq/irq.h"
    110 
    111 #include <string.h>
     105#include <libcpu/powerpc-utility.h>
     106#include <libcpu/raw_exception.h>
     107
     108#include <bsp.h>
     109#include <bsp/bootcard.h>
     110#include <bsp/ppc_exc_bspsupp.h>
     111
     112#include <bsp/irq.h>
    112113
    113114#if defined(HAS_UBOOT)
     
    115116bd_t uboot_bdinfo_copy;             /* will be overwritten with copy of bdinfo */
    116117#endif
    117 
    118 SPR_RW(SPRG1)
    119 
    120 extern unsigned long intrStackPtr;
    121118
    122119/*
     
    125122uint32_t   bsp_clicks_per_usec;
    126123
    127 /*
    128  *  Use the shared implementations of the following routines.
    129  *  Look in rtems/c/src/lib/libbsp/shared/bsplibc.c.
    130  */
    131 void bsp_libc_init( void *, uint32_t, int );
    132 extern void initialize_exceptions(void);
    133 extern void cpu_init(void);
    134 
    135124void BSP_panic(char *s)
    136125  {
     
    145134  }
    146135
    147 /*
    148  *  Function:   bsp_pretasking_hook
    149  *  Created:    95/03/10
    150  *
    151  *  Description:
    152  *      BSP pretasking hook.  Called just before drivers are initialized.
    153  *      Used to setup libc and install any BSP extensions.
    154  *
    155  *  NOTES:
    156  *      Must not use libc (to do io) from here, since drivers are
    157  *      not yet initialized.
    158  *
    159  */
    160 
    161 void
    162 bsp_pretasking_hook(void)
     136void bsp_get_work_area(
     137  void   **work_area_start,
     138  size_t  *work_area_size,
     139  void   **heap_start,
     140  size_t  *heap_size)
    163141{
    164   /*
    165    *  These are assigned addresses in the linkcmds file for the BSP. This
    166    *  approach is better than having these defined as manifest constants and
    167    *  compiled into the kernel, but it is still not ideal when dealing with
    168    *  multiprocessor configuration in which each board as a different memory
    169    *  map. A better place for defining these symbols might be the makefiles.
    170    *  Consideration should also be given to developing an approach in which
    171    *  the kernel and the application can be linked and burned into ROM
    172    *  independently of each other.
    173    */
    174 
    175 #if defined(HAS_UBOOT)
    176     extern unsigned char _HeapStart;
    177 
    178     bsp_libc_init( &_HeapStart,
    179                    uboot_bdinfo_ptr->bi_memstart
    180                    + uboot_bdinfo_ptr->bi_memsize
    181                    - (uint32_t)&_HeapStart
    182                    , 0 );
    183 #else
    184     extern unsigned char _HeapStart;
    185     extern unsigned char _HeapEnd;
    186 
    187     bsp_libc_init( &_HeapStart, &_HeapEnd - &_HeapStart, 0 );
    188 #endif
     142#ifdef HAS_UBOOT
     143  char *ram_end = (char *) uboot_bdinfo_ptr->bi_memstart +
     144                                 uboot_bdinfo_ptr->bi_memsize;
     145#else /* HAS_UBOOT */
     146  char *ram_end = bsp_ram_end;
     147#endif /* HAS_UBOOT */
     148
     149  *work_area_start = bsp_work_area_start;
     150  *work_area_size = ram_end - bsp_work_area_start;
     151  *heap_start = BSP_BOOTCARD_HEAP_USES_WORK_AREA;
     152  *heap_size = BSP_BOOTCARD_HEAP_SIZE_DEFAULT;
    189153}
    190154
     
    220184void bsp_start(void)
    221185{
    222   extern void *_WorkspaceBase;
    223186  ppc_cpu_id_t myCpu;
    224187  ppc_cpu_revision_t myCpuRevision;
    225   register unsigned char* intrStack;
    226188
    227189  /*
     
    247209  cpu_init();
    248210
    249   /*
    250    * Initialize some SPRG registers related to irq handling
    251    */
    252 
    253   intrStack = (((unsigned char*)&intrStackPtr) - PPC_MINIMUM_STACK_FRAME_SIZE);
    254 
    255   _write_SPRG1((unsigned int)intrStack);
    256 
    257211 bsp_clicks_per_usec    = (IPB_CLOCK/1000000);
    258 
    259  /*
    260   * Install our own set of exception vectors
    261   */
    262 
    263   initialize_exceptions();
    264212
    265213  /*
     
    273221  #endif
    274222
    275   /*
    276    *  Need to "allocate" the memory for the RTEMS Workspace and
    277    *  tell the RTEMS configuration where it is.  This memory is
    278    *  not malloc'ed.  It is just "pulled from the air".
    279    */
    280   Configuration.work_space_start = (void *)&_WorkspaceBase;
    281   #ifdef SHOW_MORE_INIT_SETTINGS
    282     printk( "workspace=%p\n", Configuration.work_space_start );
    283     printk( "workspace size=%d\n", Configuration.work_space_size );
    284   #endif
    285 
    286   /*
    287    * Initalize RTEMS IRQ system
    288    */
    289   BSP_rtems_irq_mng_init(0);
     223  /* Initialize exception handler */
     224  ppc_exc_cache_wb_check = 0;
     225  ppc_exc_initialize(
     226    PPC_INTERRUPT_DISABLE_MASK_DEFAULT,
     227    (uint32_t) bsp_interrupt_stack_start,
     228    (uint32_t) bsp_interrupt_stack_size
     229  );
     230
     231  /* Initalize interrupt support */
     232  if (bsp_interrupt_initialize() != RTEMS_SUCCESSFUL) {
     233    BSP_panic( "Cannot intitialize interrupt support\n");
     234  }
    290235
    291236  /*
  • c/src/lib/libbsp/powerpc/gen5200/startup/cpuinit.c

    r9ac9883 r82bd8d9d  
    118118  BAT dbat;
    119119
    120   calc_dbat_regvals(&dbat,RAM_START,RAM_SIZE,1,0,0,0,BPP_RW);
     120  calc_dbat_regvals(
     121    &dbat,
     122    (uint32_t) bsp_ram_start,
     123    (uint32_t) bsp_ram_size,
     124    true,
     125    false,
     126    false,
     127    false,
     128    BPP_RW
     129  );
    121130  SET_DBAT(0,dbat.batu,dbat.batl);
    122131
    123   calc_dbat_regvals(&dbat,ROM_START,ROM_SIZE,1,0,0,0,BPP_RX);
     132  calc_dbat_regvals(
     133    &dbat,
     134    (uint32_t) bsp_rom_start,
     135    (uint32_t) bsp_rom_size,
     136    true,
     137    false,
     138    false,
     139    false,
     140    BPP_RX
     141  );
    124142  SET_DBAT(1,dbat.batu,dbat.batl);
    125143
    126   calc_dbat_regvals(&dbat,MBAR,128*1024,1,1,1,1,BPP_RW);
     144  calc_dbat_regvals(
     145    &dbat,
     146    (uint32_t) MBAR,
     147    128 * 1024,
     148    false,
     149    true,
     150    false,
     151    true,
     152    BPP_RW
     153  );
    127154  SET_DBAT(2,dbat.batu,dbat.batl);
    128155
    129   calc_dbat_regvals(&dbat,DPRAM_START,128*1024,1,1,1,1,BPP_RW);
     156  calc_dbat_regvals(
     157    &dbat,
     158    (uint32_t) bsp_dpram_start,
     159    128 * 1024,
     160    false,
     161    true,
     162    false,
     163    true,
     164    BPP_RW
     165  );
    130166  SET_DBAT(3,dbat.batu,dbat.batl);
    131167}
     
    134170{
    135171  BAT dbat;
     172  uint32_t start = 0;
    136173 
    137174  /*
    138175   * Program BAT0 for RAM
    139176   */
    140   calc_dbat_regvals(&dbat,
    141                     uboot_bdinfo_ptr->bi_memstart,
    142                     uboot_bdinfo_ptr->bi_memsize,
    143                     1,0,0,0,BPP_RW);
     177  calc_dbat_regvals(
     178    &dbat,
     179    uboot_bdinfo_ptr->bi_memstart,
     180    uboot_bdinfo_ptr->bi_memsize,
     181    true,
     182    false,
     183    false,
     184    false,
     185    BPP_RW
     186  );
    144187  SET_DBAT(0,dbat.batu,dbat.batl);
    145188
     
    151194   * corrects that.
    152195   */
    153   if ( (uboot_bdinfo_ptr->bi_flashstart + uboot_bdinfo_ptr->bi_flashsize) <
    154         uboot_bdinfo_ptr->bi_flashstart ) {
    155     uint32_t start = 0 - uboot_bdinfo_ptr->bi_flashsize;
    156     calc_dbat_regvals(&dbat,
    157                       start, uboot_bdinfo_ptr->bi_flashsize, 1,0,0,0,BPP_RX);
     196  if ((uboot_bdinfo_ptr->bi_flashstart + uboot_bdinfo_ptr->bi_flashsize)
     197    < uboot_bdinfo_ptr->bi_flashstart) {
     198    start = 0 - uboot_bdinfo_ptr->bi_flashsize;
    158199  } else {
    159     calc_dbat_regvals(&dbat,
    160                       uboot_bdinfo_ptr->bi_flashstart,
    161                       uboot_bdinfo_ptr->bi_flashsize,
    162                       1,0,0,0,BPP_RX);
     200    start = uboot_bdinfo_ptr->bi_flashstart;
    163201  }
     202  calc_dbat_regvals(
     203    &dbat,
     204    start,
     205    uboot_bdinfo_ptr->bi_flashsize,
     206    true,
     207    false,
     208    false,
     209    false,
     210    BPP_RX
     211  );
    164212  SET_DBAT(1,dbat.batu,dbat.batl);
    165213
     
    167215   * Program BAT2 for the MBAR
    168216   */
    169   calc_dbat_regvals(&dbat,MBAR,128*1024,1,1,1,1,BPP_RW);
     217  calc_dbat_regvals(
     218    &dbat,
     219    (uint32_t) MBAR,
     220    128 * 1024,
     221    false,
     222    true,
     223    false,
     224    true,
     225    BPP_RW
     226  );
    170227  SET_DBAT(2,dbat.batu,dbat.batl);
    171228
     
    174231   */
    175232  if (uboot_bdinfo_ptr->bi_sramsize != 0) {
    176     calc_dbat_regvals(&dbat,
    177                       uboot_bdinfo_ptr->bi_sramstart,
    178                       uboot_bdinfo_ptr->bi_sramsize,
    179                       0,1,1,1,BPP_RW);
     233    calc_dbat_regvals(
     234      &dbat,
     235      uboot_bdinfo_ptr->bi_sramstart,
     236      uboot_bdinfo_ptr->bi_sramsize,
     237      false,
     238      true,
     239      true,
     240      true,
     241      BPP_RW
     242    );
    180243    SET_DBAT(3,dbat.batu,dbat.batl);
    181244  }
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