Changeset 82b3a44 in rtems-docs


Ignore:
Timestamp:
11/01/22 18:54:15 (3 months ago)
Author:
Kinsey Moore <kinsey.moore@…>
Branches:
master
Children:
aaba6e5
Parents:
0f7e3a6
git-author:
Kinsey Moore <kinsey.moore@…> (11/01/22 18:54:15)
git-committer:
Joel Sherrill <joel@…> (11/23/22 23:34:56)
Message:

user/zynqmp: Add information about CFC-400X

Add a list of known working hardware and commentary about bitstream
loading for specific hardware.

File:
1 edited

Legend:

Unmodified
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  • user/bsps/aarch64/xilinx-zynqmp.rst

    r0f7e3a6 r82b3a44  
    77.. _BSP_aarch64_qemu_xilinx_zynqmp_ilp32_zu3eg:
    88.. _BSP_aarch64_qemu_xilinx_zynqmp_lp64_zu3eg:
     9.. _BSP_aarch64_qemu_xilinx_zynqmp_lp64_cfc400x:
    910
    1011Qemu Xilinx ZynqMP
    1112==================
    1213
    13 This BSP supports four variants: `xilinx-zynqmp-ilp32-qemu`,
    14 `xilinx-zynqmp-lp64-qemu`, `xilinx-zynqmp-ilp32-zu3eg`, and
    15 `xilinx-zynqmp-lp64-zu3eg`. Platform-specific hardware initialization is
    16 performed by ARM Trusted Firmware (ATF). Other basic hardware initialization is
    17 performed by the BSP. These BSPs support the GICv2 interrupt controller present
    18 in all ZynqMP systems. The zu3eg BSPs have also been tested to be fully
    19 functional on zu2cg boards and should also work on any other ZynqMP chip variant
    20 since the Processing Subsystem (PS) does not vary among chip variants other than
    21 the number of CPU cores available.
     14This BSP family supports the following variants:
     15
     16* `xilinx-zynqmp-ilp32-qemu`
     17
     18* `xilinx-zynqmp-lp64-qemu`
     19
     20* `xilinx-zynqmp-ilp32-zu3eg`
     21
     22* `xilinx-zynqmp-lp64-zu3eg`
     23
     24* `xilinx-zynqmp-lp64-cfc400x`
     25
     26Platform-specific hardware initialization is performed by ARM Trusted Firmware
     27(ATF). Other basic hardware initialization is performed by the BSP. These BSPs
     28support the GICv2 interrupt controller present in all ZynqMP systems. The zu3eg
     29BSPs have also been tested to be fully functional on zu2cg boards and should
     30also work on any other ZynqMP chip variant since the Processing Subsystem (PS)
     31does not vary among chip variants other than the number of CPU cores available.
     32
     33This BSP family has been tested on the following hardware:
     34
     35* `Avnet UltraZed-EG SOM`
     36
     37* `Innoflight CFC-400X`
     38
     39* `Trenz TE0802`
     40
     41* `Xilinx ZCU102`
    2242
    2343Boot on QEMU
     
    3353recommended to use the u-boot BOOT.bin that comes with the PetaLinux prebuilts
    3454for the board in question.
     55
     56Some systems such as the CFC-400X may require a bitstream to be loaded into the
     57FPGA portion of the chip to operate as expected. This bitstream must be loaded
     58before RTEMS begins operation since accesses to programmable logic (PL) memory
     59space can cause the CPU to hang if the FPGA is not initialized. This can be
     60performed as part of BOOT.bin or by a bootloader such as u-boot. Loading
     61bitstreams from RTEMS has not been tested on the ZynqMP platform and requires
     62additional libraries from Xilinx.
    3563
    3664Hardware Boot Image Generation
     
    243271Cadence GEM instances present on all ZynqMP hardware variants. All interfaces
    244272are enabled by default, but only interfaces with operational MII busses will be
    245 recognized and usable in RTEMS. Most ZynqMP dev boards use CGEM3.
     273recognized and usable in RTEMS. Most ZynqMP dev boards use RGMII with CGEM3.
    246274
    247275When used with lwIP from the rtems-lwip integration repository, these BSP
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