Changeset 8264d23 in rtems for cpukit/score/cpu/mips/idtcpu.h

Timestamp:

03/08/02 16:24:48 (20 years ago)

Author:

Joel Sherrill <joel.sherrill@…>

Branches:

4.10, 4.11, 4.8, 4.9, 5, master

Children:

ffdc659

Parents:

9f9871f

Message:

2002-03-05 Greg Menke <gregory.menke@…>

• cpu_asm.S: Added support for the debug exception vector, cleaned up the exception processing & exception return stuff. Re-added EPC in the task context structure so the gdb stub will know where a thread is executing. Should've left it there in the first place...
• idtcpu.h: Added support for the debug exception vector.
• cpu.c: Added _exceptionTaskStack to hold a pointer to the stack frame in an interrupt so context switch code can get the userspace EPC when scheduling.
• rtems/score/cpu.h: Re-added EPC to the task context.

File:

• cpukit/score/cpu/mips/idtcpu.h (modified) (2 diffs)

cpukit/score/cpu/mips/idtcpu.h

@@ -59 +59 @@
 #if  __mips == 1
 #define UT_VEC  K0BASE                  /* utlbmiss vector */
-#define E_VEC   (K0BASE+0x80)           /* exception vevtor */
+#define DB_VEC  (K0BASE+0x40)           /* debug vector */
+#define E_VEC   (K0BASE+0x80)           /* exception vector */
 #elif  __mips == 3
 #define T_VEC   (K0BASE+0x000)          /* tlbmiss vector */
@@ -254 +255 @@
 
 #if  __mips == 1
+
+
+/* definitions for Debug and Cache Invalidate control (DCIC) register bits */
+#define DCIC_TR         0x80000000      /* Trap enable */
+#define DCIC_UD         0x40000000      /* User debug enable */
+#define DCIC_KD         0x20000000      /* Kernel debug enable */
+#define DCIC_TE         0x10000000      /* Trace enable */
+#define DCIC_DW         0x08000000      /* Enable data breakpoints on write */
+#define DCIC_DR         0x04000000      /* Enable data breakpoints on read */
+#define DCIC_DAE        0x02000000      /* Enable data addresss breakpoints */
+#define DCIC_PCE        0x01000000      /* Enable instruction breakpoints */
+#define DCIC_DE         0x00800000      /* Debug enable */
+#define DCIC_DL         0x00008000      /* Data cache line invalidate */
+#define DCIC_IL         0x00004000      /* Instruction cache line invalidate */
+#define DCIC_D          0x00002000      /* Data cache invalidate enable */
+#define DCIC_I          0x00001000      /* Instr. cache invalidate enable */
+#define DCIC_T          0x00000020      /* Trace, set by CPU */
+#define DCIC_W          0x00000010      /* Write reference, set by CPU */
+#define DCIC_R          0x00000008      /* Read reference, set by CPU */
+#define DCIC_DA         0x00000004      /* Data address, set by CPU */
+#define DCIC_PC         0x00000002      /* Program counter, set by CPU */
+#define DCIC_DB         0x00000001      /* Debug, set by CPU */
+
+
+
+
 #define SR_CUMASK       0xf0000000      /* coproc usable bits */
 #define SR_CU3          0x80000000      /* Coprocessor 3 usable */