Changeset 8264d23 in rtems


Ignore:
Timestamp:
Mar 8, 2002, 4:24:48 PM (18 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
ffdc659
Parents:
9f9871f
Message:

2002-03-05 Greg Menke <gregory.menke@…>

  • cpu_asm.S: Added support for the debug exception vector, cleaned up the exception processing & exception return stuff. Re-added EPC in the task context structure so the gdb stub will know where a thread is executing. Should've left it there in the first place...
  • idtcpu.h: Added support for the debug exception vector.
  • cpu.c: Added _exceptionTaskStack to hold a pointer to the stack frame in an interrupt so context switch code can get the userspace EPC when scheduling.
  • rtems/score/cpu.h: Re-added EPC to the task context.
Files:
13 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/mips/ChangeLog

    r9f9871f r8264d23  
     12002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
     2
     3        * cpu_asm.S: Added support for the debug exception vector, cleaned
     4        up the exception processing & exception return stuff.  Re-added
     5        EPC in the task context structure so the gdb stub will know where
     6        a thread is executing.  Should've left it there in the first place...
     7        * idtcpu.h: Added support for the debug exception vector.
     8        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
     9        stack frame in an interrupt so context switch code can get the
     10        userspace EPC when scheduling.
     11        * rtems/score/cpu.h: Re-added EPC to the task context.
     12
    1132002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
    214
  • c/src/exec/score/cpu/mips/cpu.c

    r9f9871f r8264d23  
    4646#include <rtems/score/isr.h>
    4747#include <rtems/score/wkspace.h>
     48
     49
     50
     51
     52/*
     53** local dword used in cpu_asm to pass the exception stack frame to the
     54** context switch code.
     55*/
     56unsigned __exceptionStackFrame = 0;
     57
     58
     59
    4860
    4961
  • c/src/exec/score/cpu/mips/cpu_asm.S

    r9f9871f r8264d23  
    125125#define RA_OFFSET 10
    126126#define C0_SR_OFFSET 11
    127 /* #define C0_EPC_OFFSET 12 */
     127#define C0_EPC_OFFSET 12
    128128
    129129/* NOTE: these constants must match the Context_Control_fp structure in cpu.h */
     
    161161#define FP31_OFFSET 31
    162162
    163 
     163       
     164ASM_EXTERN(__exceptionStackFrame, SZ_INT)
     165
     166       
     167               
    164168/*
    165169 *  _CPU_Context_save_fp_context
     
    387391        STREG s7,S7_OFFSET*R_SZ(a0)
    388392
     393       
     394        /*
     395        ** this code grabs the userspace EPC if we're dispatching from
     396        ** an interrupt frame or fakes an address as the EPC if we're
     397        ** not.  This is for the gdbstub's benefit so it can know
     398        **  where each thread is running.
     399        **
     400        ** Its value is only set when calling threadDispatch from
     401        ** the interrupt handler and is cleared immediately when this
     402        ** routine gets it.
     403        */
     404       
     405        la      t0,__exceptionStackFrame        /* see if we're coming in from an exception */
     406        LDREG   t1, (t0)
     407        NOP
     408        beqz    t1,1f
     409
     410        STREG   zero, (t0)                      /* and clear it */
     411        NOP
     412        LDREG   t0,R_EPC*R_SZ(t1)               /* get the userspace EPC from the frame */
     413        b       2f
     414               
     4151:      la    t0,_Thread_Dispatch               /* if ==0, we're switched out */
     416
     4172:      STREG   t0,C0_EPC_OFFSET*R_SZ(a0)
     418       
    389419
    390420_CPU_Context_switch_restore:
     
    503533.extern _ISR_Vector_table
    504534
     535
     536       
     537
     538
     539/*  void _DBG_Handler()
     540 *
     541 *  This routine services the (at least) MIPS1 debug vector,
     542 *  only used the the hardware debugging features.  This code,
     543 *  while optional, is best located here because its intrinsically
     544 *  associated with exceptions in general & thus tied pretty
     545 *  closely to _ISR_Handler.
     546 *
     547 */
     548
     549
     550FRAME(_DBG_Handler,sp,0,ra)
     551        .set noreorder
     552        la      k0,_ISR_Handler
     553        j       k0
     554        NOP
     555        .set reorder
     556ENDFRAME(_DBG_Handler)
     557
     558
     559
     560
     561       
    505562/*  void __ISR_Handler()
    506563 *
     
    562619        STREG t0, R_MDHI*R_SZ(sp)
    563620        STREG fp, R_FP*R_SZ(sp)
     621       
    564622        .set noat
    565623        STREG AT, R_AT*R_SZ(sp)
     
    580638        /* determine if an interrupt generated this exception */
    581639
    582         MFC0     k0,C0_CAUSE
    583         NOP
    584 
    585         and      k1,k0,CAUSE_EXCMASK
    586         beq      k1, 0, _ISR_Handler_1
     640        MFC0     t0,C0_CAUSE
     641        NOP
     642
     643        and      t1,t0,CAUSE_EXCMASK
     644        beq      t1, 0, _ISR_Handler_1
    587645
    588646_ISR_Handler_Exception:
    589647
    590648        /*
    591         sw      k0,0x8001FF00
     649        sw      t0,0x8001FF00
    592650        sw      t1,0x8001FF04
    593651        */
     
    601659         */
    602660
    603         /* already got k0 = cause in the interrupt test above */
    604         STREG    k0,R_CAUSE*R_SZ(sp)
    605 
    606         STREG    sp,SP_OFFSET*R_SZ(sp)     /* save sp */
    607 
    608         STREG    s0,S0_OFFSET*R_SZ(sp)     /* save s0 - s7 */
    609         STREG    s1,S1_OFFSET*R_SZ(sp)
    610         STREG    s2,S2_OFFSET*R_SZ(sp)
    611         STREG    s3,S3_OFFSET*R_SZ(sp)
    612         STREG    s4,S4_OFFSET*R_SZ(sp)
    613         STREG    s5,S5_OFFSET*R_SZ(sp)
    614         STREG    s6,S6_OFFSET*R_SZ(sp)
    615         STREG    s7,S7_OFFSET*R_SZ(sp)
     661        /* already got t0 = cause in the interrupt test above */
     662        STREG    t0,R_CAUSE*R_SZ(sp)
     663
     664        STREG    sp, R_SP*R_SZ(sp)
     665       
     666        STREG    s0,R_S0*R_SZ(sp)     /* save s0 - s7 */
     667        STREG    s1,R_S1*R_SZ(sp)
     668        STREG    s2,R_S2*R_SZ(sp)
     669        STREG    s3,R_S3*R_SZ(sp)
     670        STREG    s4,R_S4*R_SZ(sp)
     671        STREG    s5,R_S5*R_SZ(sp)
     672        STREG    s6,R_S6*R_SZ(sp)
     673        STREG    s7,R_S7*R_SZ(sp)
    616674
    617675        /* CP0 special registers */
     
    645703        NOP
    646704
    647         /* since we're returning, compute the address of the instruction we'll return to */
     705       
     706        /*
     707        ** note, if the exception vector returns, rely on it to have
     708        ** adjusted EPC so we will return to some correct address.  If
     709        ** this is not done, we might get stuck in an infinite loop because
     710        ** we'll return to the instruction where the exception occured and
     711        ** it could throw again.
     712        **
     713        ** It is expected the only code using the exception processing is
     714        ** either the gdb stub or some user code which is either going to
     715        ** panic or do something useful.
     716        */
     717
     718       
     719/* *********************************************************************
     720        * compute the address of the instruction we'll return to *
    648721
    649722        LDREG   t1, R_CAUSE*R_SZ(sp)
    650723        LDREG   t0, R_EPC*R_SZ(sp)
    651724
    652         /* first see if the exception happened in the delay slot */
     725        * first see if the exception happened in the delay slot *
    653726        li      t3,CAUSE_BD
    654727        AND     t4,t1,t3
     
    656729        NOP
    657730       
    658         /* it did, now see if the branch occured or not */
     731        * it did, now see if the branch occured or not *
    659732        li      t3,CAUSE_BT
    660733        AND     t4,t1,t3
     
    662735        NOP
    663736       
    664         /* branch was taken, we resume at the branch target */
     737        * branch was taken, we resume at the branch target *
    665738        LDREG   t0, R_TAR*R_SZ(sp)
    666739        j       excreturn
     
    676749        STREG   t0, R_EPC*R_SZ(sp)
    677750        NOP
    678        
    679        
     751********************************************************************* */
     752       
     753
     754 /* if we're returning into mips_break, move to the next instruction */
     755       
     756        LDREG   t0,R_EPC*R_SZ(sp)
     757        la      t1,mips_break
     758        xor     t2,t0,t1
     759        bnez    t2,3f
     760       
     761        addu    t0,R_SZ
     762        STREG   t0,R_EPC*R_SZ(sp)
     763        NOP
     7643:     
     765
     766       
     767       
     768               
    680769#if ( CPU_HARDWARE_FP == TRUE )
    681770        MFC0     t0,C0_SR               /* FPU is enabled, restore state */
     
    6957842:
    696785#endif
    697         LDREG    s0,S0_OFFSET*R_SZ(sp)    /* restore s0 - s7 */
    698         LDREG    s1,S1_OFFSET*R_SZ(sp)
    699         LDREG    s2,S2_OFFSET*R_SZ(sp)
    700         LDREG    s3,S3_OFFSET*R_SZ(sp)
    701         LDREG    s4,S4_OFFSET*R_SZ(sp)
    702         LDREG    s5,S5_OFFSET*R_SZ(sp)
    703         LDREG    s6,S6_OFFSET*R_SZ(sp)
    704         LDREG    s7,S7_OFFSET*R_SZ(sp)
     786        LDREG    s0,R_S0*R_SZ(sp)    /* restore s0 - s7 */
     787        LDREG    s1,R_S1*R_SZ(sp)
     788        LDREG    s2,R_S2*R_SZ(sp)
     789        LDREG    s3,R_S3*R_SZ(sp)
     790        LDREG    s4,R_S4*R_SZ(sp)
     791        LDREG    s5,R_S5*R_SZ(sp)
     792        LDREG    s6,R_S6*R_SZ(sp)
     793        LDREG    s7,R_S7*R_SZ(sp)
    705794
    706795        /* do NOT restore the sp as this could mess up the world */
     
    712801_ISR_Handler_1:
    713802
    714         MFC0     k1,C0_SR
    715         and      k0,CAUSE_IPMASK
    716         and      k0,k1
     803        MFC0     t1,C0_SR
     804        and      t0,CAUSE_IPMASK
     805        and      t0,t1
    717806
    718807        /* external interrupt not enabled, ignore */
     
    720809        /* Then where did it come from??? */
    721810       
    722         beq      k0,zero,_ISR_Handler_exit
     811        beq      t0,zero,_ISR_Handler_exit
    723812
    724813       
     
    795884
    796885
    797 
    798 
    799        
    800 
    801886       
    802887  /*
     
    839924        MTC0    t0, C0_SR
    840925        NOP
    841                        
     926
     927        /* save off our stack frame so the context switcher can get to it */
     928        la      t0,__exceptionStackFrame
     929        STREG   sp,(t0)
     930                                       
    842931        jal     _Thread_Dispatch
    843932        NOP
     933
     934        /* and make sure its clear in case we didn't dispatch.  if we did, its
     935        ** already cleared */
     936        la      t0,__exceptionStackFrame
     937        STREG   zero,(t0)
     938        NOP
    844939
    845940/*
    846941** turn interrupts back off while we restore context so
    847 ** a badly timed interrupt won't accidentally mess up k0
     942** a badly timed interrupt won't accidentally mess things up
    848943*/
    849944        MFC0    t0, C0_SR
     
    889984#endif
    890985
    891         LDREG k0, R_MDLO*R_SZ(sp)
     986        LDREG t8, R_MDLO*R_SZ(sp)
    892987        LDREG t0, R_T0*R_SZ(sp)
    893         mtlo  k0
    894         LDREG k0, R_MDHI*R_SZ(sp)           
     988        mtlo  t8
     989        LDREG t8, R_MDHI*R_SZ(sp)           
    895990        LDREG t1, R_T1*R_SZ(sp)
    896         mthi  k0
     991        mthi  t8
    897992        LDREG t2, R_T2*R_SZ(sp)
    898993        LDREG t3, R_T3*R_SZ(sp)
     
    9131008        LDREG v0, R_V0*R_SZ(sp)
    9141009       
    915         LDREG     k0, R_EPC*R_SZ(sp)
     1010        LDREG     k1, R_EPC*R_SZ(sp)
    9161011       
    9171012        .set noat
     
    9201015
    9211016        ADDIU     sp,sp,EXCP_STACK_SIZE
    922         j         k0
     1017        j         k1
    9231018        rfe
    9241019        NOP
     
    9281023
    9291024
    930        
    931                
     1025
     1026       
    9321027FRAME(mips_break,sp,0,ra)
    9331028        .set noreorder
    934         break   0x0
     1029        break   0x0     /* this statement must be first in this function, assumed so by mips-stub.c */
     1030        NOP
    9351031        j       ra
    9361032        NOP
  • c/src/exec/score/cpu/mips/idtcpu.h

    r9f9871f r8264d23  
    5959#if  __mips == 1
    6060#define UT_VEC  K0BASE                  /* utlbmiss vector */
    61 #define E_VEC   (K0BASE+0x80)           /* exception vevtor */
     61#define DB_VEC  (K0BASE+0x40)           /* debug vector */
     62#define E_VEC   (K0BASE+0x80)           /* exception vector */
    6263#elif  __mips == 3
    6364#define T_VEC   (K0BASE+0x000)          /* tlbmiss vector */
     
    254255
    255256#if  __mips == 1
     257
     258
     259/* definitions for Debug and Cache Invalidate control (DCIC) register bits */
     260#define DCIC_TR         0x80000000      /* Trap enable */
     261#define DCIC_UD         0x40000000      /* User debug enable */
     262#define DCIC_KD         0x20000000      /* Kernel debug enable */
     263#define DCIC_TE         0x10000000      /* Trace enable */
     264#define DCIC_DW         0x08000000      /* Enable data breakpoints on write */
     265#define DCIC_DR         0x04000000      /* Enable data breakpoints on read */
     266#define DCIC_DAE        0x02000000      /* Enable data addresss breakpoints */
     267#define DCIC_PCE        0x01000000      /* Enable instruction breakpoints */
     268#define DCIC_DE         0x00800000      /* Debug enable */
     269#define DCIC_DL         0x00008000      /* Data cache line invalidate */
     270#define DCIC_IL         0x00004000      /* Instruction cache line invalidate */
     271#define DCIC_D          0x00002000      /* Data cache invalidate enable */
     272#define DCIC_I          0x00001000      /* Instr. cache invalidate enable */
     273#define DCIC_T          0x00000020      /* Trace, set by CPU */
     274#define DCIC_W          0x00000010      /* Write reference, set by CPU */
     275#define DCIC_R          0x00000008      /* Read reference, set by CPU */
     276#define DCIC_DA         0x00000004      /* Data address, set by CPU */
     277#define DCIC_PC         0x00000002      /* Program counter, set by CPU */
     278#define DCIC_DB         0x00000001      /* Debug, set by CPU */
     279
     280
     281
     282
    256283#define SR_CUMASK       0xf0000000      /* coproc usable bits */
    257284#define SR_CU3          0x80000000      /* Coprocessor 3 usable */
  • c/src/exec/score/cpu/mips/rtems/score/cpu.h

    r9f9871f r8264d23  
    386386    __MIPS_REGISTER_TYPE ra;
    387387    __MIPS_REGISTER_TYPE c0_sr;
    388 /*    __MIPS_REGISTER_TYPE c0_epc; */
     388    __MIPS_REGISTER_TYPE c0_epc;
    389389} Context_Control;
    390390
  • c/src/exec/score/cpu/mips/rtems/score/mips.h

    r9f9871f r8264d23  
    141141
    142142
     143
     144
     145/*
     146 *  Access the Debug Cache Invalidate Control register
     147 */
     148
     149#define mips_get_dcic( _x ) \
     150  do { \
     151    asm volatile( "mfc0 %0, $7; nop" : "=r" (_x) : ); \
     152  } while (0)
     153
     154
     155#define mips_set_dcic( _x ) \
     156  do { \
     157    register unsigned int __x = (_x); \
     158    asm volatile( "mtc0 %0, $7; nop" : : "r" (__x) ); \
     159  } while (0)
     160
     161
     162
     163
     164/*
     165 *  Access the Breakpoint Program Counter & Mask registers
     166 *  (_x for BPC, _y for mask)
     167 */
     168
     169#define mips_get_bpcrm( _x, _y ) \
     170  do { \
     171    asm volatile( "mfc0 %0, $3; nop" : "=r" (_x) : ); \
     172    asm volatile( "mfc0 %0, $11; nop" : "=r" (_y) : ); \
     173  } while (0)
     174
     175
     176#define mips_set_bpcrm( _x, _y ) \
     177  do { \
     178    register unsigned int __x = (_x); \
     179    register unsigned int __y = (_y); \
     180    asm volatile( "mtc0 %0, $11; nop" : : "r" (__y) ); \
     181    asm volatile( "mtc0 %0, $3; nop" : : "r" (__x) ); \
     182  } while (0)
     183
     184
     185
     186
     187
     188
     189/*
     190 *  Access the Breakpoint Data Address & Mask registers
     191 *  (_x for BDA, _y for mask)
     192 */
     193
     194#define mips_get_bdarm( _x, _y ) \
     195  do { \
     196    asm volatile( "mfc0 %0, $5; nop" : "=r" (_x) : ); \
     197    asm volatile( "mfc0 %0, $9; nop" : "=r" (_y) : ); \
     198  } while (0)
     199
     200
     201#define mips_set_bdarm( _x, _y ) \
     202  do { \
     203    register unsigned int __x = (_x); \
     204    register unsigned int __y = (_y); \
     205    asm volatile( "mtc0 %0, $9; nop" : : "r" (__y) ); \
     206    asm volatile( "mtc0 %0, $5; nop" : : "r" (__x) ); \
     207  } while (0)
     208
     209
     210
     211
     212
     213
     214
    143215/*
    144216 *  Access FCR31
  • cpukit/score/cpu/mips/ChangeLog

    r9f9871f r8264d23  
     12002-03-05      Greg Menke <gregory.menke@gsfc.nasa.gov>
     2
     3        * cpu_asm.S: Added support for the debug exception vector, cleaned
     4        up the exception processing & exception return stuff.  Re-added
     5        EPC in the task context structure so the gdb stub will know where
     6        a thread is executing.  Should've left it there in the first place...
     7        * idtcpu.h: Added support for the debug exception vector.
     8        * cpu.c: Added ___exceptionTaskStack to hold a pointer to the
     9        stack frame in an interrupt so context switch code can get the
     10        userspace EPC when scheduling.
     11        * rtems/score/cpu.h: Re-added EPC to the task context.
     12
    1132002-02-27      Greg Menke <gregory.menke@gsfc.nasa.gov>
    214
  • cpukit/score/cpu/mips/cpu.c

    r9f9871f r8264d23  
    4646#include <rtems/score/isr.h>
    4747#include <rtems/score/wkspace.h>
     48
     49
     50
     51
     52/*
     53** local dword used in cpu_asm to pass the exception stack frame to the
     54** context switch code.
     55*/
     56unsigned __exceptionStackFrame = 0;
     57
     58
     59
    4860
    4961
  • cpukit/score/cpu/mips/cpu_asm.S

    r9f9871f r8264d23  
    125125#define RA_OFFSET 10
    126126#define C0_SR_OFFSET 11
    127 /* #define C0_EPC_OFFSET 12 */
     127#define C0_EPC_OFFSET 12
    128128
    129129/* NOTE: these constants must match the Context_Control_fp structure in cpu.h */
     
    161161#define FP31_OFFSET 31
    162162
    163 
     163       
     164ASM_EXTERN(__exceptionStackFrame, SZ_INT)
     165
     166       
     167               
    164168/*
    165169 *  _CPU_Context_save_fp_context
     
    387391        STREG s7,S7_OFFSET*R_SZ(a0)
    388392
     393       
     394        /*
     395        ** this code grabs the userspace EPC if we're dispatching from
     396        ** an interrupt frame or fakes an address as the EPC if we're
     397        ** not.  This is for the gdbstub's benefit so it can know
     398        **  where each thread is running.
     399        **
     400        ** Its value is only set when calling threadDispatch from
     401        ** the interrupt handler and is cleared immediately when this
     402        ** routine gets it.
     403        */
     404       
     405        la      t0,__exceptionStackFrame        /* see if we're coming in from an exception */
     406        LDREG   t1, (t0)
     407        NOP
     408        beqz    t1,1f
     409
     410        STREG   zero, (t0)                      /* and clear it */
     411        NOP
     412        LDREG   t0,R_EPC*R_SZ(t1)               /* get the userspace EPC from the frame */
     413        b       2f
     414               
     4151:      la    t0,_Thread_Dispatch               /* if ==0, we're switched out */
     416
     4172:      STREG   t0,C0_EPC_OFFSET*R_SZ(a0)
     418       
    389419
    390420_CPU_Context_switch_restore:
     
    503533.extern _ISR_Vector_table
    504534
     535
     536       
     537
     538
     539/*  void _DBG_Handler()
     540 *
     541 *  This routine services the (at least) MIPS1 debug vector,
     542 *  only used the the hardware debugging features.  This code,
     543 *  while optional, is best located here because its intrinsically
     544 *  associated with exceptions in general & thus tied pretty
     545 *  closely to _ISR_Handler.
     546 *
     547 */
     548
     549
     550FRAME(_DBG_Handler,sp,0,ra)
     551        .set noreorder
     552        la      k0,_ISR_Handler
     553        j       k0
     554        NOP
     555        .set reorder
     556ENDFRAME(_DBG_Handler)
     557
     558
     559
     560
     561       
    505562/*  void __ISR_Handler()
    506563 *
     
    562619        STREG t0, R_MDHI*R_SZ(sp)
    563620        STREG fp, R_FP*R_SZ(sp)
     621       
    564622        .set noat
    565623        STREG AT, R_AT*R_SZ(sp)
     
    580638        /* determine if an interrupt generated this exception */
    581639
    582         MFC0     k0,C0_CAUSE
    583         NOP
    584 
    585         and      k1,k0,CAUSE_EXCMASK
    586         beq      k1, 0, _ISR_Handler_1
     640        MFC0     t0,C0_CAUSE
     641        NOP
     642
     643        and      t1,t0,CAUSE_EXCMASK
     644        beq      t1, 0, _ISR_Handler_1
    587645
    588646_ISR_Handler_Exception:
    589647
    590648        /*
    591         sw      k0,0x8001FF00
     649        sw      t0,0x8001FF00
    592650        sw      t1,0x8001FF04
    593651        */
     
    601659         */
    602660
    603         /* already got k0 = cause in the interrupt test above */
    604         STREG    k0,R_CAUSE*R_SZ(sp)
    605 
    606         STREG    sp,SP_OFFSET*R_SZ(sp)     /* save sp */
    607 
    608         STREG    s0,S0_OFFSET*R_SZ(sp)     /* save s0 - s7 */
    609         STREG    s1,S1_OFFSET*R_SZ(sp)
    610         STREG    s2,S2_OFFSET*R_SZ(sp)
    611         STREG    s3,S3_OFFSET*R_SZ(sp)
    612         STREG    s4,S4_OFFSET*R_SZ(sp)
    613         STREG    s5,S5_OFFSET*R_SZ(sp)
    614         STREG    s6,S6_OFFSET*R_SZ(sp)
    615         STREG    s7,S7_OFFSET*R_SZ(sp)
     661        /* already got t0 = cause in the interrupt test above */
     662        STREG    t0,R_CAUSE*R_SZ(sp)
     663
     664        STREG    sp, R_SP*R_SZ(sp)
     665       
     666        STREG    s0,R_S0*R_SZ(sp)     /* save s0 - s7 */
     667        STREG    s1,R_S1*R_SZ(sp)
     668        STREG    s2,R_S2*R_SZ(sp)
     669        STREG    s3,R_S3*R_SZ(sp)
     670        STREG    s4,R_S4*R_SZ(sp)
     671        STREG    s5,R_S5*R_SZ(sp)
     672        STREG    s6,R_S6*R_SZ(sp)
     673        STREG    s7,R_S7*R_SZ(sp)
    616674
    617675        /* CP0 special registers */
     
    645703        NOP
    646704
    647         /* since we're returning, compute the address of the instruction we'll return to */
     705       
     706        /*
     707        ** note, if the exception vector returns, rely on it to have
     708        ** adjusted EPC so we will return to some correct address.  If
     709        ** this is not done, we might get stuck in an infinite loop because
     710        ** we'll return to the instruction where the exception occured and
     711        ** it could throw again.
     712        **
     713        ** It is expected the only code using the exception processing is
     714        ** either the gdb stub or some user code which is either going to
     715        ** panic or do something useful.
     716        */
     717
     718       
     719/* *********************************************************************
     720        * compute the address of the instruction we'll return to *
    648721
    649722        LDREG   t1, R_CAUSE*R_SZ(sp)
    650723        LDREG   t0, R_EPC*R_SZ(sp)
    651724
    652         /* first see if the exception happened in the delay slot */
     725        * first see if the exception happened in the delay slot *
    653726        li      t3,CAUSE_BD
    654727        AND     t4,t1,t3
     
    656729        NOP
    657730       
    658         /* it did, now see if the branch occured or not */
     731        * it did, now see if the branch occured or not *
    659732        li      t3,CAUSE_BT
    660733        AND     t4,t1,t3
     
    662735        NOP
    663736       
    664         /* branch was taken, we resume at the branch target */
     737        * branch was taken, we resume at the branch target *
    665738        LDREG   t0, R_TAR*R_SZ(sp)
    666739        j       excreturn
     
    676749        STREG   t0, R_EPC*R_SZ(sp)
    677750        NOP
    678        
    679        
     751********************************************************************* */
     752       
     753
     754 /* if we're returning into mips_break, move to the next instruction */
     755       
     756        LDREG   t0,R_EPC*R_SZ(sp)
     757        la      t1,mips_break
     758        xor     t2,t0,t1
     759        bnez    t2,3f
     760       
     761        addu    t0,R_SZ
     762        STREG   t0,R_EPC*R_SZ(sp)
     763        NOP
     7643:     
     765
     766       
     767       
     768               
    680769#if ( CPU_HARDWARE_FP == TRUE )
    681770        MFC0     t0,C0_SR               /* FPU is enabled, restore state */
     
    6957842:
    696785#endif
    697         LDREG    s0,S0_OFFSET*R_SZ(sp)    /* restore s0 - s7 */
    698         LDREG    s1,S1_OFFSET*R_SZ(sp)
    699         LDREG    s2,S2_OFFSET*R_SZ(sp)
    700         LDREG    s3,S3_OFFSET*R_SZ(sp)
    701         LDREG    s4,S4_OFFSET*R_SZ(sp)
    702         LDREG    s5,S5_OFFSET*R_SZ(sp)
    703         LDREG    s6,S6_OFFSET*R_SZ(sp)
    704         LDREG    s7,S7_OFFSET*R_SZ(sp)
     786        LDREG    s0,R_S0*R_SZ(sp)    /* restore s0 - s7 */
     787        LDREG    s1,R_S1*R_SZ(sp)
     788        LDREG    s2,R_S2*R_SZ(sp)
     789        LDREG    s3,R_S3*R_SZ(sp)
     790        LDREG    s4,R_S4*R_SZ(sp)
     791        LDREG    s5,R_S5*R_SZ(sp)
     792        LDREG    s6,R_S6*R_SZ(sp)
     793        LDREG    s7,R_S7*R_SZ(sp)
    705794
    706795        /* do NOT restore the sp as this could mess up the world */
     
    712801_ISR_Handler_1:
    713802
    714         MFC0     k1,C0_SR
    715         and      k0,CAUSE_IPMASK
    716         and      k0,k1
     803        MFC0     t1,C0_SR
     804        and      t0,CAUSE_IPMASK
     805        and      t0,t1
    717806
    718807        /* external interrupt not enabled, ignore */
     
    720809        /* Then where did it come from??? */
    721810       
    722         beq      k0,zero,_ISR_Handler_exit
     811        beq      t0,zero,_ISR_Handler_exit
    723812
    724813       
     
    795884
    796885
    797 
    798 
    799        
    800 
    801886       
    802887  /*
     
    839924        MTC0    t0, C0_SR
    840925        NOP
    841                        
     926
     927        /* save off our stack frame so the context switcher can get to it */
     928        la      t0,__exceptionStackFrame
     929        STREG   sp,(t0)
     930                                       
    842931        jal     _Thread_Dispatch
    843932        NOP
     933
     934        /* and make sure its clear in case we didn't dispatch.  if we did, its
     935        ** already cleared */
     936        la      t0,__exceptionStackFrame
     937        STREG   zero,(t0)
     938        NOP
    844939
    845940/*
    846941** turn interrupts back off while we restore context so
    847 ** a badly timed interrupt won't accidentally mess up k0
     942** a badly timed interrupt won't accidentally mess things up
    848943*/
    849944        MFC0    t0, C0_SR
     
    889984#endif
    890985
    891         LDREG k0, R_MDLO*R_SZ(sp)
     986        LDREG t8, R_MDLO*R_SZ(sp)
    892987        LDREG t0, R_T0*R_SZ(sp)
    893         mtlo  k0
    894         LDREG k0, R_MDHI*R_SZ(sp)           
     988        mtlo  t8
     989        LDREG t8, R_MDHI*R_SZ(sp)           
    895990        LDREG t1, R_T1*R_SZ(sp)
    896         mthi  k0
     991        mthi  t8
    897992        LDREG t2, R_T2*R_SZ(sp)
    898993        LDREG t3, R_T3*R_SZ(sp)
     
    9131008        LDREG v0, R_V0*R_SZ(sp)
    9141009       
    915         LDREG     k0, R_EPC*R_SZ(sp)
     1010        LDREG     k1, R_EPC*R_SZ(sp)
    9161011       
    9171012        .set noat
     
    9201015
    9211016        ADDIU     sp,sp,EXCP_STACK_SIZE
    922         j         k0
     1017        j         k1
    9231018        rfe
    9241019        NOP
     
    9281023
    9291024
    930        
    931                
     1025
     1026       
    9321027FRAME(mips_break,sp,0,ra)
    9331028        .set noreorder
    934         break   0x0
     1029        break   0x0     /* this statement must be first in this function, assumed so by mips-stub.c */
     1030        NOP
    9351031        j       ra
    9361032        NOP
  • cpukit/score/cpu/mips/idtcpu.h

    r9f9871f r8264d23  
    5959#if  __mips == 1
    6060#define UT_VEC  K0BASE                  /* utlbmiss vector */
    61 #define E_VEC   (K0BASE+0x80)           /* exception vevtor */
     61#define DB_VEC  (K0BASE+0x40)           /* debug vector */
     62#define E_VEC   (K0BASE+0x80)           /* exception vector */
    6263#elif  __mips == 3
    6364#define T_VEC   (K0BASE+0x000)          /* tlbmiss vector */
     
    254255
    255256#if  __mips == 1
     257
     258
     259/* definitions for Debug and Cache Invalidate control (DCIC) register bits */
     260#define DCIC_TR         0x80000000      /* Trap enable */
     261#define DCIC_UD         0x40000000      /* User debug enable */
     262#define DCIC_KD         0x20000000      /* Kernel debug enable */
     263#define DCIC_TE         0x10000000      /* Trace enable */
     264#define DCIC_DW         0x08000000      /* Enable data breakpoints on write */
     265#define DCIC_DR         0x04000000      /* Enable data breakpoints on read */
     266#define DCIC_DAE        0x02000000      /* Enable data addresss breakpoints */
     267#define DCIC_PCE        0x01000000      /* Enable instruction breakpoints */
     268#define DCIC_DE         0x00800000      /* Debug enable */
     269#define DCIC_DL         0x00008000      /* Data cache line invalidate */
     270#define DCIC_IL         0x00004000      /* Instruction cache line invalidate */
     271#define DCIC_D          0x00002000      /* Data cache invalidate enable */
     272#define DCIC_I          0x00001000      /* Instr. cache invalidate enable */
     273#define DCIC_T          0x00000020      /* Trace, set by CPU */
     274#define DCIC_W          0x00000010      /* Write reference, set by CPU */
     275#define DCIC_R          0x00000008      /* Read reference, set by CPU */
     276#define DCIC_DA         0x00000004      /* Data address, set by CPU */
     277#define DCIC_PC         0x00000002      /* Program counter, set by CPU */
     278#define DCIC_DB         0x00000001      /* Debug, set by CPU */
     279
     280
     281
     282
    256283#define SR_CUMASK       0xf0000000      /* coproc usable bits */
    257284#define SR_CU3          0x80000000      /* Coprocessor 3 usable */
  • cpukit/score/cpu/mips/rtems/mips/idtcpu.h

    r9f9871f r8264d23  
    5959#if  __mips == 1
    6060#define UT_VEC  K0BASE                  /* utlbmiss vector */
    61 #define E_VEC   (K0BASE+0x80)           /* exception vevtor */
     61#define DB_VEC  (K0BASE+0x40)           /* debug vector */
     62#define E_VEC   (K0BASE+0x80)           /* exception vector */
    6263#elif  __mips == 3
    6364#define T_VEC   (K0BASE+0x000)          /* tlbmiss vector */
     
    254255
    255256#if  __mips == 1
     257
     258
     259/* definitions for Debug and Cache Invalidate control (DCIC) register bits */
     260#define DCIC_TR         0x80000000      /* Trap enable */
     261#define DCIC_UD         0x40000000      /* User debug enable */
     262#define DCIC_KD         0x20000000      /* Kernel debug enable */
     263#define DCIC_TE         0x10000000      /* Trace enable */
     264#define DCIC_DW         0x08000000      /* Enable data breakpoints on write */
     265#define DCIC_DR         0x04000000      /* Enable data breakpoints on read */
     266#define DCIC_DAE        0x02000000      /* Enable data addresss breakpoints */
     267#define DCIC_PCE        0x01000000      /* Enable instruction breakpoints */
     268#define DCIC_DE         0x00800000      /* Debug enable */
     269#define DCIC_DL         0x00008000      /* Data cache line invalidate */
     270#define DCIC_IL         0x00004000      /* Instruction cache line invalidate */
     271#define DCIC_D          0x00002000      /* Data cache invalidate enable */
     272#define DCIC_I          0x00001000      /* Instr. cache invalidate enable */
     273#define DCIC_T          0x00000020      /* Trace, set by CPU */
     274#define DCIC_W          0x00000010      /* Write reference, set by CPU */
     275#define DCIC_R          0x00000008      /* Read reference, set by CPU */
     276#define DCIC_DA         0x00000004      /* Data address, set by CPU */
     277#define DCIC_PC         0x00000002      /* Program counter, set by CPU */
     278#define DCIC_DB         0x00000001      /* Debug, set by CPU */
     279
     280
     281
     282
    256283#define SR_CUMASK       0xf0000000      /* coproc usable bits */
    257284#define SR_CU3          0x80000000      /* Coprocessor 3 usable */
  • cpukit/score/cpu/mips/rtems/score/cpu.h

    r9f9871f r8264d23  
    386386    __MIPS_REGISTER_TYPE ra;
    387387    __MIPS_REGISTER_TYPE c0_sr;
    388 /*    __MIPS_REGISTER_TYPE c0_epc; */
     388    __MIPS_REGISTER_TYPE c0_epc;
    389389} Context_Control;
    390390
  • cpukit/score/cpu/mips/rtems/score/mips.h

    r9f9871f r8264d23  
    141141
    142142
     143
     144
     145/*
     146 *  Access the Debug Cache Invalidate Control register
     147 */
     148
     149#define mips_get_dcic( _x ) \
     150  do { \
     151    asm volatile( "mfc0 %0, $7; nop" : "=r" (_x) : ); \
     152  } while (0)
     153
     154
     155#define mips_set_dcic( _x ) \
     156  do { \
     157    register unsigned int __x = (_x); \
     158    asm volatile( "mtc0 %0, $7; nop" : : "r" (__x) ); \
     159  } while (0)
     160
     161
     162
     163
     164/*
     165 *  Access the Breakpoint Program Counter & Mask registers
     166 *  (_x for BPC, _y for mask)
     167 */
     168
     169#define mips_get_bpcrm( _x, _y ) \
     170  do { \
     171    asm volatile( "mfc0 %0, $3; nop" : "=r" (_x) : ); \
     172    asm volatile( "mfc0 %0, $11; nop" : "=r" (_y) : ); \
     173  } while (0)
     174
     175
     176#define mips_set_bpcrm( _x, _y ) \
     177  do { \
     178    register unsigned int __x = (_x); \
     179    register unsigned int __y = (_y); \
     180    asm volatile( "mtc0 %0, $11; nop" : : "r" (__y) ); \
     181    asm volatile( "mtc0 %0, $3; nop" : : "r" (__x) ); \
     182  } while (0)
     183
     184
     185
     186
     187
     188
     189/*
     190 *  Access the Breakpoint Data Address & Mask registers
     191 *  (_x for BDA, _y for mask)
     192 */
     193
     194#define mips_get_bdarm( _x, _y ) \
     195  do { \
     196    asm volatile( "mfc0 %0, $5; nop" : "=r" (_x) : ); \
     197    asm volatile( "mfc0 %0, $9; nop" : "=r" (_y) : ); \
     198  } while (0)
     199
     200
     201#define mips_set_bdarm( _x, _y ) \
     202  do { \
     203    register unsigned int __x = (_x); \
     204    register unsigned int __y = (_y); \
     205    asm volatile( "mtc0 %0, $9; nop" : : "r" (__y) ); \
     206    asm volatile( "mtc0 %0, $5; nop" : : "r" (__x) ); \
     207  } while (0)
     208
     209
     210
     211
     212
     213
     214
    143215/*
    144216 *  Access FCR31
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