Changeset 80f7732 in rtems


Ignore:
Timestamp:
Dec 2, 2009, 9:48:25 AM (9 years ago)
Author:
Ralf Corsepius <ralf.corsepius@…>
Branches:
4.10, 4.11, master
Children:
46e483b8
Parents:
882b1875
Message:

Whitespace removal.

Location:
cpukit
Files:
20 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/nios2/cpu.c

    r882b1875 r80f7732  
    4747 *  XXX document implementation including references if appropriate
    4848 */
    49  
     49
    5050uint32_t   _CPU_ISR_Get_level( void )
    5151{
     
    6565 *  XXX document implementation including references if appropriate
    6666 */
    67  
     67
    6868void _CPU_ISR_install_raw_handler(
    6969  uint32_t    vector,
     
    167167    /* Differentiate between IRQ off and on (for debugging) */
    168168    if(st & 1)
    169       for(;;); 
     169      for(;;);
    170170    else
    171       for(;;); 
    172  
     171      for(;;);
     172
    173173    /* insert your "halt" instruction here */ ;
    174174  }
  • cpukit/score/cpu/nios2/cpu_asm.S

    r882b1875 r80f7732  
    9090_exception_vector:
    9191
    92     /* 
     92    /*
    9393     * First, re-wind so we're pointed to the instruction where the exception
    9494     * occurred.
    9595     */
    9696
    97     addi ea, ea, -4 
     97    addi ea, ea, -4
    9898
    9999    /*
     
    118118    br _ISR_Handler
    119119
    120 /* ===================================================================== 
     120/* =====================================================================
    121121 * Exception handler:
    122122 *   Responsible for unimplemented instructions and other software
     
    183183
    184184    /*
    185      * Pass a pointer to the stack frame as the input argument of the 
     185     * Pass a pointer to the stack frame as the input argument of the
    186186     * exception handler (CPU_Exception_frame *).
    187187     */
     
    199199    br stuck_in_exception
    200200
    201     /* 
    202      * Restore the saved registers, so that all general purpose registers 
     201    /*
     202     * Restore the saved registers, so that all general purpose registers
    203203     * have been restored to their state at the time the interrupt occured.
    204204     */
     
    253253_ISR_Handler:
    254254
    255     /* 
    256      * Process an external hardware interrupt. 
     255    /*
     256     * Process an external hardware interrupt.
    257257     *
    258      * First, preserve all callee saved registers on 
     258     * First, preserve all callee saved registers on
    259259     * the stack. (See the Nios2 ABI documentation for details).
    260260     *
    261      * Do we really need to save all? 
     261     * Do we really need to save all?
    262262     *
    263263     * If this is interrupting a task (and not another interrupt),
     
    332332    call    __ISR_Handler
    333333
    334     /* 
     334    /*
    335335     * Now that the interrupt processing is complete, prepare to return to
    336336     * the interrupted code.
     
    338338
    339339    /*
    340      * Restore the saved registers, so that all general purpose registers 
     340     * Restore the saved registers, so that all general purpose registers
    341341     * have been restored to their state at the time the interrupt occured.
    342342     */
  • cpukit/score/cpu/nios2/rtems/score/cpu.h

    r882b1875 r80f7732  
    1414 *  + Anywhere there is an XXX, it should be replaced
    1515 *    with information about the CPU family being ported to.
    16  * 
     16 *
    1717 *  + At the end of each comment section, there is a heading which
    1818 *    says "Port Specific Information:".  When porting to RTEMS,
     
    169169/**
    170170 *  Does the RTEMS invoke the user's ISR with the vector number and
    171  *  a pointer to the saved interrupt frame (1) or just the vector 
     171 *  a pointer to the saved interrupt frame (1) or just the vector
    172172 *  number (0)?
    173173 *
     
    195195 */
    196196
    197 /** 
     197/**
    198198 *  @def CPU_SOFTWARE_FP
    199199 *
     
    203203 *
    204204 *  This feature conditional is used to indicate whether or not there
    205  *  is software implemented floating point that must be context 
     205 *  is software implemented floating point that must be context
    206206 *  switched.  The determination of whether or not this applies
    207207 *  is very tool specific and the state saved/restored is also
     
    520520/**
    521521 *  @ingroup CPUContext Management
    522  *  This defines the set of integer and processor state registers that are 
     522 *  This defines the set of integer and processor state registers that are
    523523 *  saved during a software exception.
    524524 */
     
    593593/**
    594594 *  @ingroup CPUInterrupt
    595  *  This variable points to the lowest physical address of the interrupt 
     595 *  This variable points to the lowest physical address of the interrupt
    596596 *  stack.
    597597 */
     
    600600/**
    601601 *  @ingroup CPUInterrupt
    602  *  This variable points to the lowest physical address of the interrupt 
     602 *  This variable points to the lowest physical address of the interrupt
    603603 *  stack.
    604604 */
     
    695695 *  @note  This does not have to be a power of 2 although it should be
    696696 *         a multiple of 2 greater than or equal to 2.  The requirement
    697  *         to be a multiple of 2 is because the heap uses the least 
     697 *         to be a multiple of 2 is because the heap uses the least
    698698 *         significant field of the front and back flags to indicate
    699699 *         that a block is in use or free.  So you do not want any odd
     
    991991 *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
    992992 *
    993  *  This set of routines are used to implement fast searches for 
     993 *  This set of routines are used to implement fast searches for
    994994 *  the most important ready task.
    995995 */
     
    10161016 *  @ingroup CPUBitfield
    10171017 *  This routine sets @a _output to the bit number of the first bit
    1018  *  set in @a _value.  @a _value is of CPU dependent type 
     1018 *  set in @a _value.  @a _value is of CPU dependent type
    10191019 *  @a Priority_Bit_map_control.  This type may be either 16 or 32 bits
    10201020 *  wide although only the 16 least significant bits will be used.
     
    10591059          _value >>=8
    10601060          _number = 8;
    1061  
     1061
    10621062        if _value > 0x0000f
    10631063          _value >=8
    10641064          _number += 4
    1065  
     1065
    10661066        _number += bit_set_table[ _value ]
    10671067@endverbatim
    1068  
     1068
    10691069 *    where bit_set_table[ 16 ] has values which indicate the first
    10701070 *      bit set
     
    11381138/**
    11391139 *  @ingroup CPUInterrupt
    1140  *  This routine installs a "raw" interrupt handler directly into the 
     1140 *  This routine installs a "raw" interrupt handler directly into the
    11411141 *  processor's vector table.
    11421142 *
     
    13001300{
    13011301  uint32_t   byte1, byte2, byte3, byte4, swapped;
    1302  
     1302
    13031303  byte4 = (value >> 24) & 0xff;
    13041304  byte3 = (value >> 16) & 0xff;
    13051305  byte2 = (value >> 8)  & 0xff;
    13061306  byte1 =  value        & 0xff;
    1307  
     1307
    13081308  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
    13091309  return( swapped );
  • cpukit/score/cpu/nios2/rtems/score/nios2.h

    r882b1875 r80f7732  
    11/*  nios2.h
    22 *
    3  *  This file sets up basic CPU dependency settings based on 
     3 *  This file sets up basic CPU dependency settings based on
    44 *  compiler settings.  For example, it can determine if
    55 *  floating point is available.  This particular implementation
     
    3636 *  to.
    3737 */
    38  
     38
    3939/*
    4040 *  Define the name of the CPU family and specific model.
     
    4646/*
    4747 *  See also nios2-rtems-gcc -print-multi-lib for all valid combinations of
    48  * 
     48 *
    4949 *    -mno-hw-mul
    5050 *    -mhw-mulx
  • cpukit/score/cpu/nios2/rtems/score/types.h

    r882b1875 r80f7732  
    44
    55/*
    6  *  This include file contains type definitions pertaining to the 
     6 *  This include file contains type definitions pertaining to the
    77 *  Altera Nios II processor family.
    88 *
  • cpukit/score/cpu/no_cpu/cpu.c

    r882b1875 r80f7732  
    4848 *  XXX document implementation including references if appropriate
    4949 */
    50  
     50
    5151uint32_t   _CPU_ISR_Get_level( void )
    5252{
     
    6666 *  XXX document implementation including references if appropriate
    6767 */
    68  
     68
    6969void _CPU_ISR_install_raw_handler(
    7070  uint32_t    vector,
  • cpukit/score/cpu/no_cpu/cpu_asm.c

    r882b1875 r80f7732  
    174174   *  LABEL "exit interrupt (simple case):
    175175   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
    176    *    if outermost interrupt 
     176   *    if outermost interrupt
    177177   *      restore stack
    178178   *  #endif
  • cpukit/score/cpu/no_cpu/rtems/score/cpu.h

    r882b1875 r80f7732  
    1414 *  + Anywhere there is an XXX, it should be replaced
    1515 *    with information about the CPU family being ported to.
    16  * 
     16 *
    1717 *  + At the end of each comment section, there is a heading which
    1818 *    says "Port Specific Information:".  When porting to RTEMS,
     
    169169/**
    170170 *  Does the RTEMS invoke the user's ISR with the vector number and
    171  *  a pointer to the saved interrupt frame (1) or just the vector 
     171 *  a pointer to the saved interrupt frame (1) or just the vector
    172172 *  number (0)?
    173173 *
     
    196196 */
    197197
    198 /** 
     198/**
    199199 *  @def CPU_SOFTWARE_FP
    200200 *
     
    204204 *
    205205 *  This feature conditional is used to indicate whether or not there
    206  *  is software implemented floating point that must be context 
     206 *  is software implemented floating point that must be context
    207207 *  switched.  The determination of whether or not this applies
    208208 *  is very tool specific and the state saved/restored is also
     
    467467 */
    468468typedef struct {
    469     /** This field is a hint that a port will have a number of integer 
     469    /** This field is a hint that a port will have a number of integer
    470470     *  registers that need to be saved at a context switch.
    471471     */
    472472    uint32_t   some_integer_register;
    473     /** This field is a hint that a port will have a number of system 
     473    /** This field is a hint that a port will have a number of system
    474474     *  registers that need to be saved at a context switch.
    475475     */
     
    488488 *
    489489 *  @param[in] _context is the thread context area to access
    490  * 
     490 *
    491491 *  @return This method returns the stack pointer.
    492492 */
     
    511511 */
    512512typedef struct {
    513     /** This field is a hint that a port will have a number of integer 
     513    /** This field is a hint that a port will have a number of integer
    514514     *  registers that need to be saved when an interrupt occurs or
    515515     *  when a context switch occurs at the end of an ISR.
     
    551551/**
    552552 *  @ingroup CPUInterrupt
    553  *  This variable points to the lowest physical address of the interrupt 
     553 *  This variable points to the lowest physical address of the interrupt
    554554 *  stack.
    555555 */
     
    558558/**
    559559 *  @ingroup CPUInterrupt
    560  *  This variable points to the lowest physical address of the interrupt 
     560 *  This variable points to the lowest physical address of the interrupt
    561561 *  stack.
    562562 */
     
    652652 *  @note  This does not have to be a power of 2 although it should be
    653653 *         a multiple of 2 greater than or equal to 2.  The requirement
    654  *         to be a multiple of 2 is because the heap uses the least 
     654 *         to be a multiple of 2 is because the heap uses the least
    655655 *         significant field of the front and back flags to indicate
    656656 *         that a block is in use or free.  So you do not want any odd
     
    927927 *  @defgroup CPUBitfield Processor Dependent Bitfield Manipulation
    928928 *
    929  *  This set of routines are used to implement fast searches for 
     929 *  This set of routines are used to implement fast searches for
    930930 *  the most important ready task.
    931931 */
     
    952952 *  @ingroup CPUBitfield
    953953 *  This routine sets @a _output to the bit number of the first bit
    954  *  set in @a _value.  @a _value is of CPU dependent type 
     954 *  set in @a _value.  @a _value is of CPU dependent type
    955955 *  @a Priority_Bit_map_control.  This type may be either 16 or 32 bits
    956956 *  wide although only the 16 least significant bits will be used.
     
    995995          _value >>=8
    996996          _number = 8;
    997  
     997
    998998        if _value > 0x0000f
    999999          _value >=8
    10001000          _number += 4
    1001  
     1001
    10021002        _number += bit_set_table[ _value ]
    10031003@endverbatim
    1004  
     1004
    10051005 *    where bit_set_table[ 16 ] has values which indicate the first
    10061006 *      bit set
     
    10741074/**
    10751075 *  @ingroup CPUInterrupt
    1076  *  This routine installs a "raw" interrupt handler directly into the 
     1076 *  This routine installs a "raw" interrupt handler directly into the
    10771077 *  processor's vector table.
    10781078 *
     
    12361236{
    12371237  uint32_t byte1, byte2, byte3, byte4, swapped;
    1238  
     1238
    12391239  byte4 = (value >> 24) & 0xff;
    12401240  byte3 = (value >> 16) & 0xff;
    12411241  byte2 = (value >> 8)  & 0xff;
    12421242  byte1 =  value        & 0xff;
    1243  
     1243
    12441244  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
    12451245  return swapped;
  • cpukit/score/cpu/no_cpu/rtems/score/no_cpu.h

    r882b1875 r80f7732  
    11/*  no_cpu.h
    22 *
    3  *  This file sets up basic CPU dependency settings based on 
     3 *  This file sets up basic CPU dependency settings based on
    44 *  compiler settings.  For example, it can determine if
    55 *  floating point is available.  This particular implementation
     
    3636 *  to.
    3737 */
    38  
     38
    3939#if defined(rtems_multilib)
    4040/*
    41  *  Figure out all CPU Model Feature Flags based upon compiler 
    42  *  predefines. 
     41 *  Figure out all CPU Model Feature Flags based upon compiler
     42 *  predefines.
    4343 */
    4444
     
    4747
    4848#elif defined(no_cpu)
    49  
     49
    5050#define CPU_MODEL_NAME  "no_cpu_model"
    5151#define NOCPU_HAS_FPU     1
    52  
     52
    5353#else
    54  
     54
    5555#error "Unsupported CPU Model"
    56  
     56
    5757#endif
    5858
  • cpukit/score/cpu/sparc/cpu.c

    r882b1875 r80f7732  
    1717
    1818/*
    19  *  This initializes the set of opcodes placed in each trap 
     19 *  This initializes the set of opcodes placed in each trap
    2020 *  table entry.  The routine which installs a handler is responsible
    2121 *  for filling in the fields for the _handler address and the _vector
     
    4242 *
    4343 *  Output Parameters: NONE
    44  * 
     44 *
    4545 *  NOTE: There is no need to save the pointer to the thread dispatch routine.
    4646 *        The SPARC's assembly code can reference it directly with no problems.
     
    7979 *    returns the current interrupt level (PIL field of the PSR)
    8080 */
    81  
     81
    8282uint32_t   _CPU_ISR_Get_level( void )
    8383{
    8484  uint32_t   level;
    85  
     85
    8686  sparc_get_interrupt_level( level );
    87  
     87
    8888  return level;
    8989}
     
    9797 *
    9898 *  Input Parameters:
    99  *    vector      - trap table entry number plus synchronous 
     99 *    vector      - trap table entry number plus synchronous
    100100 *                    vs. asynchronous information
    101101 *    new_handler - address of the handler to be installed
     
    104104 *  Output Parameters: NONE
    105105 *    *new_handler - address of the handler previously installed
    106  * 
    107  *  NOTE: 
     106 *
     107 *  NOTE:
    108108 *
    109109 *  On the SPARC, there are really only 256 vectors.  However, the executive
     
    126126 *  address.
    127127 */
    128  
     128
    129129void _CPU_ISR_install_raw_handler(
    130130  uint32_t    vector,
     
    171171
    172172  if ( slot->mov_psr_l0 == _CPU_Trap_slot_template.mov_psr_l0 ) {
    173     u32_handler = 
     173    u32_handler =
    174174      (slot->sethi_of_handler_to_l4 << HIGH_BITS_SHIFT) |
    175175      (slot->jmp_to_low_of_handler_plus_l4 & LOW_BITS_MASK);
     
    187187
    188188  slot->mov_vector_l3 |= vector;
    189   slot->sethi_of_handler_to_l4 |= 
     189  slot->sethi_of_handler_to_l4 |=
    190190    (u32_handler & HIGH_BITS_MASK) >> HIGH_BITS_SHIFT;
    191191  slot->jmp_to_low_of_handler_plus_l4 |= (u32_handler & LOW_BITS_MASK);
     
    209209 *    old_handler  - pointer to former ISR for this vector number
    210210 *
    211  *  Output parameters: 
     211 *  Output parameters:
    212212 *    *old_handler - former ISR for this vector number
    213213 *
     
    280280    uint32_t     the_size;
    281281    uint32_t     tmp_psr;
    282  
     282
    283283    /*
    284284     *  On CPUs with stacks which grow down (i.e. SPARC), we build the stack
    285      *  based on the stack_high address. 
     285     *  based on the stack_high address.
    286286     */
    287  
     287
    288288    stack_high = ((uint32_t)(stack_base) + size);
    289289    stack_high &= ~(CPU_STACK_ALIGNMENT - 1);
    290  
     290
    291291    the_size = size & ~(CPU_STACK_ALIGNMENT - 1);
    292  
     292
    293293    /*
    294294     *  See the README in this directory for a diagram of the stack.
    295295     */
    296  
     296
    297297    the_context->o7    = ((uint32_t) entry_point) - 8;
    298298    the_context->o6_sp = stack_high - CPU_MINIMUM_STACK_FRAME_SIZE;
     
    312312    tmp_psr |= (new_level << 8) & SPARC_PSR_PIL_MASK;
    313313    tmp_psr &= ~SPARC_PSR_EF_MASK;      /* disabled by default */
    314    
     314
    315315#if (SPARC_HAS_FPU == 1)
    316316    /*
  • cpukit/score/cpu/sparc/cpu_asm.S

    r882b1875 r80f7732  
    33 *  This file contains the basic algorithms for all assembly code used
    44 *  in an specific CPU port of RTEMS.  These algorithms must be implemented
    5  *  in assembly language. 
     5 *  in assembly language.
    66 *
    77 *  COPYRIGHT (c) 1989-2007.
     
    1313 *
    1414 *  Ported to ERC32 implementation of the SPARC by On-Line Applications
    15  *  Research Corporation (OAR) under contract to the European Space 
     15 *  Research Corporation (OAR) under contract to the European Space
    1616 *  Agency (ESA).
    1717 *
    18  *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995. 
     18 *  ERC32 modifications of respective RTEMS file: COPYRIGHT (c) 1995.
    1919 *  European Space Agency.
    2020 *
     
    3535 *  from is changed then the pointer is modified by this routine.
    3636 *
    37  *  NOTE: See the README in this directory for information on the 
     37 *  NOTE: See the README in this directory for information on the
    3838 *        management of the "EF" bit in the PSR.
    3939 */
     
    4747         *  The following enables the floating point unit.
    4848         */
    49    
     49
    5050        mov     %psr, %l0
    5151        sethi   %hi(SPARC_PSR_EF_MASK), %l1
     
    5353        or      %l0, %l1, %l0
    5454        mov     %l0, %psr                  ! **** ENABLE FLOAT ACCESS ****
    55         nop; nop; nop;                     ! Need three nops before EF is 
     55        nop; nop; nop;                     ! Need three nops before EF is
    5656        ld      [%i0], %l0                 ! active due to pipeline delay!!!
    5757        std     %f0, [%l0 + FO_F1_OFFSET]
     
    8484 *  from is changed then the pointer is modified by this routine.
    8585 *
    86  *  NOTE: See the README in this directory for information on the 
     86 *  NOTE: See the README in this directory for information on the
    8787 *        management of the "EF" bit in the PSR.
    8888 */
     
    9696         *  The following enables the floating point unit.
    9797         */
    98    
     98
    9999        mov     %psr, %l0
    100100        sethi   %hi(SPARC_PSR_EF_MASK), %l1
     
    102102        or      %l0, %l1, %l0
    103103        mov     %l0, %psr                  ! **** ENABLE FLOAT ACCESS ****
    104         nop; nop; nop;                     ! Need three nops before EF is 
     104        nop; nop; nop;                     ! Need three nops before EF is
    105105        ld      [%i0], %l0                 ! active due to pipeline delay!!!
    106106        ldd     [%l0 + FO_F1_OFFSET], %f0
     
    182182         *  In examining the set register windows, one may logically divide
    183183         *  the windows into sets (some of which may be empty) based on their
    184          *  current status: 
    185          *
    186          *    + current (i.e. in use), 
     184         *  current status:
     185         *
     186         *    + current (i.e. in use),
    187187         *    + used (i.e. a restore would not trap)
    188188         *    + invalid (i.e. 1 in corresponding bit in WIM)
     
    203203         *  In this case, we only would save the used windows -- 6 and 7.
    204204         *
    205          *   Traps are disabled for the same logical period as in a 
     205         *   Traps are disabled for the same logical period as in a
    206206         *     flush all windows trap handler.
    207          *   
     207         *
    208208         *    Register Usage while saving the windows:
    209209         *      g1 = current PSR
     
    239239        nop
    240240
    241         restore                               ! back one window 
     241        restore                               ! back one window
    242242
    243243        /*
    244244         *  Now save the window just as if we overflowed to it.
    245245         */
    246  
     246
    247247        std     %l0, [%sp + CPU_STACK_FRAME_L0_OFFSET]
    248248        std     %l2, [%sp + CPU_STACK_FRAME_L2_OFFSET]
    249249        std     %l4, [%sp + CPU_STACK_FRAME_L4_OFFSET]
    250250        std     %l6, [%sp + CPU_STACK_FRAME_L6_OFFSET]
    251  
     251
    252252        std     %i0, [%sp + CPU_STACK_FRAME_I0_OFFSET]
    253253        std     %i2, [%sp + CPU_STACK_FRAME_I2_OFFSET]
     
    263263        and     %g3, SPARC_NUMBER_OF_REGISTER_WINDOWS - 1, %g3
    264264        mov     1, %g4
    265         sll     %g4, %g3, %g4                 ! g4 = new WIM 
     265        sll     %g4, %g3, %g4                 ! g4 = new WIM
    266266        mov     %g4, %wim
    267267
     
    560560        wr       %l0, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS ****
    561561        ba,a     simple_return
    562          
     562       
    563563enable_irq:
    564         or       %g5, SPARC_PSR_PIL_MASK, %g4 
     564        or       %g5, SPARC_PSR_PIL_MASK, %g4
    565565        wr       %g4, SPARC_PSR_ET_MASK, %psr ! **** ENABLE TRAPS ****
    566566        nop; nop; nop
     
    659659        ! NOTE: Use the delay slot
    660660        sethi    %hi(SYM(_Context_Switch_necessary)), %l4
    661        
     661
    662662
    663663        /*
     
    686686                                 !   to the currently executing task flag
    687687        st       %g0, [%l6 + %lo(SYM(_ISR_Signals_to_thread_executing))]
    688                                  
     688
    689689
    690690        /*
     
    708708        sub      %fp, CPU_MINIMUM_STACK_FRAME_SIZE, %sp
    709709
    710         or      %l0, SPARC_PSR_ET_MASK, %l7    ! l7 = PSR with ET=1 
     710        or      %l0, SPARC_PSR_ET_MASK, %l7    ! l7 = PSR with ET=1
    711711        mov     %l7, %psr                      !  **** ENABLE TRAPS ****
    712712        nop
     
    720720         *  We invoked _Thread_Dispatch in a state similar to the interrupted
    721721         *  task.  In order to safely be able to tinker with the register
    722          *  windows and get the task back to its pre-interrupt state, 
     722         *  windows and get the task back to its pre-interrupt state,
    723723         *  we need to disable interrupts disabled so we can safely tinker
    724724         *  with the register windowing.  In particular, the CWP in the PSR
     
    789789        andn    %l0, SPARC_PSR_CWP_MASK, %l0   ! want rest from task
    790790        or      %l3, %l0, %l0                  ! install it later...
    791         andn    %l0, SPARC_PSR_ET_MASK, %l0 
     791        andn    %l0, SPARC_PSR_ET_MASK, %l0
    792792
    793793        /*
  • cpukit/score/cpu/sparc/rtems/asm.h

    r882b1875 r80f7732  
    100100 *  Entry for traps which jump to a programmer-specified trap handler.
    101101 */
    102  
     102
    103103#define TRAP(_vector, _handler)  \
    104104  mov   %psr, %l0 ; \
     
    110110 *  Used for the reset trap to avoid a supervisor instruction
    111111 */
    112  
     112
    113113#define RTRAP(_vector, _handler)  \
    114114  mov   %g0, %l0 ; \
  • cpukit/score/cpu/sparc/rtems/score/cpu.h

    r882b1875 r80f7732  
    44
    55/*
    6  *  This include file contains information pertaining to the port of 
     6 *  This include file contains information pertaining to the port of
    77 *  the executive to the SPARC processor.
    88 *
     
    104104/*
    105105 *  Does the RTEMS invoke the user's ISR with the vector number and
    106  *  a pointer to the saved interrupt frame (1) or just the vector 
     106 *  a pointer to the saved interrupt frame (1) or just the vector
    107107 *  number (0)?
    108108 */
     
    192192 *  much of the critical data area as possible in a cache line.
    193193 *
    194  *  The SPARC does not appear to have particularly strict alignment 
     194 *  The SPARC does not appear to have particularly strict alignment
    195195 *  requirements.  This value was chosen to take advantages of caches.
    196196 */
     
    217217
    218218/*
    219  *  This structure represents the organization of the minimum stack frame 
     219 *  This structure represents the organization of the minimum stack frame
    220220 *  for the SPARC.  More framing information is required in certain situaions
    221221 *  such as when there are a large number of out parameters or when the callee
     
    307307typedef struct {
    308308    /*
    309      *  Using a double g0_g1 will put everything in this structure on a 
     309     *  Using a double g0_g1 will put everything in this structure on a
    310310     *  double word boundary which allows us to use double word loads
    311311     *  and stores safely in the context switch.
     
    513513#define ISF_TPC_OFFSET         CPU_MINIMUM_STACK_FRAME_SIZE + 0x4c
    514514
    515 #define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0x50 
     515#define CONTEXT_CONTROL_INTERRUPT_FRAME_SIZE CPU_MINIMUM_STACK_FRAME_SIZE + 0x50
    516516#ifndef ASM
    517517/*
    518518 *  This variable is contains the initialize context for the FP unit.
    519  *  It is filled in by _CPU_Initialize and copied into the task's FP 
     519 *  It is filled in by _CPU_Initialize and copied into the task's FP
    520520 *  context area during _CPU_Context_Initialize.
    521521 */
     
    556556 *        trap type (a.k.a. vector) and another with the psr.
    557557 */
    558  
     558
    559559typedef struct {
    560560  uint32_t     mov_psr_l0;                     /* mov   %psr, %l0           */
     
    563563  uint32_t     mov_vector_l3;                  /* mov   _vector, %l3        */
    564564} CPU_Trap_table_entry;
    565  
     565
    566566/*
    567567 *  This is the set of opcodes for the instructions loaded into a trap
     
    573573 *  must be filled in when the handler is installed.
    574574 */
    575  
     575
    576576extern const CPU_Trap_table_entry _CPU_Trap_slot_template;
    577577
    578578/*
    579  *  The size of the floating point context area. 
     579 *  The size of the floating point context area.
    580580 */
    581581
     
    715715#define _CPU_ISR_Disable( _level ) \
    716716  (_level) = sparc_disable_interrupts()
    717  
     717
    718718/*
    719719 *  Enable interrupts to the previous level (returned by _CPU_ISR_Disable).
     
    734734#define _CPU_ISR_Flash( _level ) \
    735735  sparc_flash_interrupts( _level )
    736  
     736
    737737/*
    738738 *  Map interrupt level in task mode onto the hardware that the CPU
    739739 *  actually provides.  Currently, interrupt levels which do not
    740  *  map onto the CPU in a straight fashion are undefined. 
     740 *  map onto the CPU in a straight fashion are undefined.
    741741 */
    742742
    743743#define _CPU_ISR_Set_level( _newlevel ) \
    744744   sparc_enable_interrupts( _newlevel << 8)
    745  
     745
    746746uint32_t   _CPU_ISR_Get_level( void );
    747  
     747
    748748/* end of ISR handler macros */
    749749
     
    781781 *  Make GDB stop unwinding at _Thread_Handler, previous register window
    782782 *  Frame pointer is 0 and calling address must be a function with starting
    783  *  with a SAVE instruction. If return address is leaf-function (no SAVE) 
     783 *  with a SAVE instruction. If return address is leaf-function (no SAVE)
    784784 *  GDB will not look at prev reg window fp.
    785785 *
     
    794794/*
    795795 *  This routine is responsible for somehow restarting the currently
    796  *  executing task. 
     796 *  executing task.
    797797 *
    798798 *  On the SPARC, this is is relatively painless but requires a small
     
    816816 *
    817817 *  The SPARC allows us to use the simple initialization model
    818  *  in which an "initial" FP context was saved into _CPU_Null_fp_context 
     818 *  in which an "initial" FP context was saved into _CPU_Null_fp_context
    819819 *  at CPU initialization and it is simply copied into the destination
    820820 *  context.
     
    892892 *  table.
    893893 */
    894  
     894
    895895void _CPU_ISR_install_raw_handler(
    896896  uint32_t    vector,
     
    912912
    913913#if (CPU_PROVIDES_IDLE_THREAD_BODY == TRUE)
    914  
     914
    915915/*
    916916 *  _CPU_Thread_Idle_body
     
    919919 *  tries to take advantage of those models.
    920920 */
    921  
     921
    922922void *_CPU_Thread_Idle_body( uintptr_t ignored );
    923923
     
    973973 *
    974974 *  This version will work on any processor, but if you come across a better
    975  *  way for the SPARC PLEASE use it.  The most common way to swap a 32-bit 
     975 *  way for the SPARC PLEASE use it.  The most common way to swap a 32-bit
    976976 *  entity as shown below is not any more efficient on the SPARC.
    977977 *
     
    984984 *  following code at optimization level four (i.e. -O4).
    985985 */
    986  
     986
    987987static inline uint32_t CPU_swap_u32(
    988988  uint32_t value
     
    990990{
    991991  uint32_t   byte1, byte2, byte3, byte4, swapped;
    992  
     992
    993993  byte4 = (value >> 24) & 0xff;
    994994  byte3 = (value >> 16) & 0xff;
    995995  byte2 = (value >> 8)  & 0xff;
    996996  byte1 =  value        & 0xff;
    997  
     997
    998998  swapped = (byte1 << 24) | (byte2 << 16) | (byte3 << 8) | byte4;
    999999  return( swapped );
  • cpukit/score/cpu/sparc/rtems/score/sparc.h

    r882b1875 r80f7732  
    44
    55/*
    6  *  This include file contains information pertaining to the SPARC 
     6 *  This include file contains information pertaining to the SPARC
    77 *  processor family.
    88 *
     
    3333 *  Currently recognized feature flags:
    3434 *
    35  *    + SPARC_HAS_FPU 
     35 *    + SPARC_HAS_FPU
    3636 *        0 - no HW FPU
    3737 *        1 - has HW FPU (assumed to be compatible w/90C602)
    3838 *
    39  *    + SPARC_HAS_BITSCAN 
     39 *    + SPARC_HAS_BITSCAN
    4040 *        0 - does not have scan instructions
    4141 *        1 - has scan instruction  (not currently implemented)
    42  * 
     42 *
    4343 *    + SPARC_NUMBER_OF_REGISTER_WINDOWS
    4444 *        8 is the most common number supported by SPARC implementations.
    4545 *        SPARC_PSR_CWP_MASK is derived from this value.
    4646 */
    47  
     47
    4848/*
    4949 *  Some higher end SPARCs have a bitscan instructions. It would
     
    6363
    6464#define SPARC_NUMBER_OF_REGISTER_WINDOWS 8
    65  
    66 /*
    67  *  This should be determined based on some soft float derived 
     65
     66/*
     67 *  This should be determined based on some soft float derived
    6868 *  cpp predefine but gcc does not currently give us that information.
    6969 */
     
    193193 *  Get and set the Y
    194194 */
    195  
     195
    196196#define sparc_get_y( _y ) \
    197197  do { \
    198198    asm volatile( "rd %%y, %0" :  "=r" (_y) : "0" (_y) ); \
    199199  } while ( 0 )
    200  
     200
    201201#define sparc_set_y( _y ) \
    202202  do { \
     
    205205
    206206/*
    207  *  Manipulate the interrupt level in the psr 
     207 *  Manipulate the interrupt level in the psr
    208208 */
    209209
    210210uint32_t sparc_disable_interrupts(void);
    211211void sparc_enable_interrupts(uint32_t);
    212  
     212
    213213#define sparc_flash_interrupts( _level ) \
    214214  do { \
  • cpukit/score/cpu/sparc/rtems/score/types.h

    r882b1875 r80f7732  
    44
    55/*
    6  *  This include file contains type definitions pertaining to the 
     6 *  This include file contains type definitions pertaining to the
    77 *  SPARC processor family.
    88 *
  • cpukit/telnetd/des.c

    r882b1875 r80f7732  
    7272
    7373#define REENTRANT
    74 /* Re-entrantify me -- all this junk needs to be in 
     74/* Re-entrantify me -- all this junk needs to be in
    7575 * struct crypt_data to make this really reentrant... */
    7676
     
    128128#define old_rawkey1 des_ctx->old_rawkey1
    129129
    130 /* Static stuff that stays resident and doesn't change after 
    131  * being initialized, and therefore doesn't need to be made 
     130/* Static stuff that stays resident and doesn't change after
     131 * being initialized, and therefore doesn't need to be made
    132132 * reentrant. */
    133133static u_char   init_perm[64], final_perm[64];
     
    242242
    243243
    244 static int 
     244static int
    245245ascii_to_bin(char ch)
    246246{
     
    774774    output[9] = '\0';
    775775    p = (u_char *)output + strlen(output);
    776   } else 
     776  } else
    777777#endif
    778778  {
  • cpukit/telnetd/genpw.c

    r882b1875 r80f7732  
    33#include <unistd.h>
    44
    5 /* 
     5/*
    66 * Authorship
    77 * ----------
     
    99 *     Till Straumann <strauman@slac.stanford.edu>, 2003-2007
    1010 *         Stanford Linear Accelerator Center, Stanford University.
    11  * 
     11 *
    1212 * Acknowledgement of sponsorship
    1313 * ------------------------------
     
    1515 *     the Stanford Linear Accelerator Center, Stanford University,
    1616 *         under Contract DE-AC03-76SFO0515 with the Department of Energy.
    17  * 
     17 *
    1818 * Government disclaimer of liability
    1919 * ----------------------------------
     
    2424 * disclosed, or represents that its use would not infringe privately owned
    2525 * rights.
    26  * 
     26 *
    2727 * Stanford disclaimer of liability
    2828 * --------------------------------
    2929 * Stanford University makes no representations or warranties, express or
    3030 * implied, nor assumes any liability for the use of this software.
    31  * 
     31 *
    3232 * Stanford disclaimer of copyright
    3333 * --------------------------------
    3434 * Stanford University, owner of the copyright, hereby disclaims its
    3535 * copyright and all other rights in this software.  Hence, anyone may
    36  * freely use it for any purpose without restriction. 
    37  * 
     36 * freely use it for any purpose without restriction.
     37 *
    3838 * Maintenance of notices
    3939 * ----------------------
     
    4444 * software made or distributed by the recipient that contains a copy or
    4545 * derivative of this software.
    46  * 
     46 *
    4747 * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
    48  */ 
     48 */
    4949static void
    5050usage(char *nm)
  • cpukit/telnetd/icmds.c

    r882b1875 r80f7732  
    5555
    5656void _rtems_telnetd_register_icmds(void) {
    57  rtems_shell_add_cmd("inet"    ,"net","inet routes"               ,main_inet);   
    58  rtems_shell_add_cmd("mbuf"    ,"net","mbuf stats"                ,main_mbuf);   
    59  rtems_shell_add_cmd("if"      ,"net","if   stats"                ,main_if  );   
    60  rtems_shell_add_cmd("ip"      ,"net","ip   stats"                ,main_ip  );   
    61  rtems_shell_add_cmd("icmp"    ,"net","icmp stats"                ,main_icmp);   
    62  rtems_shell_add_cmd("tcp"     ,"net","tcp  stats"                ,main_tcp );   
    63  rtems_shell_add_cmd("udp"     ,"net","udp  stats"                ,main_udp );   
     57 rtems_shell_add_cmd("inet"    ,"net","inet routes"               ,main_inet);
     58 rtems_shell_add_cmd("mbuf"    ,"net","mbuf stats"                ,main_mbuf);
     59 rtems_shell_add_cmd("if"      ,"net","if   stats"                ,main_if  );
     60 rtems_shell_add_cmd("ip"      ,"net","ip   stats"                ,main_ip  );
     61 rtems_shell_add_cmd("icmp"    ,"net","icmp stats"                ,main_icmp);
     62 rtems_shell_add_cmd("tcp"     ,"net","tcp  stats"                ,main_tcp );
     63 rtems_shell_add_cmd("udp"     ,"net","udp  stats"                ,main_udp );
    6464}
  • cpukit/telnetd/pty.c

    r882b1875 r80f7732  
    1818 *     they may cleanup. Some magic hack works around termios
    1919 *     limitation.
    20  * 
     20 *
    2121 *  $Id$
    2222 */
     
    7878 int                       socket;
    7979 int                       last_cr;
    80  unsigned                  iac_mode;   
    81  unsigned char             sb_buf[SB_MAX]; 
     80 unsigned                  iac_mode;
     81 unsigned char             sb_buf[SB_MAX];
    8282 int                       sb_ind;
    8383 int                       width;
     
    9393
    9494/* This procedure returns the devname for a pty slot free.
    95  * If not slot availiable (field socket>=0) 
     95 * If not slot availiable (field socket>=0)
    9696 *  then the socket argument is closed
    9797 */
     
    111111      return NULL;
    112112    }
    113      
     113
    114114    for (ndx=0;ndx<rtems_telnetd_maximum_ptys;ndx++) {
    115115
     
    133133/*
    134134 * The NVT terminal is negociated in PollRead and PollWrite
    135  * with every BYTE sendded or received. 
    136  * A litle status machine in the pty_read_byte(int minor) 
    137  * 
     135 * with every BYTE sendded or received.
     136 * A litle status machine in the pty_read_byte(int minor)
     137 *
    138138 */
    139139static const char IAC_AYT_RSP[]="\r\nAYT? Yes, RTEMS-SHELL is here\r\n";
     
    270270       case IAC_WILL:
    271271           if (value==34){
    272               send_iac(minor,IAC_DONT,   34);  /*LINEMODE*/ 
     272              send_iac(minor,IAC_DONT,   34);  /*LINEMODE*/
    273273              send_iac(minor,IAC_DO  ,    1);  /*ECHO    */
    274274           } else if (value==31) {
     
    286286           if (value==3) {
    287287              send_iac(minor,IAC_WILL,    3);  /* GO AHEAD*/
    288            } else  if (value==1) {                         
     288           } else  if (value==1) {
    289289              /* ECHO */
    290290           } else {
     
    304304              return -1;
    305305           } else {
    306               result=value; 
     306              result=value;
    307307              if ( 0
    308308#if 0               /* pass CRLF through - they should use termios to handle it */
     
    328328static const rtems_termios_callbacks * pty_get_termios_handlers(int polled) ;
    329329/*-----------------------------------------------------------*/
    330 /* Set the 'Hardware'                                        */ 
     330/* Set the 'Hardware'                                        */
    331331/*-----------------------------------------------------------*/
    332332static int
     
    340340}
    341341/*-----------------------------------------------------------*/
    342 static int 
     342static int
    343343ptyPollInitialize(int major,int minor,void * arg) {
    344344  rtems_libio_open_close_args_t * args = (rtems_libio_open_close_args_t*)arg;
     
    359359}
    360360/*-----------------------------------------------------------*/
    361 static int 
     361static int
    362362ptyShutdown(int major,int minor,void * arg) {
    363363  if (minor<rtems_telnetd_maximum_ptys) {
     
    372372}
    373373/*-----------------------------------------------------------*/
    374 /* Write Characters into pty device                          */ 
     374/* Write Characters into pty device                          */
    375375/*-----------------------------------------------------------*/
    376376static int
     
    426426  telnet_ptys = malloc( rtems_telnetd_maximum_ptys * sizeof (pty_t) );
    427427
    428   /* 
     428  /*
    429429   * Set up ptys
    430430   */
     
    511511  return sc;
    512512}
    513  
     513
    514514/*
    515515 *  Close entry point
  • cpukit/telnetd/pty.h

    r882b1875 r80f7732  
    88 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    99 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
    10  * 
     10 *
    1111 *  $Id$
    1212 */
     
    2525
    2626/* Return the devname for a free pty slot.
    27  * If no slot available (socket>=0) 
     27 * If no slot available (socket>=0)
    2828 * then the socket argument is closed
    2929 */
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