Index: freebsd/sys/arm/lpc/if_lpe.c
===================================================================
--- freebsd/sys/arm/lpc/if_lpe.c	(revision 803a4950f214d80f8f1ce3caf4ad0bf9956c27d9)
+++ freebsd/sys/arm/lpc/if_lpe.c	(revision 803a4950f214d80f8f1ce3caf4ad0bf9956c27d9)
@@ -0,0 +1,1234 @@
+#include <machine/rtems-bsd-kernel-space.h>
+
+/*-
+ * Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <rtems/bsd/sys/param.h>
+#include <sys/endian.h>
+#include <sys/systm.h>
+#include <sys/sockio.h>
+#include <sys/mbuf.h>
+#include <sys/malloc.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <rtems/bsd/sys/lock.h>
+#include <sys/mutex.h>
+#include <sys/rman.h>
+#include <sys/bus.h>
+#include <sys/socket.h>
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <net/if.h>
+#include <net/if_arp.h>
+#include <net/ethernet.h>
+#include <net/if_dl.h>
+#include <net/if_media.h>
+#include <net/if_types.h>
+#include <net/if_var.h>
+
+#include <net/bpf.h>
+
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <dev/mii/mii.h>
+#include <dev/mii/miivar.h>
+
+#include <arm/lpc/lpcreg.h>
+#include <arm/lpc/lpcvar.h>
+#include <arm/lpc/if_lpereg.h>
+
+#include <rtems/bsd/local/miibus_if.h>
+
+#ifdef DEBUG
+#define debugf(fmt, args...) do { printf("%s(): ", __func__);   \
+    printf(fmt,##args); } while (0)
+#else
+#define debugf(fmt, args...)
+#endif
+
+struct lpe_dmamap_arg {
+	bus_addr_t		lpe_dma_busaddr;
+};
+
+struct lpe_rxdesc {
+	struct mbuf *		lpe_rxdesc_mbuf;
+	bus_dmamap_t		lpe_rxdesc_dmamap;
+};
+
+struct lpe_txdesc {
+	int			lpe_txdesc_first;
+	struct mbuf *		lpe_txdesc_mbuf;
+	bus_dmamap_t		lpe_txdesc_dmamap;
+};
+
+struct lpe_chain_data {
+	bus_dma_tag_t		lpe_parent_tag;
+	bus_dma_tag_t		lpe_tx_ring_tag;
+	bus_dmamap_t		lpe_tx_ring_map;
+	bus_dma_tag_t		lpe_tx_status_tag;
+	bus_dmamap_t		lpe_tx_status_map;
+	bus_dma_tag_t		lpe_tx_buf_tag;
+	bus_dma_tag_t		lpe_rx_ring_tag;
+	bus_dmamap_t		lpe_rx_ring_map;
+	bus_dma_tag_t		lpe_rx_status_tag;
+	bus_dmamap_t		lpe_rx_status_map;
+	bus_dma_tag_t		lpe_rx_buf_tag;
+	struct lpe_rxdesc	lpe_rx_desc[LPE_RXDESC_NUM];
+	struct lpe_txdesc	lpe_tx_desc[LPE_TXDESC_NUM];
+	int			lpe_tx_prod;
+	int			lpe_tx_last;
+	int			lpe_tx_used;
+};
+
+struct lpe_ring_data {
+	struct lpe_hwdesc *	lpe_rx_ring;
+	struct lpe_hwstatus *	lpe_rx_status;
+	bus_addr_t		lpe_rx_ring_phys;
+	bus_addr_t		lpe_rx_status_phys;
+	struct lpe_hwdesc *	lpe_tx_ring;
+	struct lpe_hwstatus *	lpe_tx_status;
+	bus_addr_t		lpe_tx_ring_phys;
+	bus_addr_t		lpe_tx_status_phys;
+};
+
+struct lpe_softc {
+	struct ifnet *		lpe_ifp;
+	struct mtx		lpe_mtx;
+	phandle_t		lpe_ofw;
+	device_t		lpe_dev;
+	device_t		lpe_miibus;
+	uint8_t			lpe_enaddr[6];
+	struct resource	*	lpe_mem_res;
+	struct resource *	lpe_irq_res;
+	void *			lpe_intrhand;
+	bus_space_tag_t		lpe_bst;
+	bus_space_handle_t	lpe_bsh;
+#define	LPE_FLAG_LINK		(1 << 0)
+	uint32_t		lpe_flags;
+	int			lpe_watchdog_timer;
+	struct callout		lpe_tick;
+	struct lpe_chain_data	lpe_cdata;
+	struct lpe_ring_data	lpe_rdata;
+};
+
+static int lpe_probe(device_t);
+static int lpe_attach(device_t);
+static int lpe_detach(device_t);
+static int lpe_miibus_readreg(device_t, int, int);
+static int lpe_miibus_writereg(device_t, int, int, int);
+static void lpe_miibus_statchg(device_t);
+
+static void lpe_reset(struct lpe_softc *);
+static void lpe_init(void *);
+static void lpe_init_locked(struct lpe_softc *);
+static void lpe_start(struct ifnet *);
+static void lpe_start_locked(struct ifnet *);
+static void lpe_stop(struct lpe_softc *);
+static void lpe_stop_locked(struct lpe_softc *);
+static int lpe_ioctl(struct ifnet *, u_long, caddr_t);
+static void lpe_set_rxmode(struct lpe_softc *);
+static void lpe_set_rxfilter(struct lpe_softc *);
+static void lpe_intr(void *);
+static void lpe_rxintr(struct lpe_softc *);
+static void lpe_txintr(struct lpe_softc *);
+static void lpe_tick(void *);
+static void lpe_watchdog(struct lpe_softc *);
+static int lpe_encap(struct lpe_softc *, struct mbuf **);
+static int lpe_dma_alloc(struct lpe_softc *);
+static int lpe_dma_alloc_rx(struct lpe_softc *);
+static int lpe_dma_alloc_tx(struct lpe_softc *);
+static int lpe_init_rx(struct lpe_softc *);
+static int lpe_init_rxbuf(struct lpe_softc *, int);
+static void lpe_discard_rxbuf(struct lpe_softc *, int);
+static void lpe_dmamap_cb(void *, bus_dma_segment_t *, int, int);
+static int lpe_ifmedia_upd(struct ifnet *);
+static void lpe_ifmedia_sts(struct ifnet *, struct ifmediareq *);
+
+#define	lpe_lock(_sc)		mtx_lock(&(_sc)->lpe_mtx)
+#define	lpe_unlock(_sc)		mtx_unlock(&(_sc)->lpe_mtx)
+#define	lpe_lock_assert(_sc)	mtx_assert(&(_sc)->lpe_mtx, MA_OWNED)
+
+#define	lpe_read_4(_sc, _reg)		\
+    bus_space_read_4((_sc)->lpe_bst, (_sc)->lpe_bsh, (_reg))
+#define	lpe_write_4(_sc, _reg, _val)	\
+    bus_space_write_4((_sc)->lpe_bst, (_sc)->lpe_bsh, (_reg), (_val))
+
+#define	LPE_HWDESC_RXERRS	(LPE_HWDESC_CRCERROR | LPE_HWDESC_SYMBOLERROR | \
+    LPE_HWDESC_LENGTHERROR | LPE_HWDESC_ALIGNERROR | LPE_HWDESC_OVERRUN | \
+    LPE_HWDESC_RXNODESCR)
+
+#define	LPE_HWDESC_TXERRS	(LPE_HWDESC_EXCDEFER | LPE_HWDESC_EXCCOLL | \
+    LPE_HWDESC_LATECOLL | LPE_HWDESC_UNDERRUN | LPE_HWDESC_TXNODESCR)
+
+static int
+lpe_probe(device_t dev)
+{
+
+	if (!ofw_bus_status_okay(dev))
+		return (ENXIO);
+
+	if (!ofw_bus_is_compatible(dev, "lpc,ethernet"))
+		return (ENXIO);
+
+	device_set_desc(dev, "LPC32x0 10/100 Ethernet");
+	return (BUS_PROBE_DEFAULT);
+}
+
+static int
+lpe_attach(device_t dev)
+{
+	struct lpe_softc *sc = device_get_softc(dev);
+	struct ifnet *ifp;
+	int rid, i;
+	uint32_t val;
+
+	sc->lpe_dev = dev;
+	sc->lpe_ofw = ofw_bus_get_node(dev);
+
+	i = OF_getprop(sc->lpe_ofw, "local-mac-address", (void *)&sc->lpe_enaddr, 6);
+	if (i != 6) {
+		sc->lpe_enaddr[0] = 0x00;
+		sc->lpe_enaddr[1] = 0x11;
+		sc->lpe_enaddr[2] = 0x22;
+		sc->lpe_enaddr[3] = 0x33;
+		sc->lpe_enaddr[4] = 0x44;
+		sc->lpe_enaddr[5] = 0x55;
+	}
+
+	mtx_init(&sc->lpe_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK,
+	    MTX_DEF);
+
+	callout_init_mtx(&sc->lpe_tick, &sc->lpe_mtx, 0);
+
+	rid = 0;
+	sc->lpe_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid,
+	    RF_ACTIVE);
+	if (!sc->lpe_mem_res) {
+		device_printf(dev, "cannot allocate memory window\n");
+		goto fail;
+	}
+
+	sc->lpe_bst = rman_get_bustag(sc->lpe_mem_res);
+	sc->lpe_bsh = rman_get_bushandle(sc->lpe_mem_res);
+
+	rid = 0;
+	sc->lpe_irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
+	    RF_ACTIVE);
+	if (!sc->lpe_irq_res) {
+		device_printf(dev, "cannot allocate interrupt\n");
+		goto fail;
+	}
+
+	sc->lpe_ifp = if_alloc(IFT_ETHER);
+	if (!sc->lpe_ifp) {
+		device_printf(dev, "cannot allocated ifnet\n");
+		goto fail;
+	}
+
+	ifp = sc->lpe_ifp;
+
+	if_initname(ifp, device_get_name(dev), device_get_unit(dev));
+	ifp->if_softc = sc;
+	ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
+	ifp->if_start = lpe_start;
+	ifp->if_ioctl = lpe_ioctl;
+	ifp->if_init = lpe_init;
+	IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN);
+	ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN;
+	IFQ_SET_READY(&ifp->if_snd);
+
+	ether_ifattach(ifp, sc->lpe_enaddr);
+
+	if (bus_setup_intr(dev, sc->lpe_irq_res, INTR_TYPE_NET, NULL,
+	    lpe_intr, sc, &sc->lpe_intrhand)) {
+		device_printf(dev, "cannot establish interrupt handler\n");
+		ether_ifdetach(ifp);
+		goto fail;
+	}
+
+	/* Enable Ethernet clock */
+	lpc_pwr_write(dev, LPC_CLKPWR_MACCLK_CTRL,
+	    LPC_CLKPWR_MACCLK_CTRL_REG |
+	    LPC_CLKPWR_MACCLK_CTRL_SLAVE |
+	    LPC_CLKPWR_MACCLK_CTRL_MASTER |
+	    LPC_CLKPWR_MACCLK_CTRL_HDWINF(3));
+
+	/* Reset chip */
+	lpe_reset(sc);
+
+	/* Initialize MII */
+	val = lpe_read_4(sc, LPE_COMMAND);
+	lpe_write_4(sc, LPE_COMMAND, val | LPE_COMMAND_RMII);
+
+	if (mii_attach(dev, &sc->lpe_miibus, ifp, lpe_ifmedia_upd,
+	    lpe_ifmedia_sts, BMSR_DEFCAPMASK, 0x01, 
+	    MII_OFFSET_ANY, 0)) {
+		device_printf(dev, "cannot find PHY\n");
+		goto fail;
+	}
+
+	lpe_dma_alloc(sc);
+
+	return (0);
+
+fail:
+	if (sc->lpe_ifp)
+		if_free(sc->lpe_ifp);
+	if (sc->lpe_intrhand)
+		bus_teardown_intr(dev, sc->lpe_irq_res, sc->lpe_intrhand);
+	if (sc->lpe_irq_res)
+		bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lpe_irq_res);
+	if (sc->lpe_mem_res)
+		bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lpe_mem_res);
+	return (ENXIO);
+}
+
+static int
+lpe_detach(device_t dev)
+{
+	struct lpe_softc *sc = device_get_softc(dev);
+
+	lpe_stop(sc);
+
+	if_free(sc->lpe_ifp);
+	bus_teardown_intr(dev, sc->lpe_irq_res, sc->lpe_intrhand);
+	bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lpe_irq_res);
+	bus_release_resource(dev, SYS_RES_MEMORY, 0, sc->lpe_mem_res);
+
+	return (0);
+}
+
+static int
+lpe_miibus_readreg(device_t dev, int phy, int reg)
+{
+	struct lpe_softc *sc = device_get_softc(dev);
+	uint32_t val;
+	int result;
+
+	lpe_write_4(sc, LPE_MCMD, LPE_MCMD_READ);
+	lpe_write_4(sc, LPE_MADR, 
+	    (reg & LPE_MADR_REGMASK) << LPE_MADR_REGSHIFT |
+	    (phy & LPE_MADR_PHYMASK) << LPE_MADR_PHYSHIFT);
+
+	val = lpe_read_4(sc, LPE_MIND);
+
+	/* Wait until request is completed */
+	while (val & LPE_MIND_BUSY) {
+		val = lpe_read_4(sc, LPE_MIND);
+		DELAY(10);
+	}
+
+	if (val & LPE_MIND_INVALID)
+		return (0);
+
+	lpe_write_4(sc, LPE_MCMD, 0);
+	result = (lpe_read_4(sc, LPE_MRDD) & LPE_MRDD_DATAMASK);
+	debugf("phy=%d reg=%d result=0x%04x\n", phy, reg, result);
+
+	return (result);
+}
+
+static int
+lpe_miibus_writereg(device_t dev, int phy, int reg, int data)
+{
+	struct lpe_softc *sc = device_get_softc(dev);
+	uint32_t val;
+
+	debugf("phy=%d reg=%d data=0x%04x\n", phy, reg, data);
+
+	lpe_write_4(sc, LPE_MCMD, LPE_MCMD_WRITE);
+	lpe_write_4(sc, LPE_MADR, 
+	    (reg & LPE_MADR_REGMASK) << LPE_MADR_REGSHIFT |
+	    (phy & LPE_MADR_PHYMASK) << LPE_MADR_PHYSHIFT);
+
+	lpe_write_4(sc, LPE_MWTD, (data & LPE_MWTD_DATAMASK));
+
+	val = lpe_read_4(sc, LPE_MIND);
+
+	/* Wait until request is completed */
+	while (val & LPE_MIND_BUSY) {
+		val = lpe_read_4(sc, LPE_MIND);
+		DELAY(10);
+	}
+
+	return (0);
+}
+
+static void
+lpe_miibus_statchg(device_t dev)
+{
+	struct lpe_softc *sc = device_get_softc(dev);
+	struct mii_data *mii = device_get_softc(sc->lpe_miibus);
+
+	lpe_lock(sc);
+
+	if ((mii->mii_media_status & IFM_ACTIVE) &&
+	    (mii->mii_media_status & IFM_AVALID))
+		sc->lpe_flags |= LPE_FLAG_LINK;
+	else
+		sc->lpe_flags &= ~LPE_FLAG_LINK;
+
+	lpe_unlock(sc);
+}
+
+static void
+lpe_reset(struct lpe_softc *sc)
+{
+	uint32_t mac1;
+
+	/* Enter soft reset mode */
+	mac1 = lpe_read_4(sc, LPE_MAC1);
+	lpe_write_4(sc, LPE_MAC1, mac1 | LPE_MAC1_SOFTRESET | LPE_MAC1_RESETTX |
+	    LPE_MAC1_RESETMCSTX | LPE_MAC1_RESETRX | LPE_MAC1_RESETMCSRX);
+
+	/* Reset registers, Tx path and Rx path */
+	lpe_write_4(sc, LPE_COMMAND, LPE_COMMAND_REGRESET |
+	    LPE_COMMAND_TXRESET | LPE_COMMAND_RXRESET);
+
+	/* Set station address */
+	lpe_write_4(sc, LPE_SA2, sc->lpe_enaddr[1] << 8 | sc->lpe_enaddr[0]);
+	lpe_write_4(sc, LPE_SA1, sc->lpe_enaddr[3] << 8 | sc->lpe_enaddr[2]);
+	lpe_write_4(sc, LPE_SA0, sc->lpe_enaddr[5] << 8 | sc->lpe_enaddr[4]);
+
+	/* Leave soft reset mode */
+	mac1 = lpe_read_4(sc, LPE_MAC1);
+	lpe_write_4(sc, LPE_MAC1, mac1 & ~(LPE_MAC1_SOFTRESET | LPE_MAC1_RESETTX |
+	    LPE_MAC1_RESETMCSTX | LPE_MAC1_RESETRX | LPE_MAC1_RESETMCSRX));
+}
+
+static void
+lpe_init(void *arg)
+{
+	struct lpe_softc *sc = (struct lpe_softc *)arg;
+
+	lpe_lock(sc);
+	lpe_init_locked(sc);
+	lpe_unlock(sc);
+}
+
+static void
+lpe_init_locked(struct lpe_softc *sc)
+{
+	struct ifnet *ifp = sc->lpe_ifp;
+	uint32_t cmd, mac1;
+
+	lpe_lock_assert(sc);
+
+	if (ifp->if_drv_flags & IFF_DRV_RUNNING)
+		return;
+
+	/* Enable Tx and Rx */
+	cmd = lpe_read_4(sc, LPE_COMMAND);
+	lpe_write_4(sc, LPE_COMMAND, cmd | LPE_COMMAND_RXENABLE |
+	    LPE_COMMAND_TXENABLE | LPE_COMMAND_PASSRUNTFRAME);
+
+	/* Enable receive */
+	mac1 = lpe_read_4(sc, LPE_MAC1);
+	lpe_write_4(sc, LPE_MAC1, /*mac1 |*/ LPE_MAC1_RXENABLE | LPE_MAC1_PASSALL);
+
+	lpe_write_4(sc, LPE_MAC2, LPE_MAC2_CRCENABLE | LPE_MAC2_PADCRCENABLE |
+	    LPE_MAC2_FULLDUPLEX);
+
+	lpe_write_4(sc, LPE_MCFG, LPE_MCFG_CLKSEL(7));
+
+	/* Set up Rx filter */
+	lpe_set_rxmode(sc);
+
+	/* Enable interrupts */
+	lpe_write_4(sc, LPE_INTENABLE, LPE_INT_RXOVERRUN | LPE_INT_RXERROR |
+	    LPE_INT_RXFINISH | LPE_INT_RXDONE | LPE_INT_TXUNDERRUN | 
+	    LPE_INT_TXERROR | LPE_INT_TXFINISH | LPE_INT_TXDONE);
+
+	sc->lpe_cdata.lpe_tx_prod = 0;
+	sc->lpe_cdata.lpe_tx_last = 0;
+	sc->lpe_cdata.lpe_tx_used = 0;
+
+	lpe_init_rx(sc);
+
+	/* Initialize Rx packet and status descriptor heads */
+	lpe_write_4(sc, LPE_RXDESC, sc->lpe_rdata.lpe_rx_ring_phys);
+	lpe_write_4(sc, LPE_RXSTATUS, sc->lpe_rdata.lpe_rx_status_phys);
+	lpe_write_4(sc, LPE_RXDESC_NUMBER, LPE_RXDESC_NUM - 1);
+	lpe_write_4(sc, LPE_RXDESC_CONS, 0);
+
+	/* Initialize Tx packet and status descriptor heads */
+	lpe_write_4(sc, LPE_TXDESC, sc->lpe_rdata.lpe_tx_ring_phys);
+	lpe_write_4(sc, LPE_TXSTATUS, sc->lpe_rdata.lpe_tx_status_phys);
+	lpe_write_4(sc, LPE_TXDESC_NUMBER, LPE_TXDESC_NUM - 1);
+	lpe_write_4(sc, LPE_TXDESC_PROD, 0);
+
+	ifp->if_drv_flags |= IFF_DRV_RUNNING;
+	ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+
+	callout_reset(&sc->lpe_tick, hz, lpe_tick, sc);
+}
+
+static void
+lpe_start(struct ifnet *ifp)
+{
+	struct lpe_softc *sc = (struct lpe_softc *)ifp->if_softc;
+
+	lpe_lock(sc);
+	lpe_start_locked(ifp);
+	lpe_unlock(sc);
+}
+
+static void
+lpe_start_locked(struct ifnet *ifp)
+{
+	struct lpe_softc *sc = (struct lpe_softc *)ifp->if_softc;
+	struct mbuf *m_head;
+	int encap = 0;
+
+	lpe_lock_assert(sc);
+
+	while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) {
+		if (lpe_read_4(sc, LPE_TXDESC_PROD) ==
+		    lpe_read_4(sc, LPE_TXDESC_CONS) - 5)
+			break;
+
+		/* Dequeue first packet */
+		IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head);
+		if (!m_head)
+			break;
+
+		lpe_encap(sc, &m_head);
+
+		encap++;
+	}
+
+	/* Submit new descriptor list */
+	if (encap) {
+		lpe_write_4(sc, LPE_TXDESC_PROD, sc->lpe_cdata.lpe_tx_prod);
+		sc->lpe_watchdog_timer = 5;
+	}
+	
+}
+
+static int
+lpe_encap(struct lpe_softc *sc, struct mbuf **m_head)
+{
+	struct lpe_txdesc *txd;
+	struct lpe_hwdesc *hwd;
+	bus_dma_segment_t segs[LPE_MAXFRAGS];
+	int i, err, nsegs, prod;
+
+	lpe_lock_assert(sc);
+	M_ASSERTPKTHDR((*m_head));
+
+	prod = sc->lpe_cdata.lpe_tx_prod;
+	txd = &sc->lpe_cdata.lpe_tx_desc[prod];
+
+	debugf("starting with prod=%d\n", prod);
+
+	err = bus_dmamap_load_mbuf_sg(sc->lpe_cdata.lpe_tx_buf_tag,
+	    txd->lpe_txdesc_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT);
+
+	if (err)
+		return (err);
+
+	if (nsegs == 0) {
+		m_freem(*m_head);
+		*m_head = NULL;
+		return (EIO);
+	}
+
+        bus_dmamap_sync(sc->lpe_cdata.lpe_tx_buf_tag, txd->lpe_txdesc_dmamap,
+          BUS_DMASYNC_PREREAD);
+        bus_dmamap_sync(sc->lpe_cdata.lpe_tx_ring_tag, sc->lpe_cdata.lpe_tx_ring_map,
+            BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
+
+	txd->lpe_txdesc_first = 1;
+	txd->lpe_txdesc_mbuf = *m_head;
+
+	for (i = 0; i < nsegs; i++) {
+		hwd = &sc->lpe_rdata.lpe_tx_ring[prod];
+		hwd->lhr_data = segs[i].ds_addr;
+		hwd->lhr_control = segs[i].ds_len - 1;
+
+		if (i == nsegs - 1) {
+			hwd->lhr_control |= LPE_HWDESC_LASTFLAG;
+			hwd->lhr_control |= LPE_HWDESC_INTERRUPT;
+			hwd->lhr_control |= LPE_HWDESC_CRC;
+			hwd->lhr_control |= LPE_HWDESC_PAD;
+		}
+
+		LPE_INC(prod, LPE_TXDESC_NUM);
+	}
+
+	bus_dmamap_sync(sc->lpe_cdata.lpe_tx_ring_tag, sc->lpe_cdata.lpe_tx_ring_map,
+	    BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE);
+
+	sc->lpe_cdata.lpe_tx_used += nsegs;
+	sc->lpe_cdata.lpe_tx_prod = prod;
+
+	return (0);
+}
+
+static void
+lpe_stop(struct lpe_softc *sc)
+{
+	lpe_lock(sc);
+	lpe_stop_locked(sc);
+	lpe_unlock(sc);
+}
+
+static void
+lpe_stop_locked(struct lpe_softc *sc)
+{
+	lpe_lock_assert(sc);
+
+	callout_stop(&sc->lpe_tick);
+
+	/* Disable interrupts */
+	lpe_write_4(sc, LPE_INTCLEAR, 0xffffffff);
+
+	/* Stop EMAC */
+	lpe_write_4(sc, LPE_MAC1, 0);
+	lpe_write_4(sc, LPE_MAC2, 0);
+	lpe_write_4(sc, LPE_COMMAND, 0);
+
+	sc->lpe_ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
+	sc->lpe_ifp->if_drv_flags &= ~IFF_DRV_RUNNING;
+}
+
+static int
+lpe_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
+{
+	struct lpe_softc *sc = ifp->if_softc;
+	struct mii_data *mii = device_get_softc(sc->lpe_miibus);
+	struct ifreq *ifr = (struct ifreq *)data;
+	int err = 0;
+
+	switch (cmd) {
+	case SIOCSIFFLAGS:
+		lpe_lock(sc);
+		if (ifp->if_flags & IFF_UP) {
+			if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
+				lpe_set_rxmode(sc);
+				lpe_set_rxfilter(sc);
+			} else
+				lpe_init_locked(sc);
+		} else
+			lpe_stop(sc);
+		lpe_unlock(sc);
+		break;
+	case SIOCADDMULTI:
+	case SIOCDELMULTI:
+		if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
+			lpe_lock(sc);
+			lpe_set_rxfilter(sc);
+			lpe_unlock(sc);
+		}
+		break;
+	case SIOCGIFMEDIA:
+	case SIOCSIFMEDIA:
+		err = ifmedia_ioctl(ifp, ifr, &mii->mii_media, cmd);
+		break;
+	default:
+		err = ether_ioctl(ifp, cmd, data);
+		break;
+	}
+
+	return (err);
+}
+
+static void lpe_set_rxmode(struct lpe_softc *sc)
+{
+	struct ifnet *ifp = sc->lpe_ifp;
+	uint32_t rxfilt;
+
+	rxfilt = LPE_RXFILTER_UNIHASH | LPE_RXFILTER_MULTIHASH | LPE_RXFILTER_PERFECT;
+
+	if (ifp->if_flags & IFF_BROADCAST)
+		rxfilt |= LPE_RXFILTER_BROADCAST;
+
+	if (ifp->if_flags & IFF_PROMISC)
+		rxfilt |= LPE_RXFILTER_UNICAST | LPE_RXFILTER_MULTICAST;
+
+	if (ifp->if_flags & IFF_ALLMULTI)
+		rxfilt |= LPE_RXFILTER_MULTICAST;
+
+	lpe_write_4(sc, LPE_RXFILTER_CTRL, rxfilt);
+}
+
+static void lpe_set_rxfilter(struct lpe_softc *sc)
+{
+	struct ifnet *ifp = sc->lpe_ifp;
+	struct ifmultiaddr *ifma;
+	int index;
+	uint32_t hashl, hashh;
+
+	hashl = 0;
+	hashh = 0;
+
+	if_maddr_rlock(ifp);
+	TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) {
+		if (ifma->ifma_addr->sa_family != AF_LINK)
+			continue;
+
+		index = ether_crc32_be(LLADDR((struct sockaddr_dl *)
+		    ifma->ifma_addr), ETHER_ADDR_LEN) >> 23 & 0x3f;
+
+		if (index > 31)
+			hashh |= (1 << (index - 32));
+		else
+			hashl |= (1 << index);
+	}
+	if_maddr_runlock(ifp);
+
+	/* Program new hash filter */
+	lpe_write_4(sc, LPE_HASHFILTER_L, hashl);
+	lpe_write_4(sc, LPE_HASHFILTER_H, hashh);
+}
+
+static void
+lpe_intr(void *arg)
+{
+	struct lpe_softc *sc = (struct lpe_softc *)arg;
+	uint32_t intstatus;
+
+	debugf("status=0x%08x\n", lpe_read_4(sc, LPE_INTSTATUS));
+
+	lpe_lock(sc);
+
+	while ((intstatus = lpe_read_4(sc, LPE_INTSTATUS))) {
+		if (intstatus & LPE_INT_RXDONE)
+			lpe_rxintr(sc);
+
+		if (intstatus & LPE_INT_TXDONE)
+			lpe_txintr(sc);
+	
+		lpe_write_4(sc, LPE_INTCLEAR, 0xffff);
+	}
+
+	lpe_unlock(sc);
+}
+
+static void
+lpe_rxintr(struct lpe_softc *sc)
+{
+	struct ifnet *ifp = sc->lpe_ifp;
+	struct lpe_hwdesc *hwd;
+	struct lpe_hwstatus *hws;
+	struct lpe_rxdesc *rxd;
+	struct mbuf *m;
+	int prod, cons;
+
+	for (;;) {
+		prod = lpe_read_4(sc, LPE_RXDESC_PROD);
+		cons = lpe_read_4(sc, LPE_RXDESC_CONS);
+		
+		if (prod == cons)
+			break;
+
+		rxd = &sc->lpe_cdata.lpe_rx_desc[cons];
+		hwd = &sc->lpe_rdata.lpe_rx_ring[cons];
+		hws = &sc->lpe_rdata.lpe_rx_status[cons];
+
+		/* Check received frame for errors */
+		if (hws->lhs_info & LPE_HWDESC_RXERRS) {
+			if_inc_counter(ifp, IFCOUNTER_IERRORS, 1);
+			lpe_discard_rxbuf(sc, cons);
+			lpe_init_rxbuf(sc, cons);
+			goto skip;
+		}
+
+		m = rxd->lpe_rxdesc_mbuf;
+		m->m_pkthdr.rcvif = ifp;
+		m->m_data += 2;
+
+		if_inc_counter(ifp, IFCOUNTER_IPACKETS, 1);
+
+		lpe_unlock(sc);
+		(*ifp->if_input)(ifp, m);	
+		lpe_lock(sc);
+
+		lpe_init_rxbuf(sc, cons);
+skip:
+		LPE_INC(cons, LPE_RXDESC_NUM);
+		lpe_write_4(sc, LPE_RXDESC_CONS, cons);
+	}
+}
+
+static void
+lpe_txintr(struct lpe_softc *sc)
+{
+	struct ifnet *ifp = sc->lpe_ifp;
+	struct lpe_hwdesc *hwd;
+	struct lpe_hwstatus *hws;
+	struct lpe_txdesc *txd;
+	int cons, last;
+
+	for (;;) {
+		cons = lpe_read_4(sc, LPE_TXDESC_CONS);
+		last = sc->lpe_cdata.lpe_tx_last;
+		
+		if (cons == last)
+			break;
+
+		txd = &sc->lpe_cdata.lpe_tx_desc[last];
+		hwd = &sc->lpe_rdata.lpe_tx_ring[last];
+		hws = &sc->lpe_rdata.lpe_tx_status[last];
+
+		bus_dmamap_sync(sc->lpe_cdata.lpe_tx_buf_tag,
+		    txd->lpe_txdesc_dmamap, BUS_DMASYNC_POSTWRITE);
+
+		if_inc_counter(ifp, IFCOUNTER_COLLISIONS, LPE_HWDESC_COLLISIONS(hws->lhs_info));
+
+		if (hws->lhs_info & LPE_HWDESC_TXERRS)
+			if_inc_counter(ifp, IFCOUNTER_OERRORS, 1);
+		else
+			if_inc_counter(ifp, IFCOUNTER_OPACKETS, 1);
+
+		if (txd->lpe_txdesc_first) {
+			bus_dmamap_unload(sc->lpe_cdata.lpe_tx_buf_tag,
+			    txd->lpe_txdesc_dmamap);	
+
+			m_freem(txd->lpe_txdesc_mbuf);
+			txd->lpe_txdesc_mbuf = NULL;
+			txd->lpe_txdesc_first = 0;
+		}
+
+		sc->lpe_cdata.lpe_tx_used--;
+		LPE_INC(sc->lpe_cdata.lpe_tx_last, LPE_TXDESC_NUM);
+	}
+
+	if (!sc->lpe_cdata.lpe_tx_used)
+		sc->lpe_watchdog_timer = 0;
+}
+
+static void
+lpe_tick(void *arg)
+{
+	struct lpe_softc *sc = (struct lpe_softc *)arg;
+	struct mii_data *mii = device_get_softc(sc->lpe_miibus);
+
+	lpe_lock_assert(sc);
+	
+	mii_tick(mii);
+	lpe_watchdog(sc);
+
+	callout_reset(&sc->lpe_tick, hz, lpe_tick, sc);
+}
+
+static void
+lpe_watchdog(struct lpe_softc *sc)
+{
+	struct ifnet *ifp = sc->lpe_ifp;
+
+	lpe_lock_assert(sc);
+
+	if (sc->lpe_watchdog_timer == 0 || sc->lpe_watchdog_timer--)
+		return;
+
+	/* Chip has stopped responding */
+	device_printf(sc->lpe_dev, "WARNING: chip hangup, restarting...\n");
+	lpe_stop_locked(sc);
+	lpe_init_locked(sc);
+
+	/* Try to resend packets */
+	if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))
+		lpe_start_locked(ifp);
+}
+
+static int
+lpe_dma_alloc(struct lpe_softc *sc)
+{
+	int err;
+
+	/* Create parent DMA tag */
+	err = bus_dma_tag_create(
+	    bus_get_dma_tag(sc->lpe_dev),
+	    1, 0,			/* alignment, boundary */
+	    BUS_SPACE_MAXADDR_32BIT,	/* lowaddr */
+	    BUS_SPACE_MAXADDR,		/* highaddr */
+	    NULL, NULL,			/* filter, filterarg */
+	    BUS_SPACE_MAXSIZE_32BIT, 0,	/* maxsize, nsegments */
+	    BUS_SPACE_MAXSIZE_32BIT, 0,	/* maxsegsize, flags */
+	    NULL, NULL,			/* lockfunc, lockarg */
+	    &sc->lpe_cdata.lpe_parent_tag);
+
+	if (err) {
+		device_printf(sc->lpe_dev, "cannot create parent DMA tag\n");
+		return (err);
+	}
+
+	err = lpe_dma_alloc_rx(sc);
+	if (err)
+		return (err);
+
+	err = lpe_dma_alloc_tx(sc);
+	if (err)
+		return (err);
+
+	return (0);
+}
+
+static int
+lpe_dma_alloc_rx(struct lpe_softc *sc)
+{
+	struct lpe_rxdesc *rxd;
+	struct lpe_dmamap_arg ctx;
+	int err, i;
+
+	/* Create tag for Rx ring */
+	err = bus_dma_tag_create(
+	    sc->lpe_cdata.lpe_parent_tag,
+	    LPE_DESC_ALIGN, 0,		/* alignment, boundary */
+	    BUS_SPACE_MAXADDR,		/* lowaddr */
+	    BUS_SPACE_MAXADDR,		/* highaddr */
+	    NULL, NULL,			/* filter, filterarg */
+	    LPE_RXDESC_SIZE, 1,		/* maxsize, nsegments */
+	    LPE_RXDESC_SIZE, 0,		/* maxsegsize, flags */
+	    NULL, NULL,			/* lockfunc, lockarg */
+	    &sc->lpe_cdata.lpe_rx_ring_tag);
+
+	if (err) {
+		device_printf(sc->lpe_dev, "cannot create Rx ring DMA tag\n");
+		goto fail;
+	}
+
+	/* Create tag for Rx status ring */
+	err = bus_dma_tag_create(
+	    sc->lpe_cdata.lpe_parent_tag,
+	    LPE_DESC_ALIGN, 0,		/* alignment, boundary */
+	    BUS_SPACE_MAXADDR,		/* lowaddr */
+	    BUS_SPACE_MAXADDR,		/* highaddr */
+	    NULL, NULL,			/* filter, filterarg */
+	    LPE_RXSTATUS_SIZE, 1,	/* maxsize, nsegments */
+	    LPE_RXSTATUS_SIZE, 0,	/* maxsegsize, flags */
+	    NULL, NULL,			/* lockfunc, lockarg */
+	    &sc->lpe_cdata.lpe_rx_status_tag);
+
+	if (err) {
+		device_printf(sc->lpe_dev, "cannot create Rx status ring DMA tag\n");
+		goto fail;
+	}
+
+	/* Create tag for Rx buffers */
+	err = bus_dma_tag_create(
+	    sc->lpe_cdata.lpe_parent_tag,
+	    LPE_DESC_ALIGN, 0,		/* alignment, boundary */
+	    BUS_SPACE_MAXADDR,		/* lowaddr */
+	    BUS_SPACE_MAXADDR,		/* highaddr */
+	    NULL, NULL,			/* filter, filterarg */
+	    MCLBYTES * LPE_RXDESC_NUM,	/* maxsize */
+	    LPE_RXDESC_NUM,		/* segments */
+	    MCLBYTES, 0,		/* maxsegsize, flags */
+	    NULL, NULL,			/* lockfunc, lockarg */
+	    &sc->lpe_cdata.lpe_rx_buf_tag);
+
+	if (err) {
+		device_printf(sc->lpe_dev, "cannot create Rx buffers DMA tag\n");
+		goto fail;
+	}
+
+	/* Allocate Rx DMA ring */
+	err = bus_dmamem_alloc(sc->lpe_cdata.lpe_rx_ring_tag,
+	    (void **)&sc->lpe_rdata.lpe_rx_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT |
+	    BUS_DMA_ZERO, &sc->lpe_cdata.lpe_rx_ring_map);
+
+	err = bus_dmamap_load(sc->lpe_cdata.lpe_rx_ring_tag, 
+	    sc->lpe_cdata.lpe_rx_ring_map, sc->lpe_rdata.lpe_rx_ring,
+	    LPE_RXDESC_SIZE, lpe_dmamap_cb, &ctx, 0);
+
+	sc->lpe_rdata.lpe_rx_ring_phys = ctx.lpe_dma_busaddr;
+
+	/* Allocate Rx status ring */
+	err = bus_dmamem_alloc(sc->lpe_cdata.lpe_rx_status_tag,
+	    (void **)&sc->lpe_rdata.lpe_rx_status, BUS_DMA_WAITOK | BUS_DMA_COHERENT |
+	    BUS_DMA_ZERO, &sc->lpe_cdata.lpe_rx_status_map);
+
+	err = bus_dmamap_load(sc->lpe_cdata.lpe_rx_status_tag, 
+	    sc->lpe_cdata.lpe_rx_status_map, sc->lpe_rdata.lpe_rx_status,
+	    LPE_RXDESC_SIZE, lpe_dmamap_cb, &ctx, 0);
+
+	sc->lpe_rdata.lpe_rx_status_phys = ctx.lpe_dma_busaddr;
+
+
+	/* Create Rx buffers DMA map */
+	for (i = 0; i < LPE_RXDESC_NUM; i++) {
+		rxd = &sc->lpe_cdata.lpe_rx_desc[i];
+		rxd->lpe_rxdesc_mbuf = NULL;
+		rxd->lpe_rxdesc_dmamap = NULL;
+
+		err = bus_dmamap_create(sc->lpe_cdata.lpe_rx_buf_tag, 0,
+		    &rxd->lpe_rxdesc_dmamap);
+
+		if (err) {
+			device_printf(sc->lpe_dev, "cannot create Rx DMA map\n");
+			return (err);
+		}
+	}
+
+	return (0);
+fail:
+	return (err);
+}
+
+static int
+lpe_dma_alloc_tx(struct lpe_softc *sc)
+{
+	struct lpe_txdesc *txd;
+	struct lpe_dmamap_arg ctx;
+	int err, i;
+
+	/* Create tag for Tx ring */
+	err = bus_dma_tag_create(
+	    sc->lpe_cdata.lpe_parent_tag,
+	    LPE_DESC_ALIGN, 0,		/* alignment, boundary */
+	    BUS_SPACE_MAXADDR,		/* lowaddr */
+	    BUS_SPACE_MAXADDR,		/* highaddr */
+	    NULL, NULL,			/* filter, filterarg */
+	    LPE_TXDESC_SIZE, 1,		/* maxsize, nsegments */
+	    LPE_TXDESC_SIZE, 0,		/* maxsegsize, flags */
+	    NULL, NULL,			/* lockfunc, lockarg */
+	    &sc->lpe_cdata.lpe_tx_ring_tag);
+
+	if (err) {
+		device_printf(sc->lpe_dev, "cannot create Tx ring DMA tag\n");
+		goto fail;
+	}
+
+	/* Create tag for Tx status ring */
+	err = bus_dma_tag_create(
+	    sc->lpe_cdata.lpe_parent_tag,
+	    LPE_DESC_ALIGN, 0,		/* alignment, boundary */
+	    BUS_SPACE_MAXADDR,		/* lowaddr */
+	    BUS_SPACE_MAXADDR,		/* highaddr */
+	    NULL, NULL,			/* filter, filterarg */
+	    LPE_TXSTATUS_SIZE, 1,	/* maxsize, nsegments */
+	    LPE_TXSTATUS_SIZE, 0,	/* maxsegsize, flags */
+	    NULL, NULL,			/* lockfunc, lockarg */
+	    &sc->lpe_cdata.lpe_tx_status_tag);
+
+	if (err) {
+		device_printf(sc->lpe_dev, "cannot create Tx status ring DMA tag\n");
+		goto fail;
+	}
+
+	/* Create tag for Tx buffers */
+	err = bus_dma_tag_create(
+	    sc->lpe_cdata.lpe_parent_tag,
+	    LPE_DESC_ALIGN, 0,		/* alignment, boundary */
+	    BUS_SPACE_MAXADDR,		/* lowaddr */
+	    BUS_SPACE_MAXADDR,		/* highaddr */
+	    NULL, NULL,			/* filter, filterarg */
+	    MCLBYTES * LPE_TXDESC_NUM,	/* maxsize */
+	    LPE_TXDESC_NUM,		/* segments */
+	    MCLBYTES, 0,		/* maxsegsize, flags */
+	    NULL, NULL,			/* lockfunc, lockarg */
+	    &sc->lpe_cdata.lpe_tx_buf_tag);
+
+	if (err) {
+		device_printf(sc->lpe_dev, "cannot create Tx buffers DMA tag\n");
+		goto fail;
+	}
+
+	/* Allocate Tx DMA ring */
+	err = bus_dmamem_alloc(sc->lpe_cdata.lpe_tx_ring_tag,
+	    (void **)&sc->lpe_rdata.lpe_tx_ring, BUS_DMA_WAITOK | BUS_DMA_COHERENT |
+	    BUS_DMA_ZERO, &sc->lpe_cdata.lpe_tx_ring_map);
+
+	err = bus_dmamap_load(sc->lpe_cdata.lpe_tx_ring_tag, 
+	    sc->lpe_cdata.lpe_tx_ring_map, sc->lpe_rdata.lpe_tx_ring,
+	    LPE_RXDESC_SIZE, lpe_dmamap_cb, &ctx, 0);
+
+	sc->lpe_rdata.lpe_tx_ring_phys = ctx.lpe_dma_busaddr;
+
+	/* Allocate Tx status ring */
+	err = bus_dmamem_alloc(sc->lpe_cdata.lpe_tx_status_tag,
+	    (void **)&sc->lpe_rdata.lpe_tx_status, BUS_DMA_WAITOK | BUS_DMA_COHERENT |
+	    BUS_DMA_ZERO, &sc->lpe_cdata.lpe_tx_status_map);
+
+	err = bus_dmamap_load(sc->lpe_cdata.lpe_tx_status_tag, 
+	    sc->lpe_cdata.lpe_tx_status_map, sc->lpe_rdata.lpe_tx_status,
+	    LPE_RXDESC_SIZE, lpe_dmamap_cb, &ctx, 0);
+
+	sc->lpe_rdata.lpe_tx_status_phys = ctx.lpe_dma_busaddr;
+
+
+	/* Create Tx buffers DMA map */
+	for (i = 0; i < LPE_TXDESC_NUM; i++) {
+		txd = &sc->lpe_cdata.lpe_tx_desc[i];
+		txd->lpe_txdesc_mbuf = NULL;
+		txd->lpe_txdesc_dmamap = NULL;
+		txd->lpe_txdesc_first = 0;
+
+		err = bus_dmamap_create(sc->lpe_cdata.lpe_tx_buf_tag, 0,
+		    &txd->lpe_txdesc_dmamap);
+
+		if (err) {
+			device_printf(sc->lpe_dev, "cannot create Tx DMA map\n");
+			return (err);
+		}
+	}
+
+	return (0);
+fail:
+	return (err);
+}
+
+static int
+lpe_init_rx(struct lpe_softc *sc)
+{
+	int i, err;
+
+	for (i = 0; i < LPE_RXDESC_NUM; i++) {
+		err = lpe_init_rxbuf(sc, i);
+		if (err)
+			return (err);
+	}
+
+	return (0);
+}
+
+static int
+lpe_init_rxbuf(struct lpe_softc *sc, int n)
+{
+	struct lpe_rxdesc *rxd;
+	struct lpe_hwdesc *hwd;
+	struct lpe_hwstatus *hws;
+	struct mbuf *m;
+	bus_dma_segment_t segs[1];
+	int nsegs;
+
+	rxd = &sc->lpe_cdata.lpe_rx_desc[n];
+	hwd = &sc->lpe_rdata.lpe_rx_ring[n];
+	hws = &sc->lpe_rdata.lpe_rx_status[n];
+	m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
+
+	if (!m) {
+		device_printf(sc->lpe_dev, "WARNING: mbufs exhausted!\n");
+		return (ENOBUFS);
+	}
+
+	m->m_len = m->m_pkthdr.len = MCLBYTES;
+
+	bus_dmamap_unload(sc->lpe_cdata.lpe_rx_buf_tag, rxd->lpe_rxdesc_dmamap);
+
+	if (bus_dmamap_load_mbuf_sg(sc->lpe_cdata.lpe_rx_buf_tag, 
+	    rxd->lpe_rxdesc_dmamap, m, segs, &nsegs, 0)) {
+		m_freem(m);
+		return (ENOBUFS);
+	}
+
+	bus_dmamap_sync(sc->lpe_cdata.lpe_rx_buf_tag, rxd->lpe_rxdesc_dmamap, 
+	    BUS_DMASYNC_PREREAD);
+
+	rxd->lpe_rxdesc_mbuf = m;
+	hwd->lhr_data = segs[0].ds_addr + 2;
+	hwd->lhr_control = (segs[0].ds_len - 1) | LPE_HWDESC_INTERRUPT;
+
+	return (0);
+}
+
+static void
+lpe_discard_rxbuf(struct lpe_softc *sc, int n)
+{
+	struct lpe_rxdesc *rxd;
+	struct lpe_hwdesc *hwd;
+
+	rxd = &sc->lpe_cdata.lpe_rx_desc[n];
+	hwd = &sc->lpe_rdata.lpe_rx_ring[n];
+
+	bus_dmamap_unload(sc->lpe_cdata.lpe_rx_buf_tag, rxd->lpe_rxdesc_dmamap);
+
+	hwd->lhr_data = 0;
+	hwd->lhr_control = 0;
+
+	if (rxd->lpe_rxdesc_mbuf) {
+		m_freem(rxd->lpe_rxdesc_mbuf); 
+		rxd->lpe_rxdesc_mbuf = NULL;
+	}
+}
+
+static void
+lpe_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nseg, int error)
+{
+	struct lpe_dmamap_arg *ctx;
+
+	if (error)
+		return;
+
+	ctx = (struct lpe_dmamap_arg *)arg;
+	ctx->lpe_dma_busaddr = segs[0].ds_addr;
+}
+
+static int
+lpe_ifmedia_upd(struct ifnet *ifp)
+{
+	return (0);
+}
+
+static void
+lpe_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr)
+{
+	struct lpe_softc *sc = ifp->if_softc;
+	struct mii_data *mii = device_get_softc(sc->lpe_miibus);
+
+	lpe_lock(sc);
+	mii_pollstat(mii);
+	ifmr->ifm_active = mii->mii_media_active;
+	ifmr->ifm_status = mii->mii_media_status;
+	lpe_unlock(sc);
+}
+
+static device_method_t lpe_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		lpe_probe),
+	DEVMETHOD(device_attach,	lpe_attach),
+	DEVMETHOD(device_detach,	lpe_detach),
+
+	/* Bus interface */
+	DEVMETHOD(bus_print_child,	bus_generic_print_child),
+
+	/* MII interface */
+	DEVMETHOD(miibus_readreg,	lpe_miibus_readreg),
+	DEVMETHOD(miibus_writereg,	lpe_miibus_writereg),
+	DEVMETHOD(miibus_statchg,	lpe_miibus_statchg),
+	{ 0, 0 }
+};
+
+static driver_t lpe_driver = {
+	"lpe",
+	lpe_methods,
+	sizeof(struct lpe_softc),
+};
+
+static devclass_t lpe_devclass;
+
+DRIVER_MODULE(lpe, simplebus, lpe_driver, lpe_devclass, 0, 0);
+DRIVER_MODULE(miibus, lpe, miibus_driver, miibus_devclass, 0, 0);
+MODULE_DEPEND(lpe, obio, 1, 1, 1);
+MODULE_DEPEND(lpe, miibus, 1, 1, 1);
+MODULE_DEPEND(lpe, ether, 1, 1, 1);
Index: freebsd/sys/arm/lpc/if_lpereg.h
===================================================================
--- freebsd/sys/arm/lpc/if_lpereg.h	(revision 803a4950f214d80f8f1ce3caf4ad0bf9956c27d9)
+++ freebsd/sys/arm/lpc/if_lpereg.h	(revision 803a4950f214d80f8f1ce3caf4ad0bf9956c27d9)
@@ -0,0 +1,208 @@
+/*-
+ * Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef	_ARM_LPC_IF_LPEREG_H
+#define	_ARM_LPC_IF_LPEREG_H
+
+#define	LPE_MAC1		0x000
+#define	LPE_MAC1_RXENABLE	(1 << 0)
+#define	LPE_MAC1_PASSALL	(1 << 1)
+#define	LPE_MAC1_RXFLOWCTRL	(1 << 2)
+#define	LPE_MAC1_TXFLOWCTRL	(1 << 3)
+#define	LPE_MAC1_LOOPBACK	(1 << 4)
+#define	LPE_MAC1_RESETTX	(1 << 8)
+#define	LPE_MAC1_RESETMCSTX	(1 << 9)
+#define	LPE_MAC1_RESETRX	(1 << 10)
+#define	LPE_MAC1_RESETMCSRX	(1 << 11)
+#define	LPE_MAC1_SIMRESET	(1 << 14)
+#define	LPE_MAC1_SOFTRESET	(1 << 15)
+#define	LPE_MAC2		0x004
+#define	LPE_MAC2_FULLDUPLEX	(1 << 0)
+#define	LPE_MAC2_FRAMELENCHECK	(1 << 1)
+#define	LPE_MAC2_HUGEFRAME	(1 << 2)
+#define	LPE_MAC2_DELAYEDCRC	(1 << 3)
+#define	LPE_MAC2_CRCENABLE	(1 << 4)
+#define	LPE_MAC2_PADCRCENABLE	(1 << 5)
+#define	LPE_MAC2_VLANPADENABLE	(1 << 6)
+#define	LPE_MAC2_AUTOPADENABLE	(1 << 7)
+#define	LPE_MAC2_PUREPREAMBLE	(1 << 8)
+#define	LPE_MAC2_LONGPREAMBLE	(1 << 9)
+#define	LPE_MAC2_NOBACKOFF	(1 << 12)
+#define	LPE_MAC2_BACKPRESSURE	(1 << 13)
+#define	LPE_MAC2_EXCESSDEFER	(1 << 14)
+#define	LPE_IPGT		0x008
+#define	LPE_IPGR		0x00c
+#define	LPE_CLRT		0x010
+#define	LPE_MAXF		0x014
+#define	LPE_SUPP		0x018
+#define	LPE_SUPP_SPEED		(1 << 8)
+#define	LPE_TEST		0x01c
+#define	LPE_MCFG		0x020
+#define	LPE_MCFG_SCANINCR	(1 << 0)
+#define	LPE_MCFG_SUPPREAMBLE	(1 << 1)
+#define	LPE_MCFG_CLKSEL(_n)	((_n & 0x7) << 2)
+#define	LPC_MCFG_RESETMII	(1 << 15)
+#define	LPE_MCMD		0x024
+#define	LPE_MCMD_READ		(1 << 0)
+#define	LPE_MCMD_WRITE		(0 << 0)
+#define	LPE_MCMD_SCAN		(1 << 1)
+#define	LPE_MADR		0x028
+#define	LPE_MADR_REGMASK	0x1f
+#define	LPE_MADR_REGSHIFT	0
+#define	LPE_MADR_PHYMASK	0x1f
+#define	LPE_MADR_PHYSHIFT	8
+#define	LPE_MWTD		0x02c
+#define	LPE_MWTD_DATAMASK	0xffff
+#define	LPE_MRDD		0x030
+#define	LPE_MRDD_DATAMASK	0xffff
+#define	LPE_MIND		0x034
+#define	LPE_MIND_BUSY		(1 << 0)
+#define	LPE_MIND_SCANNING	(1 << 1)
+#define	LPE_MIND_INVALID	(1 << 2)
+#define	LPE_MIND_MIIFAIL	(1 << 3)
+#define	LPE_SA0			0x040
+#define	LPE_SA1			0x044
+#define	LPE_SA2			0x048
+#define	LPE_COMMAND		0x100
+#define	LPE_COMMAND_RXENABLE	(1 << 0)
+#define	LPE_COMMAND_TXENABLE	(1 << 1)
+#define	LPE_COMMAND_REGRESET	(1 << 3)
+#define	LPE_COMMAND_TXRESET	(1 << 4)
+#define	LPE_COMMAND_RXRESET	(1 << 5)
+#define	LPE_COMMAND_PASSRUNTFRAME	(1 << 6)
+#define	LPE_COMMAND_PASSRXFILTER	(1 << 7)
+#define	LPE_COMMAND_TXFLOWCTL		(1 << 8)
+#define	LPE_COMMAND_RMII		(1 << 9)
+#define	LPE_COMMAND_FULLDUPLEX		(1 << 10)
+#define	LPE_STATUS		0x104
+#define	LPE_STATUS_RXACTIVE		(1 << 0)
+#define	LPE_STATUS_TXACTIVE		(1 << 1)
+#define	LPE_RXDESC		0x108
+#define	LPE_RXSTATUS		0x10c
+#define	LPE_RXDESC_NUMBER	0x110
+#define	LPE_RXDESC_PROD		0x114
+#define	LPE_RXDESC_CONS		0x118
+#define	LPE_TXDESC		0x11c
+#define	LPE_TXSTATUS		0x120
+#define	LPE_TXDESC_NUMBER	0x124
+#define	LPE_TXDESC_PROD		0x128
+#define	LPE_TXDESC_CONS		0x12c
+#define	LPE_TSV0		0x158
+#define	LPE_TSV1		0x15c
+#define	LPE_RSV			0x160
+#define	LPE_FLOWCONTROL_COUNTER	0x170
+#define	LPE_FLOWCONTROL_STATUS	0x174
+#define	LPE_RXFILTER_CTRL	0x200
+#define	LPE_RXFILTER_UNICAST	(1 << 0)
+#define	LPE_RXFILTER_BROADCAST	(1 << 1)
+#define LPE_RXFILTER_MULTICAST	(1 << 2)
+#define	LPE_RXFILTER_UNIHASH	(1 << 3)
+#define	LPE_RXFILTER_MULTIHASH	(1 << 4)
+#define	LPE_RXFILTER_PERFECT	(1 << 5)
+#define	LPE_RXFILTER_WOL	(1 << 12)
+#define	LPE_RXFILTER_FILTWOL	(1 << 13)
+#define	LPE_RXFILTER_WOL_STATUS	0x204
+#define	LPE_RXFILTER_WOL_CLEAR	0x208
+#define	LPE_HASHFILTER_L	0x210
+#define	LPE_HASHFILTER_H	0x214
+#define	LPE_INTSTATUS		0xfe0
+#define	LPE_INTENABLE		0xfe4
+#define	LPE_INTCLEAR		0xfe8
+#define	LPE_INTSET		0xfec
+#define	LPE_INT_RXOVERRUN	(1 << 0)
+#define	LPE_INT_RXERROR		(1 << 1)
+#define	LPE_INT_RXFINISH	(1 << 2)
+#define	LPE_INT_RXDONE		(1 << 3)
+#define	LPE_INT_TXUNDERRUN	(1 << 4)
+#define	LPE_INT_TXERROR		(1 << 5)
+#define	LPE_INT_TXFINISH	(1 << 6)
+#define	LPE_INT_TXDONE		(1 << 7)
+#define	LPE_INT_SOFTINT		(1 << 12)
+#define	LPE_INTWAKEUPINT	(1 << 13)
+#define	LPE_POWERDOWN		0xff4
+
+#define	LPE_DESC_ALIGN		8
+#define	LPE_TXDESC_NUM		128
+#define	LPE_RXDESC_NUM		128
+#define	LPE_TXDESC_SIZE		(LPE_TXDESC_NUM * sizeof(struct lpe_hwdesc))
+#define	LPE_RXDESC_SIZE		(LPE_RXDESC_NUM * sizeof(struct lpe_hwdesc))
+#define	LPE_TXSTATUS_SIZE	(LPE_TXDESC_NUM * sizeof(struct lpe_hwstatus))
+#define	LPE_RXSTATUS_SIZE	(LPE_RXDESC_NUM * sizeof(struct lpe_hwstatus))
+#define	LPE_MAXFRAGS		8
+
+struct lpe_hwdesc {
+	uint32_t	lhr_data;
+	uint32_t	lhr_control;
+};
+
+struct lpe_hwstatus {
+	uint32_t	lhs_info;
+	uint32_t	lhs_crc;
+};
+
+#define	LPE_INC(x, y)		(x) = ((x) == ((y)-1)) ? 0 : (x)+1
+
+/* These are valid for both Rx and Tx descriptors */
+#define	LPE_HWDESC_SIZE_MASK	(1 << 10)
+#define	LPE_HWDESC_INTERRUPT	(1U << 31)
+
+/* These are valid for Tx descriptors */
+#define	LPE_HWDESC_LAST		(1 << 30)
+#define	LPE_HWDESC_CRC		(1 << 29)
+#define	LPE_HWDESC_PAD		(1 << 28)
+#define	LPE_HWDESC_HUGE		(1 << 27)
+#define	LPE_HWDESC_OVERRIDE	(1 << 26)
+
+/* These are valid for Tx status descriptors */
+#define	LPE_HWDESC_COLLISIONS(_n) (((_n) >> 21) & 0x7)
+#define	LPE_HWDESC_DEFER	(1 << 25)
+#define	LPE_HWDESC_EXCDEFER	(1 << 26)
+#define	LPE_HWDESC_EXCCOLL	(1 << 27)
+#define	LPE_HWDESC_LATECOLL	(1 << 28)
+#define	LPE_HWDESC_UNDERRUN	(1 << 29)
+#define	LPE_HWDESC_TXNODESCR	(1 << 30)
+#define	LPE_HWDESC_ERROR	(1U << 31)
+
+/* These are valid for Rx status descriptors */
+#define	LPE_HWDESC_CONTROL	(1 << 18)
+#define	LPE_HWDESC_VLAN		(1 << 19)
+#define	LPE_HWDESC_FAILFILTER	(1 << 20)
+#define	LPE_HWDESC_MULTICAST	(1 << 21)
+#define	LPE_HWDESC_BROADCAST	(1 << 22)
+#define	LPE_HWDESC_CRCERROR	(1 << 23)
+#define	LPE_HWDESC_SYMBOLERROR	(1 << 24)
+#define	LPE_HWDESC_LENGTHERROR	(1 << 25)
+#define	LPE_HWDESC_RANGEERROR	(1 << 26)
+#define	LPE_HWDESC_ALIGNERROR	(1 << 27)
+#define	LPE_HWDESC_OVERRUN	(1 << 28)
+#define	LPE_HWDESC_RXNODESCR	(1 << 29)
+#define	LPE_HWDESC_LASTFLAG	(1 << 30)
+#define	LPE_HWDESC_ERROR	(1U << 31)
+
+
+#endif	/* _ARM_LPC_IF_LPEREG_H */
Index: freebsd/sys/arm/lpc/lpc_pwr.c
===================================================================
--- freebsd/sys/arm/lpc/lpc_pwr.c	(revision 803a4950f214d80f8f1ce3caf4ad0bf9956c27d9)
+++ freebsd/sys/arm/lpc/lpc_pwr.c	(revision 803a4950f214d80f8f1ce3caf4ad0bf9956c27d9)
@@ -0,0 +1,131 @@
+#include <machine/rtems-bsd-kernel-space.h>
+
+/*-
+ * Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ */
+
+#include <sys/cdefs.h>
+__FBSDID("$FreeBSD$");
+
+#include <rtems/bsd/sys/param.h>
+#include <sys/systm.h>
+#include <sys/bus.h>
+#include <sys/kernel.h>
+#include <sys/module.h>
+#include <sys/malloc.h>
+#include <sys/rman.h>
+#include <machine/bus.h>
+#include <machine/intr.h>
+
+#include <dev/ofw/ofw_bus.h>
+#include <dev/ofw/ofw_bus_subr.h>
+
+#include <arm/lpc/lpcreg.h>
+#include <arm/lpc/lpcvar.h>
+
+struct lpc_pwr_softc {
+	device_t		dp_dev;
+	struct resource *	dp_mem_res;
+	bus_space_tag_t		dp_bst;
+	bus_space_handle_t	dp_bsh;
+};
+
+static struct lpc_pwr_softc *lpc_pwr_sc = NULL;
+
+static int lpc_pwr_probe(device_t);
+static int lpc_pwr_attach(device_t);
+
+#define	lpc_pwr_read_4(_sc, _reg)			\
+    bus_space_read_4((_sc)->dp_bst, (_sc)->dp_bsh, _reg)
+#define	lpc_pwr_write_4(_sc, _reg, _val)		\
+    bus_space_write_4((_sc)->dp_bst, (_sc)->dp_bsh, _reg, _val)
+
+static int
+lpc_pwr_probe(device_t dev)
+{
+	
+	if (!ofw_bus_status_okay(dev))
+		return (ENXIO);
+
+	if (!ofw_bus_is_compatible(dev, "lpc,pwr"))
+		return (ENXIO);
+
+	device_set_desc(dev, "LPC32x0 Power Controller");
+	return (BUS_PROBE_DEFAULT);
+}
+
+static int
+lpc_pwr_attach(device_t dev)
+{
+	struct lpc_pwr_softc *sc = device_get_softc(dev);
+	int rid;
+
+	sc->dp_dev = dev;
+
+	rid = 0;
+	sc->dp_mem_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 
+	    RF_ACTIVE);
+	if (!sc->dp_mem_res) {
+		device_printf(dev, "cannot allocate memory window\n");
+		return (ENXIO);
+	}
+
+	sc->dp_bst = rman_get_bustag(sc->dp_mem_res);
+	sc->dp_bsh = rman_get_bushandle(sc->dp_mem_res);
+
+	lpc_pwr_sc = sc;
+
+	return (0);
+}
+
+uint32_t
+lpc_pwr_read(device_t dev, int reg)
+{
+	return (lpc_pwr_read_4(lpc_pwr_sc, reg));
+}
+
+void
+lpc_pwr_write(device_t dev, int reg, uint32_t value)
+{
+	lpc_pwr_write_4(lpc_pwr_sc, reg, value);
+}
+
+static device_method_t lpc_pwr_methods[] = {
+	/* Device interface */
+	DEVMETHOD(device_probe,		lpc_pwr_probe),
+	DEVMETHOD(device_attach,	lpc_pwr_attach),
+	{ 0, 0 }
+};
+
+static devclass_t lpc_pwr_devclass;
+
+static driver_t lpc_pwr_driver = {
+	"pwr",
+	lpc_pwr_methods,
+	sizeof(struct lpc_pwr_softc),
+};
+
+DRIVER_MODULE(pwr, simplebus, lpc_pwr_driver, lpc_pwr_devclass, 0, 0);
Index: freebsd/sys/arm/lpc/lpcreg.h
===================================================================
--- freebsd/sys/arm/lpc/lpcreg.h	(revision 803a4950f214d80f8f1ce3caf4ad0bf9956c27d9)
+++ freebsd/sys/arm/lpc/lpcreg.h	(revision 803a4950f214d80f8f1ce3caf4ad0bf9956c27d9)
@@ -0,0 +1,665 @@
+/*-
+ * Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef	_ARM_LPC_LPCREG_H
+#define	_ARM_LPC_LPCREG_H
+
+#define	LPC_DEV_PHYS_BASE		0x40000000
+#define	LPC_DEV_P5_PHYS_BASE		0x20000000
+#define	LPC_DEV_P6_PHYS_BASE		0x30000000
+#define	LPC_DEV_SIZE			0x10000000
+
+/*
+ * Interrupt controller (from UM10326: LPC32x0 User manual, page 87)
+
+ */
+#define	LPC_INTC_MIC_ER			0x0000
+#define	LPC_INTC_MIC_RSR		0x0004
+#define	LPC_INTC_MIC_SR			0x0008
+#define	LPC_INTC_MIC_APR		0x000c
+#define	LPC_INTC_MIC_ATR		0x0010
+#define	LPC_INTC_MIC_ITR		0x0014
+#define	LPC_INTC_SIC1_ER		0x4000
+#define	LPC_INTC_SIC1_RSR		0x4004
+#define	LPC_INTC_SIC1_SR		0x4008
+#define	LPC_INTC_SIC1_APR		0x400c
+#define	LPC_INTC_SIC1_ATR		0x4010
+#define	LPC_INTC_SIC1_ITR		0x4014
+#define	LPC_INTC_SIC2_ER		0x8000
+#define	LPC_INTC_SIC2_RSR		0x8004
+#define	LPC_INTC_SIC2_SR		0x8008
+#define	LPC_INTC_SIC2_APR		0x800c
+#define	LPC_INTC_SIC2_ATR		0x8010
+#define	LPC_INTC_SIC2_ITR		0x8014
+
+
+/*
+ * Timer 0|1|2|3|4|5. (from UM10326: LPC32x0 User manual, page 540)
+ */
+#define	LPC_TIMER_IR			0x00
+#define	LPC_TIMER_TCR			0x04
+#define	LPC_TIMER_TCR_ENABLE		(1 << 0)
+#define	LPC_TIMER_TCR_RESET		(1 << 1)
+#define	LPC_TIMER_TC			0x08
+#define	LPC_TIMER_PR			0x0c
+#define	LPC_TIMER_PC			0x10
+#define	LPC_TIMER_MCR			0x14
+#define	LPC_TIMER_MCR_MR0I		(1 << 0)
+#define	LPC_TIMER_MCR_MR0R		(1 << 1)
+#define	LPC_TIMER_MCR_MR0S		(1 << 2)
+#define	LPC_TIMER_MCR_MR1I		(1 << 3)
+#define	LPC_TIMER_MCR_MR1R		(1 << 4)
+#define	LPC_TIMER_MCR_MR1S		(1 << 5)
+#define	LPC_TIMER_MCR_MR2I		(1 << 6)
+#define	LPC_TIMER_MCR_MR2R		(1 << 7)
+#define	LPC_TIMER_MCR_MR2S		(1 << 8)
+#define	LPC_TIMER_MCR_MR3I		(1 << 9)
+#define	LPC_TIMER_MCR_MR3R		(1 << 10)
+#define	LPC_TIMER_MCR_MR3S		(1 << 11)
+#define	LPC_TIMER_MR0			0x18
+#define	LPC_TIMER_CTCR			0x70
+
+/*
+ * Watchdog timer. (from UM10326: LPC32x0 User manual, page 572)
+ */
+#define	LPC_WDTIM_PHYS_BASE		(LPC_DEV_PHYS_BASE + 0x3c000)
+#define	LPC_WDTIM_INT			0x00
+#define	LPC_WDTIM_CTRL			0x04
+#define	LPC_WDTIM_COUNTER		0x08
+#define	LPC_WDTIM_MCTRL			0x0c
+#define	LPC_WDTIM_MATCH0		0x10
+#define	LPC_WDTIM_EMR			0x14
+#define	LPC_WDTIM_PULSE			0x18
+#define	LPC_WDTIM_RES			0x1c
+#define	LPC_WDTIM_SIZE			0x20
+
+/*
+ * Clocking and power control. (from UM10326: LPC32x0 User manual, page 58)
+ */
+#define	LPC_CLKPWR_PHYS_BASE		(LPC_DEV_PHYS_BASE + 0x4000)
+#define	LPC_CLKPWR_PWR_CTRL		0x44
+#define	LPC_CLKPWR_OSC_CTRL		0x4c
+#define	LPC_CLKPWR_SYSCLK_CTRL		0x50
+#define	LPC_CLKPWR_PLL397_CTRL		0x48
+#define	LPC_CLKPWR_HCLKPLL_CTRL		0x58
+#define	LPC_CLKPWR_HCLKDIV_CTRL		0x40
+#define	LPC_CLKPWR_TEST_CTRL		0xa4
+#define	LPC_CLKPWR_AUTOCLK_CTRL		0xec
+#define	LPC_CLKPWR_START_ER_PIN		0x30
+#define	LPC_CLKPWR_START_ER_INT		0x20
+#define	LPC_CLKPWR_P0_INTR_ER		0x18
+#define	LPC_CLKPWR_START_SR_PIN		0x38
+#define	LPC_CLKPWR_START_SR_INT		0x28
+#define	LPC_CLKPWR_START_RSR_PIN	0x34
+#define	LPC_CLKPWR_START_RSR_INT	0x24
+#define	LPC_CLKPWR_START_APR_PIN	0x3c
+#define	LPC_CLKPWR_START_APR_INT	0x2c
+#define	LPC_CLKPWR_USB_CTRL		0x64
+#define	LPC_CLKPWR_USB_CTRL_SLAVE_HCLK	(1 << 24)
+#define	LPC_CLKPWR_USB_CTRL_I2C_EN	(1 << 23)
+#define	LPC_CLKPWR_USB_CTRL_DEV_NEED_CLK_EN	(1 << 22)
+#define	LPC_CLKPWR_USB_CTRL_HOST_NEED_CLK_EN	(1 << 21)
+#define	LPC_CLKPWR_USB_CTRL_BUSKEEPER	(1 << 19)
+#define	LPC_CLKPWR_USB_CTRL_CLK_EN2	(1 << 18)
+#define	LPC_CLKPWR_USB_CTRL_CLK_EN1	(1 << 17)
+#define	LPC_CLKPWR_USB_CTRL_PLL_PDOWN	(1 << 16)
+#define	LPC_CLKPWR_USB_CTRL_BYPASS	(1 << 15)
+#define	LPC_CLKPWR_USB_CTRL_DIRECT_OUT	(1 << 14)
+#define	LPC_CLKPWR_USB_CTRL_FEEDBACK	(1 << 13)
+#define	LPC_CLKPWR_USB_CTRL_POSTDIV(_x)	((_x & 0x3) << 11)
+#define	LPC_CLKPWR_USB_CTRL_PREDIV(_x)	((_x & 0x3) << 9)
+#define	LPC_CLKPWR_USB_CTRL_FDBKDIV(_x)	(((_x-1) & 0xff) << 1)
+#define	LPC_CLKPWR_USB_CTRL_PLL_LOCK	(1 << 0)
+#define	LPC_CLKPWR_USBDIV_CTRL		0x1c
+#define	LPC_CLKPWR_MS_CTRL		0x80
+#define	LPC_CLKPWR_MS_CTRL_DISABLE_SD	(1 << 10)
+#define	LPC_CLKPWR_MS_CTRL_CLOCK_EN	(1 << 9)
+#define	LPC_CLKPWR_MS_CTRL_MSSDIO23_PAD	(1 << 8)
+#define	LPC_CLKPWR_MS_CTRL_MSSDIO1_PAD	(1 << 7)
+#define	LPC_CLKPWR_MS_CTRL_MSSDIO0_PAD	(1 << 6)
+#define	LPC_CLKPWR_MS_CTRL_SD_CLOCK	(1 << 5)
+#define	LPC_CLKPWR_MS_CTRL_CLKDIV_MASK	0xf
+#define	LPC_CLKPWR_DMACLK_CTRL		0xe8
+#define	LPC_CLKPWR_DMACLK_CTRL_EN	(1 << 0)
+#define	LPC_CLKPWR_FLASHCLK_CTRL	0xc8
+#define	LPC_CLKPWR_MACCLK_CTRL		0x90
+#define	LPC_CLKPWR_MACCLK_CTRL_REG	(1 << 0)
+#define	LPC_CLKPWR_MACCLK_CTRL_SLAVE	(1 << 1)
+#define	LPC_CLKPWR_MACCLK_CTRL_MASTER	(1 << 2)
+#define	LPC_CLKPWR_MACCLK_CTRL_HDWINF(_n) ((_n & 0x3) << 3)
+#define	LPC_CLKPWR_LCDCLK_CTRL		0x54
+#define	LPC_CLKPWR_LCDCLK_CTRL_DISPTYPE	(1 << 8)
+#define	LPC_CLKPWR_LCDCLK_CTRL_MODE(_n)	((_n & 0x3) << 6)
+#define	LPC_CLKPWR_LCDCLK_CTRL_MODE_12	0x0
+#define	LPC_CLKPWR_LCDCLK_CTRL_MODE_15	0x1
+#define	LPC_CLKPWR_LCDCLK_CTRL_MODE_16	0x2
+#define	LPC_CLKPWR_LCDCLK_CTRL_MODE_24	0x3
+#define	LPC_CLKPWR_LCDCLK_CTRL_HCLKEN	(1 << 5)
+#define	LPC_CLKPWR_LCDCLK_CTRL_CLKDIV(_n) ((_n) & 0x1f)
+#define	LPC_CLKPWR_I2S_CTRL		0x7c
+#define	LPC_CLKPWR_SSP_CTRL		0x78
+#define	LPC_CLKPWR_SSP_CTRL_SSP1RXDMA	(1 << 5)
+#define	LPC_CLKPWR_SSP_CTRL_SSP1TXDMA	(1 << 4)
+#define	LPC_CLKPWR_SSP_CTRL_SSP0RXDMA	(1 << 3)
+#define	LPC_CLKPWR_SSP_CTRL_SSP0TXDMA	(1 << 2)
+#define	LPC_CLKPWR_SSP_CTRL_SSP1EN	(1 << 1)
+#define	LPC_CLKPWR_SSP_CTRL_SSP0EN	(1 << 0)
+#define	LPC_CLKPWR_SPI_CTRL		0xc4
+#define	LPC_CLKPWR_I2CCLK_CTRL		0xac
+#define	LPC_CLKPWR_TIMCLK_CTRL1		0xc0
+#define	LPC_CLKPWR_TIMCLK_CTRL1_TIMER4	(1 << 0)
+#define	LPC_CLKPWR_TIMCLK_CTRL1_TIMER5	(1 << 1)
+#define	LPC_CLKPWR_TIMCLK_CTRL1_TIMER0	(1 << 2)
+#define	LPC_CLKPWR_TIMCLK_CTRL1_TIMER1	(1 << 3)
+#define	LPC_CLKPWR_TIMCLK_CTRL1_TIMER2	(1 << 4)
+#define	LPC_CLKPWR_TIMCLK_CTRL1_TIMER3	(1 << 5)
+#define	LPC_CLKPWR_TIMCLK_CTRL1_MOTORCTL	(1 << 6)
+#define	LPC_CLKPWR_TIMCLK_CTRL		0xbc
+#define	LPC_CLKPWR_TIMCLK_CTRL_WATCHDOG	(1 << 0)
+#define	LPC_CLKPWR_TIMCLK_CTRL_HSTIMER	(1 << 1)
+#define	LPC_CLKPWR_ADCLK_CTRL		0xb4
+#define	LPC_CLKPWR_ADCLK_CTRL1		0x60
+#define	LPC_CLKPWR_KEYCLK_CTRL		0xb0
+#define	LPC_CLKPWR_PWMCLK_CTRL		0xb8
+#define	LPC_CLKPWR_UARTCLK_CTRL		0xe4
+#define	LPC_CLKPWR_POS0_IRAM_CTRL	0x110
+#define	LPC_CLKPWR_POS1_IRAM_CTRL	0x114
+#define	LPC_CLKPWR_SIZE			0x118
+
+/* Additional UART registers in CLKPWR address space. */
+#define	LPC_CLKPWR_UART_U3CLK		0xd0
+#define	LPC_CLKPWR_UART_U4CLK		0xd4
+#define	LPC_CLKPWR_UART_U5CLK		0xd8
+#define	LPC_CLKPWR_UART_U6CLK		0xdc
+#define	LPC_CLKPWR_UART_UCLK_HCLK	(1 << 16)
+#define	LPC_CLKPWR_UART_UCLK_X(_n)	(((_n) & 0xff) << 8)
+#define	LPC_CLKPWR_UART_UCLK_Y(_n)	((_n) & 0xff)
+#define	LPC_CLKPWR_UART_IRDACLK		0xe0
+
+/* Additional UART registers */
+#define	LPC_UART_BASE			0x80000
+#define	LPC_UART_CONTROL_BASE		0x54000
+#define	LPC_UART5_BASE			0x90000
+#define	LPC_UART_CTRL			0x00
+#define	LPC_UART_CLKMODE		0x04
+#define	LPC_UART_CLKMODE_UART3(_n)	(((_n) & 0x3) << 4)
+#define	LPC_UART_CLKMODE_UART4(_n)	(((_n) & 0x3) << 6)
+#define	LPC_UART_CLKMODE_UART5(_n)	(((_n) & 0x3) << 8)
+#define	LPC_UART_CLKMODE_UART6(_n)	(((_n) & 0x3) << 10)
+#define	LPC_UART_LOOP			0x08
+#define	LPC_UART_CONTROL_SIZE		0x0c
+#define	LPC_UART_FIFOSIZE		64
+
+/*
+ * Real time clock. (from UM10326: LPC32x0 User manual, page 566)
+ */
+#define	LPC_RTC_UCOUNT			0x00
+#define	LPC_RTC_DCOUNT			0x04
+#define	LPC_RTC_MATCH0			0x08
+#define	LPC_RTC_MATCH1			0x0c
+#define	LPC_RTC_CTRL			0x10
+#define	LPC_RTC_CTRL_ONSW		(1 << 7)
+#define	LPC_RTC_CTRL_DISABLE		(1 << 6)
+#define	LPC_RTC_CTRL_RTCRESET		(1 << 4)
+#define	LPC_RTC_CTRL_MATCH0ONSW		(1 << 3)
+#define	LPC_RTC_CTRL_MATCH1ONSW		(1 << 2)
+#define	LPC_RTC_CTRL_MATCH1INTR		(1 << 1)
+#define	LPC_RTC_CTRL_MATCH0INTR		(1 << 0)
+#define	LPC_RTC_INTSTAT			0x14
+#define	LPC_RTC_KEY			0x18
+#define	LPC_RTC_SRAM_BEGIN		0x80
+#define LPC_RTC_SRAM_END		0xff
+
+/*
+ * MMC/SD controller. (from UM10326: LPC32x0 User manual, page 436)
+ */
+#define	LPC_SD_PHYS_BASE		(LPC_DEV_P5_PHYS_BASE + 0x98000)
+#define	LPC_SD_CLK			(13 * 1000 * 1000)	// 13Mhz
+#define	LPC_SD_POWER			0x00
+#define	LPC_SD_POWER_OPENDRAIN		(1 << 6)
+#define	LPC_SD_POWER_CTRL_OFF		0x00
+#define	LPC_SD_POWER_CTRL_UP		0x02
+#define	LPC_SD_POWER_CTRL_ON		0x03
+#define	LPC_SD_CLOCK			0x04
+#define	LPC_SD_CLOCK_WIDEBUS		(1 << 11)
+#define	LPC_SD_CLOCK_BYPASS		(1 << 10)
+#define	LPC_SD_CLOCK_PWRSAVE		(1 << 9)
+#define	LPC_SD_CLOCK_ENABLE		(1 << 8)
+#define	LPC_SD_CLOCK_CLKDIVMASK		0xff
+#define	LPC_SD_ARGUMENT			0x08
+#define	LPC_SD_COMMAND			0x0c
+#define	LPC_SD_COMMAND_ENABLE		(1 << 10)
+#define	LPC_SD_COMMAND_PENDING		(1 << 9)
+#define	LPC_SD_COMMAND_INTERRUPT	(1 << 8)
+#define	LPC_SD_COMMAND_LONGRSP		(1 << 7)
+#define	LPC_SD_COMMAND_RESPONSE		(1 << 6)
+#define	LPC_SD_COMMAND_CMDINDEXMASK	0x3f
+#define	LPC_SD_RESPCMD			0x10
+#define	LPC_SD_RESP0			0x14
+#define	LPC_SD_RESP1			0x18
+#define	LPC_SD_RESP2			0x1c
+#define	LPC_SD_RESP3			0x20
+#define	LPC_SD_DATATIMER		0x24
+#define	LPC_SD_DATALENGTH		0x28
+#define	LPC_SD_DATACTRL			0x2c
+#define	LPC_SD_DATACTRL_BLOCKSIZESHIFT	4
+#define	LPC_SD_DATACTRL_BLOCKSIZEMASK	0xf
+#define	LPC_SD_DATACTRL_DMAENABLE	(1 << 3)
+#define	LPC_SD_DATACTRL_MODE		(1 << 2)
+#define	LPC_SD_DATACTRL_WRITE		(0 << 1)
+#define	LPC_SD_DATACTRL_READ		(1 << 1)
+#define	LPC_SD_DATACTRL_ENABLE		(1 << 0)
+#define	LPC_SD_DATACNT			0x30
+#define	LPC_SD_STATUS			0x34
+#define	LPC_SD_STATUS_RXDATAAVLBL	(1 << 21)
+#define	LPC_SD_STATUS_TXDATAAVLBL	(1 << 20)
+#define	LPC_SD_STATUS_RXFIFOEMPTY	(1 << 19)
+#define	LPC_SD_STATUS_TXFIFOEMPTY	(1 << 18)
+#define	LPC_SD_STATUS_RXFIFOFULL	(1 << 17)
+#define	LPC_SD_STATUS_TXFIFOFULL	(1 << 16)
+#define	LPC_SD_STATUS_RXFIFOHALFFULL	(1 << 15)
+#define	LPC_SD_STATUS_TXFIFOHALFEMPTY	(1 << 14)
+#define	LPC_SD_STATUS_RXACTIVE		(1 << 13)
+#define	LPC_SD_STATUS_TXACTIVE		(1 << 12)
+#define	LPC_SD_STATUS_CMDACTIVE		(1 << 11)
+#define	LPC_SD_STATUS_DATABLOCKEND	(1 << 10)
+#define	LPC_SD_STATUS_STARTBITERR	(1 << 9)
+#define	LPC_SD_STATUS_DATAEND		(1 << 8)
+#define	LPC_SD_STATUS_CMDSENT		(1 << 7)
+#define	LPC_SD_STATUS_CMDRESPEND	(1 << 6)
+#define	LPC_SD_STATUS_RXOVERRUN		(1 << 5)
+#define	LPC_SD_STATUS_TXUNDERRUN	(1 << 4)
+#define	LPC_SD_STATUS_DATATIMEOUT	(1 << 3)
+#define	LPC_SD_STATUS_CMDTIMEOUT	(1 << 2)
+#define	LPC_SD_STATUS_DATACRCFAIL	(1 << 1)
+#define	LPC_SD_STATUS_CMDCRCFAIL	(1 << 0)
+#define	LPC_SD_CLEAR			0x38
+#define	LPC_SD_MASK0			0x03c
+#define	LPC_SD_MASK1			0x40
+#define	LPC_SD_FIFOCNT			0x48
+#define	LPC_SD_FIFO			0x80
+
+/*
+ * USB OTG controller (from UM10326: LPC32x0 User manual, page 410)
+ */
+#define	LPC_OTG_INT_STATUS		0x100
+#define	LPC_OTG_INT_ENABLE		0x104
+#define	LPC_OTG_INT_SET			0x108
+#define	LPC_OTG_INT_CLEAR		0x10c
+#define	LPC_OTG_STATUS			0x110
+#define	LPC_OTG_STATUS_ATOB_HNP_TRACK	(1 << 9)
+#define	LPC_OTG_STATUS_BTOA_HNP_TACK	(1 << 8)
+#define	LPC_OTG_STATUS_TRANSP_I2C_EN	(1 << 7)
+#define	LPC_OTG_STATUS_TIMER_RESET	(1 << 6)
+#define	LPC_OTG_STATUS_TIMER_EN		(1 << 5)
+#define	LPC_OTG_STATUS_TIMER_MODE	(1 << 4)
+#define	LPC_OTG_STATUS_TIMER_SCALE	(1 << 2)
+#define	LPC_OTG_STATUS_HOST_EN		(1 << 0)
+#define	LPC_OTG_TIMER			0x114
+#define	LPC_OTG_I2C_TXRX		0x300
+#define	LPC_OTG_I2C_STATUS		0x304
+#define	LPC_OTG_I2C_STATUS_TFE		(1 << 11)
+#define	LPC_OTG_I2C_STATUS_TFF		(1 << 10)
+#define	LPC_OTG_I2C_STATUS_RFE		(1 << 9)
+#define	LPC_OTG_I2C_STATUS_RFF		(1 << 8)
+#define	LPC_OTG_I2C_STATUS_SDA		(1 << 7)
+#define	LPC_OTG_I2C_STATUS_SCL		(1 << 6)
+#define	LPC_OTG_I2C_STATUS_ACTIVE	(1 << 5)
+#define	LPC_OTG_I2C_STATUS_DRSI		(1 << 4)
+#define	LPC_OTG_I2C_STATUS_DRMI		(1 << 3)
+#define	LPC_OTG_I2C_STATUS_NAI		(1 << 2)
+#define	LPC_OTG_I2C_STATUS_AFI		(1 << 1)
+#define	LPC_OTG_I2C_STATUS_TDI		(1 << 0)
+#define	LPC_OTG_I2C_CTRL		0x308
+#define	LPC_OTG_I2C_CTRL_SRST		(1 << 8)
+#define	LPC_OTG_I2C_CTRL_TFFIE		(1 << 7)
+#define	LPC_OTG_I2C_CTRL_RFDAIE		(1 << 6)
+#define	LPC_OTG_I2C_CTRL_RFFIE		(1 << 5)
+#define	LPC_OTG_I2C_CTRL_DRSIE		(1 << 4)
+#define	LPC_OTG_I2C_CTRL_DRMIE		(1 << 3)
+#define	LPC_OTG_I2C_CTRL_NAIE		(1 << 2)
+#define	LPC_OTG_I2C_CTRL_AFIE		(1 << 1)
+#define	LPC_OTG_I2C_CTRL_TDIE		(1 << 0)
+#define	LPC_OTG_I2C_CLKHI		0x30c
+#define	LPC_OTG_I2C_CLKLO		0x310
+#define	LPC_OTG_CLOCK_CTRL		0xff4
+#define	LPC_OTG_CLOCK_CTRL_AHB_EN	(1 << 4)
+#define	LPC_OTG_CLOCK_CTRL_OTG_EN	(1 << 3)
+#define	LPC_OTG_CLOCK_CTRL_I2C_EN	(1 << 2)
+#define	LPC_OTG_CLOCK_CTRL_DEV_EN	(1 << 1)
+#define	LPC_OTG_CLOCK_CTRL_HOST_EN	(1 << 0)
+#define	LPC_OTG_CLOCK_STATUS		0xff8
+
+/*
+ * ISP3101 USB transceiver registers
+ */
+#define	LPC_ISP3101_I2C_ADDR		0x2d
+#define	LPC_ISP3101_MODE_CONTROL_1	0x04
+#define	LPC_ISP3101_MC1_SPEED_REG	(1 << 0)
+#define	LPC_ISP3101_MC1_SUSPEND_REG	(1 << 1)
+#define	LPC_ISP3101_MC1_DAT_SE0		(1 << 2)
+#define	LPC_ISP3101_MC1_TRANSPARENT	(1 << 3)
+#define	LPC_ISP3101_MC1_BDIS_ACON_EN	(1 << 4)
+#define	LPC_ISP3101_MC1_OE_INT_EN	(1 << 5)
+#define	LPC_ISP3101_MC1_UART_EN		(1 << 6)
+#define	LPC_ISP3101_MODE_CONTROL_2	0x12
+#define	LPC_ISP3101_MC2_GLOBAL_PWR_DN	(1 << 0)
+#define	LPC_ISP3101_MC2_SPD_SUSP_CTRL	(1 << 1)
+#define	LPC_ISP3101_MC2_BI_DI		(1 << 2)
+#define	LPC_ISP3101_MC2_TRANSP_BDIR0	(1 << 3)
+#define	LPC_ISP3101_MC2_TRANSP_BDIR1	(1 << 4)
+#define	LPC_ISP3101_MC2_AUDIO_EN	(1 << 5)
+#define	LPC_ISP3101_MC2_PSW_EN		(1 << 6)
+#define	LPC_ISP3101_MC2_EN2V7		(1 << 7)
+#define	LPC_ISP3101_OTG_CONTROL_1	0x06
+#define	LPC_ISP3101_OTG1_DP_PULLUP	(1 << 0)
+#define	LPC_ISP3101_OTG1_DM_PULLUP	(1 << 1)
+#define	LPC_ISP3101_OTG1_DP_PULLDOWN	(1 << 2)
+#define	LPC_ISP3101_OTG1_DM_PULLDOWN	(1 << 3)
+#define	LPC_ISP3101_OTG1_ID_PULLDOWN	(1 << 4)
+#define	LPC_ISP3101_OTG1_VBUS_DRV	(1 << 5)
+#define	LPC_ISP3101_OTG1_VBUS_DISCHRG	(1 << 6)
+#define	LPC_ISP3101_OTG1_VBUS_CHRG	(1 << 7)
+#define	LPC_ISP3101_OTG_CONTROL_2	0x10
+#define	LPC_ISP3101_OTG_INTR_LATCH	0x0a
+#define	LPC_ISP3101_OTG_INTR_FALLING	0x0c
+#define	LPC_ISP3101_OTG_INTR_RISING	0x0e
+#define	LPC_ISP3101_REG_CLEAR_ADDR	0x01
+
+/*
+ * LCD Controller (from UM10326: LPC32x0 User manual, page 229)
+ */
+#define	LPC_LCD_TIMH			0x00
+#define	LPC_LCD_TIMH_HBP(_n)		(((_n) & 0xff) << 24)
+#define	LPC_LCD_TIMH_HFP(_n)		(((_n) & 0xff) << 16)
+#define	LPC_LCD_TIMH_HSW(_n)		(((_n) & 0xff) << 8)
+#define	LPC_LCD_TIMH_PPL(_n)		(((_n) / 16 - 1) << 2)
+#define	LPC_LCD_TIMV			0x04
+#define	LPC_LCD_TIMV_VBP(_n)		(((_n) & 0xff) << 24)
+#define	LPC_LCD_TIMV_VFP(_n)		(((_n) & 0xff) << 16)
+#define	LPC_LCD_TIMV_VSW(_n)		(((_n) & 0x3f) << 10)
+#define	LPC_LCD_TIMV_LPP(_n)		((_n) & 0x1ff)
+#define	LPC_LCD_POL			0x08
+#define	LPC_LCD_POL_PCD_HI		(((_n) & 0x1f) << 27)
+#define	LPC_LCD_POL_BCD			(1 << 26)
+#define	LPC_LCD_POL_CPL(_n)		(((_n) & 0x3ff) << 16)
+#define	LPC_LCD_POL_IOE			(1 << 14)
+#define	LPC_LCD_POL_IPC			(1 << 13)
+#define	LPC_LCD_POL_IHS			(1 << 12)
+#define	LPC_LCD_POL_IVS			(1 << 11)
+#define	LPC_LCD_POL_ACB(_n)		((_n & 0x1f) << 6)
+#define	LPC_LCD_POL_CLKSEL		(1 << 5)
+#define	LPC_LCD_POL_PCD_LO(_n)		((_n) & 0x1f)
+#define	LPC_LCD_LE			0x0c
+#define	LPC_LCD_LE_LEE			(1 << 16)
+#define	LPC_LCD_LE_LED			((_n) & 0x7f)
+#define	LPC_LCD_UPBASE			0x10
+#define	LPC_LCD_LPBASE			0x14
+#define	LPC_LCD_CTRL			0x18
+#define	LPC_LCD_CTRL_WATERMARK		(1 << 16)
+#define	LPC_LCD_CTRL_LCDVCOMP(_n)	(((_n) & 0x3) << 12)
+#define	LPC_LCD_CTRL_LCDPWR		(1 << 11)
+#define	LPC_LCD_CTRL_BEPO		(1 << 10)
+#define	LPC_LCD_CTRL_BEBO		(1 << 9)
+#define	LPC_LCD_CTRL_BGR		(1 << 8)
+#define	LPC_LCD_CTRL_LCDDUAL		(1 << 7)
+#define	LPC_LCD_CTRL_LCDMONO8		(1 << 6)
+#define	LPC_LCD_CTRL_LCDTFT		(1 << 5)
+#define	LPC_LCD_CTRL_LCDBW		(1 << 4)
+#define	LPC_LCD_CTRL_LCDBPP(_n)		(((_n) & 0x7) << 1)
+#define	LPC_LCD_CTRL_BPP1		0
+#define	LPC_LCD_CTRL_BPP2		1
+#define	LPC_LCD_CTRL_BPP4		2
+#define	LPC_LCD_CTRL_BPP8		3
+#define	LPC_LCD_CTRL_BPP16		4
+#define	LPC_LCD_CTRL_BPP24		5
+#define	LPC_LCD_CTRL_BPP16_565		6
+#define	LPC_LCD_CTRL_BPP12_444		7
+#define	LPC_LCD_CTRL_LCDEN		(1 << 0)
+#define	LPC_LCD_INTMSK			0x1c
+#define	LPC_LCD_INTRAW			0x20
+#define	LPC_LCD_INTSTAT			0x24
+#define	LPC_LCD_INTCLR			0x28
+#define	LPC_LCD_UPCURR			0x2c
+#define	LPC_LCD_LPCURR			0x30
+#define	LPC_LCD_PAL			0x200
+#define	LPC_LCD_CRSR_IMG		0x800
+#define	LPC_LCD_CRSR_CTRL		0xc00
+#define	LPC_LCD_CRSR_CFG		0xc04
+#define	LPC_LCD_CRSR_PAL0		0xc08
+#define	LPC_LCD_CRSR_PAL1		0xc0c
+#define	LPC_LCD_CRSR_XY			0xc10
+#define	LPC_LCD_CRSR_CLIP		0xc14
+#define	LPC_LCD_CRSR_INTMSK		0xc20
+#define	LPC_LCD_CRSR_INTCLR		0xc24
+#define	LPC_LCD_CRSR_INTRAW		0xc28
+#define	LPC_LCD_CRSR_INTSTAT		0xc2c
+
+/*
+ * SPI interface (from UM10326: LPC32x0 User manual, page 483)
+ */
+#define	LPC_SPI_GLOBAL			0x00
+#define	LPC_SPI_GLOBAL_RST		(1 << 1)
+#define	LPC_SPI_GLOBAL_ENABLE		(1 << 0)
+#define	LPC_SPI_CON			0x04
+#define	LPC_SPI_CON_UNIDIR		(1 << 23)
+#define	LPC_SPI_CON_BHALT		(1 << 22)
+#define	LPC_SPI_CON_BPOL		(1 << 21)
+#define	LPC_SPI_CON_MSB			(1 << 19)
+#define	LPC_SPI_CON_MODE(_n)		((_n & 0x3) << 16)
+#define	LPC_SPI_CON_RXTX		(1 << 15)
+#define	LPC_SPI_CON_THR			(1 << 14)
+#define	LPC_SPI_CON_SHIFT_OFF		(1 << 13)
+#define	LPC_SPI_CON_BITNUM(_n)		((_n & 0xf) << 9)
+#define	LPC_SPI_CON_MS			(1 << 7)
+#define	LPC_SPI_CON_RATE(_n)		(_n & 0x7f)
+#define	LPC_SPI_FRM			0x08
+#define	LPC_SPI_IER			0x0c
+#define	LPC_SPI_IER_INTEOT		(1 << 1)
+#define	LPC_SPI_IER_INTTHR		(1 << 0)
+#define	LPC_SPI_STAT			0x10
+#define	LPC_SPI_STAT_INTCLR		(1 << 8)
+#define	LPC_SPI_STAT_EOT		(1 << 7)
+#define	LPC_SPI_STAT_BUSYLEV		(1 << 6)
+#define	LPC_SPI_STAT_SHIFTACT		(1 << 3)
+#define	LPC_SPI_STAT_BF			(1 << 2)
+#define	LPC_SPI_STAT_THR		(1 << 1)
+#define	LPC_SPI_STAT_BE			(1 << 0)
+#define	LPC_SPI_DAT			0x14
+#define	LPC_SPI_TIM_CTRL		0x400
+#define	LPC_SPI_TIM_COUNT		0x404
+#define	LPC_SPI_TIM_STAT		0x408
+
+/*
+ * SSP interface (from UM10326: LPC32x0 User manual, page 500)
+ */
+#define	LPC_SSP0_BASE			0x4c00
+#define	LPC_SSP1_BASE			0xc000
+#define	LPC_SSP_CR0			0x00
+#define	LPC_SSP_CR0_DSS(_n)		((_n-1) & 0xf)
+#define	LPC_SSP_CR0_TI			(1 << 4)
+#define	LPC_SSP_CR0_MICROWIRE		(1 << 5)
+#define	LPC_SSP_CR0_CPOL		(1 << 6)
+#define	LPC_SSP_CR0_CPHA		(1 << 7)
+#define	LPC_SSP_CR0_SCR(_n)		((_x & & 0xff) << 8)
+#define	LPC_SSP_CR1			0x04
+#define	LPC_SSP_CR1_LBM			(1 << 0)
+#define	LPC_SSP_CR1_SSE			(1 << 1)
+#define	LPC_SSP_CR1_MS			(1 << 2)
+#define	LPC_SSP_CR1_SOD			(1 << 3)
+#define	LPC_SSP_DR			0x08
+#define	LPC_SSP_SR			0x0c
+#define	LPC_SSP_SR_TFE			(1 << 0)
+#define	LPC_SSP_SR_TNF			(1 << 1)
+#define	LPC_SSP_SR_RNE			(1 << 2)
+#define	LPC_SSP_SR_RFF			(1 << 3)
+#define	LPC_SSP_SR_BSY			(1 << 4)
+#define	LPC_SSP_CPSR			0x10
+#define	LPC_SSP_IMSC			0x14
+#define	LPC_SSP_IMSC_RORIM		(1 << 0)
+#define	LPC_SSP_IMSC_RTIM		(1 << 1)
+#define	LPC_SSP_IMSC_RXIM		(1 << 2)
+#define	LPC_SSP_IMSC_TXIM		(1 << 3)
+#define	LPC_SSP_RIS			0x18
+#define	LPC_SSP_RIS_RORRIS		(1 << 0)
+#define	LPC_SSP_RIS_RTRIS		(1 << 1)
+#define	LPC_SSP_RIS_RXRIS		(1 << 2)
+#define	LPC_SSP_RIS_TXRIS		(1 << 3)
+#define	LPC_SSP_MIS			0x1c
+#define	LPC_SSP_ICR			0x20
+#define	LPC_SSP_DMACR			0x24
+
+/*
+ * GPIO (from UM10326: LPC32x0 User manual, page 606)
+ */
+#define	LPC_GPIO_PHYS_BASE		(LPC_DEV_PHYS_BASE + 0x28000)
+#define	LPC_GPIO_P0_COUNT		8
+#define	LPC_GPIO_P1_COUNT		24
+#define	LPC_GPIO_P2_COUNT		13
+#define	LPC_GPIO_P3_COUNT		52
+#define	LPC_GPIO_P0_INP_STATE		0x40
+#define	LPC_GPIO_P0_OUTP_SET		0x44
+#define	LPC_GPIO_P0_OUTP_CLR		0x48
+#define	LPC_GPIO_P0_OUTP_STATE		0x4c
+#define	LPC_GPIO_P0_DIR_SET		0x50
+#define	LPC_GPIO_P0_DIR_CLR		0x54
+#define	LPC_GPIO_P0_DIR_STATE		0x58
+#define	LPC_GPIO_P1_INP_STATE		0x60
+#define	LPC_GPIO_P1_OUTP_SET		0x64
+#define	LPC_GPIO_P1_OUTP_CLR		0x68
+#define	LPC_GPIO_P1_OUTP_STATE		0x6c
+#define	LPC_GPIO_P1_DIR_SET		0x70
+#define	LPC_GPIO_P1_DIR_CLR		0x74
+#define	LPC_GPIO_P1_DIR_STATE		0x78
+#define	LPC_GPIO_P2_INP_STATE		0x1c
+#define	LPC_GPIO_P2_OUTP_SET		0x20
+#define	LPC_GPIO_P2_OUTP_CLR		0x24
+#define	LPC_GPIO_P2_DIR_SET		0x10
+#define	LPC_GPIO_P2_DIR_CLR		0x14
+#define	LPC_GPIO_P2_DIR_STATE		0x14
+#define	LPC_GPIO_P3_INP_STATE		0x00
+#define	LPC_GPIO_P3_OUTP_SET		0x04
+#define	LPC_GPIO_P3_OUTP_CLR		0x08
+#define	LPC_GPIO_P3_OUTP_STATE		0x0c
+#define	LPC_GPIO_SIZE			0x80
+
+/* Aliases for logical pin numbers: */
+#define	LPC_GPIO_GPI_00(_n)		(0 + _n)
+#define	LPC_GPIO_GPI_15(_n)		(10 + _n)
+#define	LPC_GPIO_GPI_25			(19)
+#define	LPC_GPIO_GPI_27(_n)		(20 + _n)
+#define	LPC_GPIO_GPO_00(_n)		(22 + _n)
+#define	LPC_GPIO_GPIO_00(_n)		(46 + _n)
+/* SPI devices chip selects: */
+#define	SSD1289_CS_PIN			LPC_GPIO_GPO_00(4)
+#define	SSD1289_DC_PIN			LPC_GPIO_GPO_00(5)
+#define	ADS7846_CS_PIN			LPC_GPIO_GPO_00(11)
+#define	ADS7846_INTR_PIN		LPC_GPIO_GPIO_00(0)
+
+/*
+ * GPDMA controller (from UM10326: LPC32x0 User manual, page 106)
+ */
+#define	LPC_DMAC_INTSTAT		0x00
+#define	LPC_DMAC_INTTCSTAT		0x04
+#define	LPC_DMAC_INTTCCLEAR		0x08
+#define	LPC_DMAC_INTERRSTAT		0x0c
+#define	LPC_DMAC_INTERRCLEAR		0x10
+#define	LPC_DMAC_RAWINTTCSTAT		0x14
+#define	LPC_DMAC_RAWINTERRSTAT		0x18
+#define	LPC_DMAC_ENABLED_CHANNELS	0x1c
+#define	LPC_DMAC_SOFTBREQ		0x20
+#define	LPC_DMAC_SOFTSREQ		0x24
+#define	LPC_DMAC_SOFTLBREQ		0x28
+#define	LPC_DMAC_SOFTLSREQ		0x2c
+#define	LPC_DMAC_CONFIG			0x30
+#define	LPC_DMAC_CONFIG_M1		(1 << 2)
+#define	LPC_DMAC_CONFIG_M0		(1 << 1)
+#define	LPC_DMAC_CONFIG_ENABLE		(1 << 0)
+#define	LPC_DMAC_CHADDR(_n)		(0x100 + (_n * 0x20))
+#define	LPC_DMAC_CHNUM			8
+#define	LPC_DMAC_CHSIZE			0x20
+#define	LPC_DMAC_CH_SRCADDR		0x00
+#define	LPC_DMAC_CH_DSTADDR		0x04
+#define	LPC_DMAC_CH_LLI			0x08
+#define	LPC_DMAC_CH_LLI_AHB1		(1 << 0)
+#define	LPC_DMAC_CH_CONTROL		0x0c
+#define	LPC_DMAC_CH_CONTROL_I		(1U << 31)
+#define	LPC_DMAC_CH_CONTROL_DI		(1 << 27)
+#define	LPC_DMAC_CH_CONTROL_SI		(1 << 26)
+#define	LPC_DMAC_CH_CONTROL_D		(1 << 25)
+#define	LPC_DMAC_CH_CONTROL_S		(1 << 24)
+#define	LPC_DMAC_CH_CONTROL_WIDTH_4	2
+#define	LPC_DMAC_CH_CONTROL_DWIDTH(_n)	((_n & 0x7) << 21)
+#define	LPC_DMAC_CH_CONTROL_SWIDTH(_n)	((_n & 0x7) << 18)
+#define	LPC_DMAC_CH_CONTROL_BURST_8	2
+#define	LPC_DMAC_CH_CONTROL_DBSIZE(_n)	((_n & 0x7) << 15)
+#define	LPC_DMAC_CH_CONTROL_SBSIZE(_n)	((_n & 0x7) << 12)
+#define	LPC_DMAC_CH_CONTROL_XFERLEN(_n)	(_n & 0xfff) 
+#define	LPC_DMAC_CH_CONFIG		0x10
+#define	LPC_DMAC_CH_CONFIG_H		(1 << 18)
+#define	LPC_DMAC_CH_CONFIG_A		(1 << 17)
+#define	LPC_DMAC_CH_CONFIG_L		(1 << 16)
+#define	LPC_DMAC_CH_CONFIG_ITC		(1 << 15)
+#define	LPC_DMAC_CH_CONFIG_IE		(1 << 14)
+#define	LPC_DMAC_CH_CONFIG_FLOWCNTL(_n)	((_n & 0x7) << 11)
+#define	LPC_DMAC_CH_CONFIG_DESTP(_n)	((_n & 0x1f) << 6)
+#define	LPC_DMAC_CH_CONFIG_SRCP(_n)	((_n & 0x1f) << 1)
+#define	LPC_DMAC_CH_CONFIG_E		(1 << 0)
+
+/* DMA flow control values */
+#define	LPC_DMAC_FLOW_D_M2M		0
+#define	LPC_DMAC_FLOW_D_M2P		1
+#define	LPC_DMAC_FLOW_D_P2M		2
+#define	LPC_DMAC_FLOW_D_P2P		3
+#define	LPC_DMAC_FLOW_DP_P2P		4
+#define	LPC_DMAC_FLOW_P_M2P		5
+#define	LPC_DMAC_FLOW_P_P2M		6
+#define	LPC_DMAC_FLOW_SP_P2P		7
+
+/* DMA peripheral ID's */
+#define	LPC_DMAC_I2S0_DMA0_ID		0
+#define	LPC_DMAC_NAND_ID		1
+#define	LPC_DMAC_IS21_DMA0_ID		2
+#define	LPC_DMAC_SSP1_ID		3
+#define	LPC_DMAC_SPI2_ID		3
+#define	LPC_DMAC_SD_ID			4
+#define	LPC_DMAC_UART1_TX_ID		5
+#define	LPC_DMAC_UART1_RX_ID		6
+#define	LPC_DMAC_UART2_TX_ID		7
+#define	LPC_DMAC_UART2_RX_ID		8
+#define	LPC_DMAC_UART7_TX_ID		9
+#define	LPC_DMAC_UART7_RX_ID		10
+#define	LPC_DMAC_I2S1_DMA1_ID		10
+#define	LPC_DMAC_SPI1_ID		11
+#define	LPC_DMAC_SSP1_TX_ID		11
+#define	LPC_DMAC_NAND2_ID		12
+#define	LPC_DMAC_I2S0_DMA1_ID		13
+#define	LPC_DMAC_SSP0_RX		14
+#define	LPC_DMAC_SSP0_TX		15
+
+#endif	/* _ARM_LPC_LPCREG_H */
Index: freebsd/sys/arm/lpc/lpcvar.h
===================================================================
--- freebsd/sys/arm/lpc/lpcvar.h	(revision 803a4950f214d80f8f1ce3caf4ad0bf9956c27d9)
+++ freebsd/sys/arm/lpc/lpcvar.h	(revision 803a4950f214d80f8f1ce3caf4ad0bf9956c27d9)
@@ -0,0 +1,69 @@
+/*-
+ * Copyright (c) 2011 Jakub Wojciech Klama <jceel@FreeBSD.org>
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in the
+ *    documentation and/or other materials provided with the distribution.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
+ * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
+ * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
+ * SUCH DAMAGE.
+ *
+ * $FreeBSD$
+ */
+
+#ifndef	_ARM_LPC_LPCVAR_H
+#define	_ARM_LPC_LPCVAR_H
+
+#include <sys/types.h>
+#include <sys/bus.h>
+#include <machine/bus.h>
+
+/* Clocking and power control */
+uint32_t lpc_pwr_read(device_t, int);
+void lpc_pwr_write(device_t, int, uint32_t);
+
+/* GPIO */
+void lpc_gpio_init(void);
+int lpc_gpio_set_flags(device_t, int, int);
+int lpc_gpio_set_state(device_t, int, int);
+int lpc_gpio_get_state(device_t, int, int *);
+
+/* DMA */
+struct lpc_dmac_channel_config
+{
+	int		ldc_fcntl;
+	int		ldc_src_periph;
+	int		ldc_src_width;
+	int		ldc_src_incr;
+	int		ldc_src_burst;
+	int		ldc_dst_periph;
+	int		ldc_dst_width;
+	int		ldc_dst_incr;
+	int		ldc_dst_burst;
+	void		(*ldc_success_handler)(void *);
+	void		(*ldc_error_handler)(void *);
+	void *		ldc_handler_arg;
+};
+
+int lpc_dmac_config_channel(device_t, int, struct lpc_dmac_channel_config *);
+int lpc_dmac_setup_transfer(device_t, int, bus_addr_t, bus_addr_t, bus_size_t, int);
+int lpc_dmac_enable_channel(device_t, int);
+int lpc_dmac_disable_channel(device_t, int);
+int lpc_dmac_start_burst(device_t, int);
+
+#endif	/* _ARM_LPC_LPCVAR_H */
