Changeset 7e85bfbe in rtems

Timestamp:

Aug 24, 2011, 9:48:56 AM (10 years ago)

Author:

Sebastian Huber <sebastian.huber@…>

Branches:

4.11, 5, master

Children:

01750d5

Parents:

1d367a49

Message:

2011-08-24 Sebastian Huber <sebastian.huber@…>

• shared/bootloader/exception.S, shared/bootloader/misc.c, shared/bootloader/mm.c, shared/console/polled_io.c, shared/startup/probeMemEnd.c: Update due to API changes.

Location:

c/src/lib/libbsp/powerpc

Files:

• ChangeLog (modified) (1 diff)
• shared/bootloader/exception.S (modified) (5 diffs)
• shared/bootloader/misc.c (modified) (2 diffs)
• shared/bootloader/mm.c (modified) (2 diffs)
• shared/console/polled_io.c (modified) (1 diff)
• shared/startup/probeMemEnd.c (modified) (2 diffs)

c/src/lib/libbsp/powerpc/ChangeLog

@@ +1 @@
+2011-08-24      Sebastian Huber <sebastian.huber@embedded-brains.de>
+
+        * shared/bootloader/exception.S, shared/bootloader/misc.c,
+        shared/bootloader/mm.c, shared/console/polled_io.c,
+        shared/startup/probeMemEnd.c: Update due to API changes.
+
 2011-07-27  Till Straumann <strauman@slac.stanford.edu>
 

c/src/lib/libbsp/powerpc/shared/bootloader/exception.S

@@ -153 +153 @@
         andi.   r3,r1,8       # check for guarded memory
         bne-    5f
-        mtspr   RPA,r1
+        mtspr   PPC_RPA,r1
         mfsrr1  r3
         tlbli   r0
@@ -169 +169 @@
         mfsrr1  r3            # get saved cr0 bits now to dual issue
         ori     r1,r1,0x100
-        mtspr   RPA,r1
+        mtspr   PPC_RPA,r1
         tlbli   r0
 /* Do not update PTE if R bit already set, this will save one cache line
@@ -249 +249 @@
         mfspr   r0,DMISS      # get miss address during load delay
 #ifdef ASSUME_REF_SET
-        mtspr   RPA,r1
+        mtspr   PPC_RPA,r1
         mfsrr1  r3
         tlbld   r0
@@ -256 +256 @@
         mfsrr1  r3            # get saved cr0 bits now to dual issue
         ori     r1,r1,0x100
-        mtspr   RPA,r1
+        mtspr   PPC_RPA,r1
         tlbld   r0
 /* Do not update PTE if R bit already set, this will save one cache line
@@ -327 +327 @@
         beq-    5f            # if (C==0) go to check protection
 3:      mfsrr1  r3            # get the saved cr0 bits
-        mtspr   RPA,r1        # set the pte
+        mtspr   PPC_RPA,r1        # set the pte
         tlbld   r0            # load the dtlb
         mtcrf   0x80,r3       # restore CR0

c/src/lib/libbsp/powerpc/shared/bootloader/misc.c

@@ -27 +27 @@
 #include <bsp.h>
 
-SPR_RW(DEC)
-SPR_RO(PVR)
+SPR_RO(PPC_PVR)
 
 struct inode;
@@ -265 +264 @@
 
 #define vpd res->VitalProductData
-        if (_read_PVR()>>16 != 1) {
+        if (_read_PPC_PVR()>>16 != 1) {
                 if ( res && vpd.ProcessorBusHz ) {
                         ticks_per_ms = vpd.ProcessorBusHz/

c/src/lib/libbsp/powerpc/shared/bootloader/mm.c

@@ -96 +96 @@
 SPR_RW(SDR1);
 SPR_RO(DSISR);
-SPR_RO(DAR);
+SPR_RO(PPC_DAR);
 
 /* We need a few statically allocated free maps to bootstrap the
@@ -141 +141 @@
                 cause = p->msr;
         } else { /* Valid for DSI and alignment exceptions */
-                vaddr = _read_DAR();
+                vaddr = _read_PPC_DAR();
                 cause = _read_DSISR();
         }

c/src/lib/libbsp/powerpc/shared/console/polled_io.c

@@ -374 +374 @@
 #define KBD_MODE_RFU            0x80
 
-SPR_RW(DEC)
-SPR_RO(PVR)
-
 #endif /* USE_KBD_SUPPORT */
 

c/src/lib/libbsp/powerpc/shared/startup/probeMemEnd.c

@@ -111 +111 @@
 SPR_RW(L2CR)
 SPR_RW(L3CR)
-SPR_RO(PVR)
+SPR_RO(PPC_PVR)
 SPR_RW(HID0)
 
@@ -128 +128 @@
         }
         asm volatile("sync");
-        switch ( _read_PVR()>>16 ) {
-                default:                printk(__FILE__" CPU_lockUnlockCaches(): unknown CPU (PVR = 0x%08x)\n",_read_PVR());
+        switch ( _read_PPC_PVR()>>16 ) {
+                default:                printk(__FILE__" CPU_lockUnlockCaches(): unknown CPU (PVR = 0x%08x)\n",_read_PPC_PVR());
                                                 return -1;
                 case PPC_750:   printk("CPU_lockUnlockCaches(): Can't lock L2 on a mpc750, sorry :-(\n");