Changeset 7e85bfbe in rtems


Ignore:
Timestamp:
Aug 24, 2011, 9:48:56 AM (10 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, 5, master
Children:
01750d5
Parents:
1d367a49
Message:

2011-08-24 Sebastian Huber <sebastian.huber@…>

  • shared/bootloader/exception.S, shared/bootloader/misc.c, shared/bootloader/mm.c, shared/console/polled_io.c, shared/startup/probeMemEnd.c: Update due to API changes.
Location:
c/src/lib/libbsp/powerpc
Files:
6 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/powerpc/ChangeLog

    r1d367a49 r7e85bfbe  
     12011-08-24      Sebastian Huber <sebastian.huber@embedded-brains.de>
     2
     3        * shared/bootloader/exception.S, shared/bootloader/misc.c,
     4        shared/bootloader/mm.c, shared/console/polled_io.c,
     5        shared/startup/probeMemEnd.c: Update due to API changes.
     6
    172011-07-27  Till Straumann <strauman@slac.stanford.edu>
    28
  • c/src/lib/libbsp/powerpc/shared/bootloader/exception.S

    r1d367a49 r7e85bfbe  
    153153        andi.   r3,r1,8       # check for guarded memory
    154154        bne-    5f
    155         mtspr   RPA,r1
     155        mtspr   PPC_RPA,r1
    156156        mfsrr1  r3
    157157        tlbli   r0
     
    169169        mfsrr1  r3            # get saved cr0 bits now to dual issue
    170170        ori     r1,r1,0x100
    171         mtspr   RPA,r1
     171        mtspr   PPC_RPA,r1
    172172        tlbli   r0
    173173/* Do not update PTE if R bit already set, this will save one cache line
     
    249249        mfspr   r0,DMISS      # get miss address during load delay
    250250#ifdef ASSUME_REF_SET
    251         mtspr   RPA,r1
     251        mtspr   PPC_RPA,r1
    252252        mfsrr1  r3
    253253        tlbld   r0
     
    256256        mfsrr1  r3            # get saved cr0 bits now to dual issue
    257257        ori     r1,r1,0x100
    258         mtspr   RPA,r1
     258        mtspr   PPC_RPA,r1
    259259        tlbld   r0
    260260/* Do not update PTE if R bit already set, this will save one cache line
     
    327327        beq-    5f            # if (C==0) go to check protection
    3283283:      mfsrr1  r3            # get the saved cr0 bits
    329         mtspr   RPA,r1        # set the pte
     329        mtspr   PPC_RPA,r1        # set the pte
    330330        tlbld   r0            # load the dtlb
    331331        mtcrf   0x80,r3       # restore CR0
  • c/src/lib/libbsp/powerpc/shared/bootloader/misc.c

    r1d367a49 r7e85bfbe  
    2727#include <bsp.h>
    2828
    29 SPR_RW(DEC)
    30 SPR_RO(PVR)
     29SPR_RO(PPC_PVR)
    3130
    3231struct inode;
     
    265264
    266265#define vpd res->VitalProductData
    267         if (_read_PVR()>>16 != 1) {
     266        if (_read_PPC_PVR()>>16 != 1) {
    268267                if ( res && vpd.ProcessorBusHz ) {
    269268                        ticks_per_ms = vpd.ProcessorBusHz/
  • c/src/lib/libbsp/powerpc/shared/bootloader/mm.c

    r1d367a49 r7e85bfbe  
    9696SPR_RW(SDR1);
    9797SPR_RO(DSISR);
    98 SPR_RO(DAR);
     98SPR_RO(PPC_DAR);
    9999
    100100/* We need a few statically allocated free maps to bootstrap the
     
    141141                cause = p->msr;
    142142        } else { /* Valid for DSI and alignment exceptions */
    143                 vaddr = _read_DAR();
     143                vaddr = _read_PPC_DAR();
    144144                cause = _read_DSISR();
    145145        }
  • c/src/lib/libbsp/powerpc/shared/console/polled_io.c

    r1d367a49 r7e85bfbe  
    374374#define KBD_MODE_RFU            0x80
    375375
    376 SPR_RW(DEC)
    377 SPR_RO(PVR)
    378 
    379376#endif /* USE_KBD_SUPPORT */
    380377
  • c/src/lib/libbsp/powerpc/shared/startup/probeMemEnd.c

    r1d367a49 r7e85bfbe  
    111111SPR_RW(L2CR)
    112112SPR_RW(L3CR)
    113 SPR_RO(PVR)
     113SPR_RO(PPC_PVR)
    114114SPR_RW(HID0)
    115115
     
    128128        }
    129129        asm volatile("sync");
    130         switch ( _read_PVR()>>16 ) {
    131                 default:                printk(__FILE__" CPU_lockUnlockCaches(): unknown CPU (PVR = 0x%08x)\n",_read_PVR());
     130        switch ( _read_PPC_PVR()>>16 ) {
     131                default:                printk(__FILE__" CPU_lockUnlockCaches(): unknown CPU (PVR = 0x%08x)\n",_read_PPC_PVR());
    132132                                                return -1;
    133133                case PPC_750:   printk("CPU_lockUnlockCaches(): Can't lock L2 on a mpc750, sorry :-(\n");
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