Changeset 7e85bfbe in rtems
- Timestamp:
- Aug 24, 2011, 9:48:56 AM (10 years ago)
- Branches:
- 4.11, 5, master
- Children:
- 01750d5
- Parents:
- 1d367a49
- Location:
- c/src/lib/libbsp/powerpc
- Files:
-
- 6 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/lib/libbsp/powerpc/ChangeLog
r1d367a49 r7e85bfbe 1 2011-08-24 Sebastian Huber <sebastian.huber@embedded-brains.de> 2 3 * shared/bootloader/exception.S, shared/bootloader/misc.c, 4 shared/bootloader/mm.c, shared/console/polled_io.c, 5 shared/startup/probeMemEnd.c: Update due to API changes. 6 1 7 2011-07-27 Till Straumann <strauman@slac.stanford.edu> 2 8 -
c/src/lib/libbsp/powerpc/shared/bootloader/exception.S
r1d367a49 r7e85bfbe 153 153 andi. r3,r1,8 # check for guarded memory 154 154 bne- 5f 155 mtspr RPA,r1155 mtspr PPC_RPA,r1 156 156 mfsrr1 r3 157 157 tlbli r0 … … 169 169 mfsrr1 r3 # get saved cr0 bits now to dual issue 170 170 ori r1,r1,0x100 171 mtspr RPA,r1171 mtspr PPC_RPA,r1 172 172 tlbli r0 173 173 /* Do not update PTE if R bit already set, this will save one cache line … … 249 249 mfspr r0,DMISS # get miss address during load delay 250 250 #ifdef ASSUME_REF_SET 251 mtspr RPA,r1251 mtspr PPC_RPA,r1 252 252 mfsrr1 r3 253 253 tlbld r0 … … 256 256 mfsrr1 r3 # get saved cr0 bits now to dual issue 257 257 ori r1,r1,0x100 258 mtspr RPA,r1258 mtspr PPC_RPA,r1 259 259 tlbld r0 260 260 /* Do not update PTE if R bit already set, this will save one cache line … … 327 327 beq- 5f # if (C==0) go to check protection 328 328 3: mfsrr1 r3 # get the saved cr0 bits 329 mtspr RPA,r1 # set the pte329 mtspr PPC_RPA,r1 # set the pte 330 330 tlbld r0 # load the dtlb 331 331 mtcrf 0x80,r3 # restore CR0 -
c/src/lib/libbsp/powerpc/shared/bootloader/misc.c
r1d367a49 r7e85bfbe 27 27 #include <bsp.h> 28 28 29 SPR_RW(DEC) 30 SPR_RO(PVR) 29 SPR_RO(PPC_PVR) 31 30 32 31 struct inode; … … 265 264 266 265 #define vpd res->VitalProductData 267 if (_read_P VR()>>16 != 1) {266 if (_read_PPC_PVR()>>16 != 1) { 268 267 if ( res && vpd.ProcessorBusHz ) { 269 268 ticks_per_ms = vpd.ProcessorBusHz/ -
c/src/lib/libbsp/powerpc/shared/bootloader/mm.c
r1d367a49 r7e85bfbe 96 96 SPR_RW(SDR1); 97 97 SPR_RO(DSISR); 98 SPR_RO( DAR);98 SPR_RO(PPC_DAR); 99 99 100 100 /* We need a few statically allocated free maps to bootstrap the … … 141 141 cause = p->msr; 142 142 } else { /* Valid for DSI and alignment exceptions */ 143 vaddr = _read_ DAR();143 vaddr = _read_PPC_DAR(); 144 144 cause = _read_DSISR(); 145 145 } -
c/src/lib/libbsp/powerpc/shared/console/polled_io.c
r1d367a49 r7e85bfbe 374 374 #define KBD_MODE_RFU 0x80 375 375 376 SPR_RW(DEC)377 SPR_RO(PVR)378 379 376 #endif /* USE_KBD_SUPPORT */ 380 377 -
c/src/lib/libbsp/powerpc/shared/startup/probeMemEnd.c
r1d367a49 r7e85bfbe 111 111 SPR_RW(L2CR) 112 112 SPR_RW(L3CR) 113 SPR_RO(P VR)113 SPR_RO(PPC_PVR) 114 114 SPR_RW(HID0) 115 115 … … 128 128 } 129 129 asm volatile("sync"); 130 switch ( _read_P VR()>>16 ) {131 default: printk(__FILE__" CPU_lockUnlockCaches(): unknown CPU (PVR = 0x%08x)\n",_read_P VR());130 switch ( _read_PPC_PVR()>>16 ) { 131 default: printk(__FILE__" CPU_lockUnlockCaches(): unknown CPU (PVR = 0x%08x)\n",_read_PPC_PVR()); 132 132 return -1; 133 133 case PPC_750: printk("CPU_lockUnlockCaches(): Can't lock L2 on a mpc750, sorry :-(\n");
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