Changeset 7de58239 in rtems


Ignore:
Timestamp:
02/01/02 16:45:18 (22 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
8e3caa5
Parents:
2835b3a5
Message:

2001-02-01 Greg Menke <gregory.menke@…>

  • Update of BSP to address problems restarting, provide more information during boot, and better handle ROM vs RAM images.
  • README, include/bsp.h, start/regs.S, start/start.S, startup/bspstart.c, startup/linkcmds, timer/timer.c: Updated
Location:
c/src/lib/libbsp/mips/genmongoosev
Files:
8 edited

Legend:

Unmodified
Added
Removed

  • c/src/lib/libbsp/mips/genmongoosev/ChangeLog

    r2835b3a5 r7de58239  
     12001-02-01      Greg Menke <gregory.menke@gsfc.nasa.gov>
     2
     3        * Update of BSP to address problems restarting, provide more
     4        information during boot, and better handle ROM vs RAM images.
     5        * README, include/bsp.h, start/regs.S, start/start.S,
     6        startup/bspstart.c, startup/linkcmds, timer/timer.c: Updated
     7
    182002-02-07      Ralf Corsepius <corsepiu@faw.uni-ulm.de>
    29

  • c/src/lib/libbsp/mips/genmongoosev/README

    r2835b3a5 r7de58239  
    3939===========
    4040
    41 At startup, PMON looks for a <space> to be pressed.  If it is pressed,
    42 then a PMON prompt is displayed.  Otherwise, PMON automatically jumps
    43 to the code at 0xBFC4_0000.  This code may be a boot manager or
    44 simply a collection of noop's that fall into the code at
    45 0xBFC5_0000.  If the code at 0xBFC4_0000 is a boot manager, then it
    46 can determine which program image to load.  This layout allows for the
    47 possible compression of program images.  Given that there is much
    48 more RAM than EEPROM, compression could be desirable for certain
    49 applications.
     41On the breadboard, a locally hacked PMON waits for a space to be pressed
     42while the board is reset/powered up.  If found, the PMON console is
     43entered, else PMON jumps to the EEPROM address above, presuming a user
     44program is located there.
     45
     46The default output of an RTEMS link is an image linked to run from
     4780020000, but has had its LMA shifted up to BFC40000.  It is suitable
     48for copying to S3 records or can be burned to ROMs in whatever manner
     49the user desires.
     50
     51Operation
     52=========
     53
     54A small relocator is supplied in the bsp startup code which copies the
     55image down to RAM for execution before doing any other initialization.
     56This locator code is location independent, and will do nothing if the
     57image is already located at its run location.  The LMA and VMA are both
     58controlled via the bsp's link script.  The above behavior is produced by
     59using the default script.  If this is not desirable, something like the
     60following may be added to the user's RTEMS link statement to override
     61the default linkcmds with a user-supplied version;
     62
     63-qnolinkcmds -Wl,-T -Wl,mips-rtems-linkcmds-eprom
     64
     65this causes the file ./mips-rtems-linkcmds-eprom to override the default
     66linkcmds.
     67
     68Before relocating the RTEMS image, the bsp startup routine attempts to
     69configure the processor into a rational state.  During this process,
     70status characters are emitted at 19200N81 baud on UART port 0.
     71
    5072
    5173Questions
    5274=========
    5375
    54 +  XXX
    55  
     76Why can I send characters slowly to a Mongoose V, but get framing errors
     77when sending them fast?
     78
     79- The MongooseV chip seems to <require> that all incoming data have 2
     80  stop bits.  When typing on a serial terminal, this is not an issue
     81  because the idle state of an RS232 line looks just like a stop bit-
     82  but when streaming in data, such pacing is required.  The manual does
     83  not indicate anything along these lines, instead, we suspect a
     84  somewhat faulty UART design.
     85
     86
    5687Status
    5788======
    5889
    59 + untested
    60 
    61 + no mkeeprom script
    62 
    63 + start code must copy from EEPROM to RAM and then run.
    64 
    65 + XXX

  • c/src/lib/libbsp/mips/genmongoosev/include/bsp.h

    r2835b3a5 r7de58239  
    130130void bsp_cleanup( void );
    131131
    132 rtems_isr_entry set_vector(
    133   rtems_isr_entry, rtems_vector_number, int );
    134 
     132rtems_isr_entry set_vector( rtems_isr_entry, rtems_vector_number, int );
     133   
    135134#ifdef __cplusplus
    136135}
    … …  
    138137
    139138#endif
     139
    140140/* end of include file */

  • c/src/lib/libbsp/mips/genmongoosev/start/regs.S

    r2835b3a5 r7de58239  
    1717
    1818/* Standard MIPS register names: */
    19 #define zero    $0
    20 #define z0      $0
    21 #define v0      $2
    22 #define v1      $3
    23 #define a0      $4
    24 #define a1      $5
    25 #define a2      $6
    26 #define a3      $7
    27 #define t0      $8
    28 #define t1      $9
    29 #define t2      $10
    30 #define t3      $11
    31 #define t4      $12
    32 #define t5      $13
    33 #define t6      $14
    34 #define t7      $15
    35 #define s0      $16
    36 #define s1      $17
    37 #define s2      $18
    38 #define s3      $19
    39 #define s4      $20
    40 #define s5      $21
    41 #define s6      $22
    42 #define s7      $23
    43 #define t8      $24
    44 #define t9      $25
    45 #define k0      $26     /* kernel private register 0 */
    46 #define k1      $27     /* kernel private register 1 */
    47 #define gp      $28     /* global data pointer */
    48 #define sp      $29     /* stack-pointer */
    49 #define fp      $30     /* frame-pointer */
    50 #define ra      $31     /* return address */
    51 #define pc      $pc     /* pc, used on mips16 */
     19#define zero    $0
     20#define z0  $0
     21#define v0  $2
     22#define v1  $3
     23#define a0  $4
     24#define a1  $5
     25#define a2  $6
     26#define a3  $7
     27#define t0  $8
     28#define t1  $9
     29#define t2  $10
     30#define t3  $11
     31#define t4  $12
     32#define t5  $13
     33#define t6  $14
     34#define t7  $15
     35#define s0  $16
     36#define s1  $17
     37#define s2  $18
     38#define s3  $19
     39#define s4  $20
     40#define s5  $21
     41#define s6  $22
     42#define s7  $23
     43#define t8  $24
     44#define t9  $25
     45#define k0  $26 /* kernel private register 0 */
     46#define k1  $27 /* kernel private register 1 */
     47#define gp  $28 /* global data pointer */
     48#define sp  $29 /* stack-pointer */
     49#define fp  $30 /* frame-pointer */
     50#define ra  $31 /* return address */
     51#define pc  $pc /* pc, used on mips16 */
    5252
    53 #define fp0     $f0
    54 #define fp1     $f1
     53#define fp0 $f0
     54#define fp1 $f1
    5555
    56 #define WATCHDOG        0xBE000000
     56#define WATCHDOG    0xBE000000
    5757
    5858/* Useful memory constants: */
    59 #define K0BASE          0x80000000
     59#define K0BASE      0x80000000
    6060#ifndef __mips64
    61 #define K1BASE          0xA0000000
     61   #define K1BASE       0xA0000000
    6262#else
    63 #define K1BASE          0xFFFFFFFFA0000000LL
     63#define K1BASE      0xFFFFFFFFA0000000LL
    6464#endif
    6565
    6666#define PHYS_TO_K1(a)   ((unsigned)(a) | K1BASE)
    6767
    68 /* Standard Co-Processor 0 register numbers:
    69 #define C0_COUNT        $9              /* Count Register */
    70 #define C0_SR           $12             /* Status Register */
    71 #define C0_CAUSE        $13             /* last exception description */
    72 #define C0_EPC          $14             /* Exception error address */
    73 #define C0_CONFIG       $16             /* CPU configuration */
     68/* Standard Co-Processor 0 register numbers: */
     69#define C0_DCIC     $7      /* debug & cache invalidate control */
     70#define C0_COUNT    $9      /* Count Register */
     71#define C0_SR           $12         /* Status Register */
     72#define C0_CAUSE    $13     /* last exception description */
     73#define C0_EPC      $14         /* Exception error address */
     74#define C0_CONFIG   $16     /* CPU configuration */
    7475
    7576/* Standard Status Register bitmasks: */
    76 #define SR_CU1          0x20000000      /* Mark CP1 as usable */
    77 #define SR_FR           0x04000000      /* Enable MIPS III FP registers */
    78 #define SR_BEV          0x00400000      /* Controls location of exception vectors */
    79 #define SR_PE           0x00100000      /* Mark soft reset (clear parity error) */
     77#define SR_CU0          0x10000000
     78#define SR_CU1      0x20000000  /* Mark CP1 as usable */
     79#define SR_FR       0x04000000  /* Enable MIPS III FP registers */
     80#define SR_BEV      0x00400000  /* Controls location of exception vectors */
     81#define SR_PE       0x00100000  /* Mark soft reset (clear parity error) */
    8082
    81 #define SR_KX           0x00000080      /* Kernel extended addressing enabled */
    82 #define SR_SX           0x00000040      /* Supervisor extended addressing enabled */
    83 #define SR_UX           0x00000020      /* User extended addressing enabled */
     83/* defined differently for Mongoose5- we don't use these anymore */
     84//#define SR_KX     0x00000080  /* Kernel extended addressing enabled */
     85//#define SR_SX     0x00000040  /* Supervisor extended addressing enabled */
     86//#define SR_UX     0x00000020  /* User extended addressing enabled */
     87
     88/* R3000 */
     89#define SR_ISC      0x00010000  /* Isolate data cache */
    8490
    8591/* Standard (R4000) cache operations. Taken from "MIPS R4000
    8692   Microprocessor User's Manual" 2nd edition: */
    8793
    88 #define CACHE_I         (0)     /* primary instruction */
    89 #define CACHE_D         (1)     /* primary data */
    90 #define CACHE_SI        (2)     /* secondary instruction */
    91 #define CACHE_SD        (3)     /* secondary data (or combined instruction/data) */
     94#define CACHE_I     (0) /* primary instruction */
     95#define CACHE_D     (1) /* primary data */
     96#define CACHE_SI    (2) /* secondary instruction */
     97#define CACHE_SD    (3) /* secondary data (or combined instruction/data) */
    9298
    93 #define INDEX_INVALIDATE                (0)     /* also encodes WRITEBACK if CACHE_D or CACHE_SD */
    94 #define INDEX_LOAD_TAG                  (1)
    95 #define INDEX_STORE_TAG                 (2)
    96 #define CREATE_DIRTY_EXCLUSIVE          (3)     /* CACHE_D and CACHE_SD only */
    97 #define HIT_INVALIDATE                  (4)
    98 #define CACHE_FILL                      (5)     /* CACHE_I only */
    99 #define HIT_WRITEBACK_INVALIDATE        (5)     /* CACHE_D and CACHE_SD only */
    100 #define HIT_WRITEBACK                   (6)     /* CACHE_I, CACHE_D and CACHE_SD only */
    101 #define HIT_SET_VIRTUAL                 (7)     /* CACHE_SI and CACHE_SD only */
     99#define INDEX_INVALIDATE        (0) /* also encodes WRITEBACK if CACHE_D or CACHE_SD */
     100#define INDEX_LOAD_TAG          (1)
     101#define INDEX_STORE_TAG         (2)
     102#define CREATE_DIRTY_EXCLUSIVE      (3) /* CACHE_D and CACHE_SD only */
     103#define HIT_INVALIDATE          (4)
     104#define CACHE_FILL          (5) /* CACHE_I only */
     105#define HIT_WRITEBACK_INVALIDATE    (5) /* CACHE_D and CACHE_SD only */
     106#define HIT_WRITEBACK           (6) /* CACHE_I, CACHE_D and CACHE_SD only */
     107#define HIT_SET_VIRTUAL         (7) /* CACHE_SI and CACHE_SD only */
    102108
    103 #define BUILD_CACHE_OP(o,c)             (((o) << 2) | (c))
     109#define BUILD_CACHE_OP(o,c)     (((o) << 2) | (c))
    104110
    105111/* Individual cache operations: */
    106 #define INDEX_INVALIDATE_I              BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
    107 #define INDEX_WRITEBACK_INVALIDATE_D    BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
     112#define INDEX_INVALIDATE_I      BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_I)
     113#define INDEX_WRITEBACK_INVALIDATE_D    BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_D)
    108114#define INDEX_INVALIDATE_SI             BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SI)
    109 #define INDEX_WRITEBACK_INVALIDATE_SD   BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
     115#define INDEX_WRITEBACK_INVALIDATE_SD   BUILD_CACHE_OP(INDEX_INVALIDATE,CACHE_SD)
    110116
    111 #define INDEX_LOAD_TAG_I                BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
     117#define INDEX_LOAD_TAG_I        BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_I)
    112118#define INDEX_LOAD_TAG_D                BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_D)
    113119#define INDEX_LOAD_TAG_SI               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SI)
    114120#define INDEX_LOAD_TAG_SD               BUILD_CACHE_OP(INDEX_LOAD_TAG,CACHE_SD)
    115121
    116 #define INDEX_STORE_TAG_I               BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
     122#define INDEX_STORE_TAG_I               BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_I)
    117123#define INDEX_STORE_TAG_D               BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_D)
    118124#define INDEX_STORE_TAG_SI              BUILD_CACHE_OP(INDEX_STORE_TAG,CACHE_SI)
    … …  
    135141#define HIT_WRITEBACK_SD                BUILD_CACHE_OP(HIT_WRITEBACK,CACHE_SD)
    136142
    137 #define HIT_SET_VIRTUAL_SI              BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
     143#define HIT_SET_VIRTUAL_SI      BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SI)
    138144#define HIT_SET_VIRTUAL_SD              BUILD_CACHE_OP(HIT_SET_VIRTUAL,CACHE_SD)
    139145

  • c/src/lib/libbsp/mips/genmongoosev/start/start.S

    r2835b3a5 r7de58239  
    11/*
    2  * start.S -- startup file for JMR3904 BSP based upon crt0.S from
    3  * newlib-1.8.2/libgloss/mips and adapted for RTEMS.
    4  *
    5  * crt0.S -- startup file for MIPS.
    6  *
    7  * Copyright (c) 1995, 1996, 1997 Cygnus Support
    8  *
    9  * The authors hereby grant permission to use, copy, modify, distribute,
    10  * and license this software and its documentation for any purpose, provided
    11  * that existing copyright notices are retained in all copies and that this
    12  * notice is included verbatim in any distributions. No written agreement,
    13  * license, or royalty fee is required for any of the authorized uses.
    14  * Modifications to this software may be copyrighted by their authors
    15  * and need not follow the licensing terms described here, provided that
    16  * the new terms are clearly indicated on the first page of each file where
    17  * they apply.
    18  */
    19 
    20 
    21 
    22 #define PMON_UTIL_ROUTINES      0xbfc00200
    23 #define UTIL_WARMSTART_VECTOR   21*4
    24 #define UTIL_CPUINIT_VECTOR     22*4
    25 #define UTIL_CONFIGUART_VECTOR  23*4
    26 #define UTIL_PUTCHROM_VECTOR    24*4
    27        
    28        
     2** start.S -- startup file for Mongoose V BSP based upon crt0.S from
     3** newlib-1.8.2/libgloss/mips and adapted for RTEMS.
     4**
     5** crt0.S -- startup file for MIPS.
     6**
     7** Copyright (c) 1995, 1996, 1997 Cygnus Support
     8**
     9** The authors hereby grant permission to use, copy, modify, distribute,
     10** and license this software and its documentation for any purpose, provided
     11** that existing copyright notices are retained in all copies and that this
     12** notice is included verbatim in any distributions. No written agreement,
     13** license, or royalty fee is required for any of the authorized uses.
     14** Modifications to this software may be copyrighted by their authors
     15** and need not follow the licensing terms described here, provided that
     16** the new terms are clearly indicated on the first page of each file where
     17** they apply.
     18**
     19**
     20** Modification History:
     21**        01/XX/01  Joel Sherrill, OAR Corp,
     22**           Modified for Mongoose V BSP for NASA/GSFC Code 582.
     23**
     24**        06/XX/01  Greg Menke, Raytheon, Code 582
     25**           Debug modifications. Removed R4000 dependencies.
     26**           Added HACKED_PMON defines to facilitate startup.
     27**           Added DEFAULT_EXIT_RETURN_TO_MONITOR option.
     28**
     29**        11/14/01  A.Ferrer, NASA/GSFC, Code 582
     30**           Cleanup for ST5 mission.
     31**
     32**        11/27/01  A.Ferrer, NASA/GSFC, Code 582
     33**           Added cache flush routines.
     34*/
     35
     36#define LANGUAGE_ASSEMBLY
     37
     38
    2939#include <asm.h>
    3040#include "regs.S"
    31 
     41#include "mg5.h"
     42
     43
     44       
    3245#ifdef __mips16
    33 /* This file contains 32 bit assembly code.  */
    34         .set nomips16
     46   /* This file contains 32 bit assembly code.  */
     47   .set nomips16
    3548#endif
    3649
    37 /* This is for referencing addresses that are not in the .sdata or
    38    .sbss section under embedded-pic, or before we've set up gp.  */
    39 #ifdef __mips_embedded_pic
    40 # ifdef __mips64
    41 #  define LA(t,x) la t,x-PICBASE ; daddu t,s0,t
    42 # else
    43 #  define LA(t,x) la t,x-PICBASE ; addu t,s0,t
    44 # endif
    45 #else /* __mips_embedded_pic */
    46 # define LA(t,x) la t,x
    47 #endif /* __mips_embedded_pic */
    48 
    49 
    50 /* defined by linkcmds, pointing to the start of the relocation target
    51    memory, referenced in this way so we can avoid defining it
    52    multiply */
    53                
    54 
    55        
    56         .text
    57         .align  2
    58 
    59 /* Without the following nop, GDB thinks _start is a data variable.
    60  * This is probably a bug in GDB in handling a symbol that is at the
    61  * start of the .text section.
    62  */
    63         nop
    64 
    65         .globl  _start
    66         .ent    _start
     50
     51#ifdef HACKED_PMON
     52   #define PMON_UTIL_ROUTINES      0xbfc00200
     53   #define UTIL_WARMSTART_VECTOR   21*4
     54   #define UTIL_CPUINIT_VECTOR     22*4
     55   #define UTIL_CONFIGUART_VECTOR  23*4
     56   #define UTIL_PUTCHROM_VECTOR    24*4
     57#endif
     58
     59
     60/*
     61** defined by linkcmds, pointing to the start of the relocation target
     62** memory, referenced in this way so we can avoid defining it
     63** multiply
     64*/
     65   .bss
     66   .word 0
     67   .text
     68   .align 2
     69
     70
     71/**********************************************************************
     72**
     73** Function: _start
     74*/
     75
     76   /* Without the following nop, GDB thinks _start is a data variable.
     77   ** This is probably a bug in GDB in handling a symbol that is at the
     78   ** start of the .text section.
     79   */
     80    nop
     81   .globl  _start
     82   .ent    _start
     83
     84   .globl putch_rom
    6785_start:
    68         .set    noreorder
    69         # Get the address of start into $5 in a position independent fashion.
    70         # This lets us know whether we have been relocated or not.
    71        
    72         $LF1 = . + 8
    73         bal     $LF1
    74         nop
    75        
     86   .set    noreorder
     87   move    k1,ra       /* save ra so we can optionally return to caller */
     88   $LF1 = . + 8
     89
     90   /*
     91   ** Get the address of start into $5 in a position independent fashion.
     92   ** This lets us know whether we have been relocated or not.
     93   */
     94
     95   bal     $LF1
     96   nop
    7697_branch:
    77         move    a1, ra                          /* save return address from the jump above */
    78 
    79         /* call down into PMON's CpuInit, so we avoid having to
    80         duplicate all that code plus remember to update both copies
    81         when something changes... Note, a1 must be preserved by
    82         CpuInit */
    83        
    84         li      t7,PMON_UTIL_ROUTINES           /* get base address of pmon's vector table */
    85         lw      t0,UTIL_CPUINIT_VECTOR(t7)
    86         nop
    87         jal     t0              /* init cpu */
    88         nop
    89 
    90         lw      t0,UTIL_CONFIGUART_VECTOR(t7)
    91         nop
    92         jal     t0              /* reconfigure UART for console output */
    93         nop
    94        
    95         lw      t0,UTIL_PUTCHROM_VECTOR(t7)
    96         li      a0,'b'          /* show we booted */
    97         jal     t0
    98 
    99 
    100        
    101         /*
    102            get the address of the _branch label above as it would appear in
    103            the relocated code
    104         */
    105         la      a2, _branch                     /* relocation destination */
    106        
    107         beq     a1, a2, _start_in_ram           /* skip relocating if we're already there */
    108         nop
    109        
    110         /* relocate the code from EEPROM to RAM */
    111 
    112         lw      t0,UTIL_PUTCHROM_VECTOR(t7)
    113         li      a0,'r'          /* show we're starting relocation */
    114         jal     t0
    115        
    116         la      a3, _edata
     98   move    a1, ra      /* save return address from the jump above */
     99
     100   /* ensure we're sane before doing anything */
     101
     102   li      t0, SR_CU0|SR_PE
     103   mtc0    t0, C0_SR
     104   nop
     105   li      t0, 0
     106   mtc0    t0, C0_DCIC
     107   nop
     108   mtc0    t0, C0_CAUSE
     109   nop
     110
     111
     112   /*
     113   ** Call cpuinit. Masking used to call EEPROM address of _cpuinit.  Label is RAM label.
     114   */
     115   move   t2,a1
     116   and    t2,0xffff0000
     117   la     t0,_cpuinit
     118   and    t0,0x0000ffff
     119   or     t0,t2
     120   jal    t0
     121   nop
     122
     123   /*
     124   ** Configure UART
     125   */
     126   move   t2,a1
     127   and    t2,0xffff0000
     128   la     t0,config_uart
     129   and    t0,0x0000ffff
     130   or     t0,t2
     131   jal    t0
     132   nop
     133
     134   /*
     135   ** Call IcacheFlush. Masking used to call EEPROM address of IcacheFlush.  Label is RAM label.
     136   */
     137   move   t2,a1
     138   and    t2,0xffff0000
     139   la     t0,IcacheFlush
     140   and    t0,0x0000ffff
     141   or     t0,t2
     142   jal    t0
     143   nop
     144
     145
     146   /*
     147   ** Print 'I'.  Show that we flushed I cache.
     148   */
     149   move   t2,a1
     150   and    t2,0xffff0000
     151   li     a0,'I'
     152   la     t0,putch_rom
     153   and    t0,0x0000ffff
     154   or     t0,t2
     155   jal    t0
     156   nop
     157
     158
     159   /*
     160   ** Call DcacheFlush. Masking used to call EEPROM address of DcacheFlush.  Label is RAM label.
     161   */
     162   move   t2,a1
     163   and    t2,0xffff0000
     164   la     t0,DcacheFlush
     165   and    t0,0x0000ffff
     166   or     t0,t2
     167   jal    t0
     168   nop
     169
     170
     171   /*
     172   ** Print 'D'.  Show that we flushed D cache.
     173   */
     174   move   t2,a1
     175   and    t2,0xffff0000
     176   li     a0,'D'
     177   la     t0,putch_rom
     178   and    t0,0x0000ffff
     179   or     t0,t2
     180   jal    t0
     181   nop
     182
     183
     184   /*
     185   ** Print ' RTEMS  b'.  Show that we are booting.
     186   */
     187   move   t2,a1
     188   and    t2,0xffff0000
     189   li     a0,' '
     190   la     t0,putch_rom
     191   and    t0,0x0000ffff
     192   or     t0,t2
     193   jal    t0
     194   nop
     195
     196   move   t2,a1
     197   and    t2,0xffff0000
     198   li     a0,'R'
     199   la     t0,putch_rom
     200   and    t0,0x0000ffff
     201   or     t0,t2
     202   jal    t0
     203   nop
     204
     205   move   t2,a1
     206   and    t2,0xffff0000
     207   li     a0,'T'
     208   la     t0,putch_rom
     209   and    t0,0x0000ffff
     210   or     t0,t2
     211   jal    t0
     212   nop
     213
     214   move   t2,a1
     215   and    t2,0xffff0000
     216   li     a0,'E'
     217   la     t0,putch_rom
     218   and    t0,0x0000ffff
     219   or     t0,t2
     220   jal    t0
     221   nop
     222
     223   move   t2,a1
     224   and    t2,0xffff0000
     225   li     a0,'M'
     226   la     t0,putch_rom
     227   and    t0,0x0000ffff
     228   or     t0,t2
     229   jal    t0
     230   nop
     231
     232   move   t2,a1
     233   and    t2,0xffff0000
     234   li     a0,'S'
     235   la     t0,putch_rom
     236   and    t0,0x0000ffff
     237   or     t0,t2
     238   jal    t0
     239   nop
     240
     241   move   t2,a1
     242   and    t2,0xffff0000
     243   li     a0,' '
     244   la     t0,putch_rom
     245   and    t0,0x0000ffff
     246   or     t0,t2
     247   jal    t0
     248   nop
     249
     250   move   t2,a1
     251   and    t2,0xffff0000
     252   li     a0,'b'
     253   la     t0,putch_rom
     254   and    t0,0x0000ffff
     255   or     t0,t2
     256   jal    t0
     257   nop
     258
     259
     260   /*
     261   ** get the address of the _branch label above as it would appear in
     262   ** the relocated code
     263   */
     264
     265   la  a2, _branch                 /* relocation destination */
     266   beq a1, a2, _start_in_ram       /* skip relocating if we're already there */
     267   nop
     268
     269   /* relocate the code from EEPROM to RAM */
     270
     271   /*
     272   ** Print 'r'
     273   */
     274   move   t2,a1
     275   and    t2,0xffff0000
     276   li     a0,'r'
     277   la     t0,putch_rom
     278   and    t0,0x0000ffff
     279   or     t0,t2
     280   jal    t0
     281   nop
     282
     283   la  a3, _edata
    117284relocate:
    118         lw      t0, (a1)                        /* load from EEPROM */
    119         addu    a1, 4
    120         sw      t0, (a2)                        /* store to RAM */
    121         addu    a2, 4
    122         bne     a2, a3, relocate                /* copied all the way to edata? */
    123         nop
    124 
    125         lw      t0,UTIL_PUTCHROM_VECTOR(t7)
    126         li      a0,'R'          /* show we relocated */
    127         jal     t0
    128         nop
    129 
    130         la      a2, _start_in_ram
    131         jr      a2
    132         nop
    133         .end _start
    134 
    135 
    136 
    137 
    138 
    139        
    140         .globl  _start_in_ram
    141         .ent _start_in_ram
     285   lw  t0, (a1)            /* load from EEPROM */
     286   addu    a1, 4
     287   sw      t0, (a2)        /* store to RAM */
     288   addu    a2, 4
     289   bne a2, a3, relocate    /* copied all the way to edata? */
     290   nop
     291
     292   /*
     293   ** Print 'R'
     294   */
     295   li     a0,'R'
     296   la     t0,putch_rom
     297   and    t0,0x0000ffff
     298   or     t0,t2
     299   jal    t0
     300   nop
     301
     302   la  a2, _start_in_ram
     303   jr  a2
     304   nop
     305   .end _start
     306
     307
     308/**********************************************************************
     309**
     310** Function: _start_in_ram
     311*/
     312
     313   .globl  _start_in_ram
     314   .ent _start_in_ram
    142315_start_in_ram:
    143         lw      t0,UTIL_PUTCHROM_VECTOR(t7)
    144         li      a0,'S'          /* show we're starting in the target address range */
    145         jal     t0
    146         nop
    147 
    148 #ifdef __mips_embedded_pic
    149         PICBASE = .+8
    150         bal     PICBASE
    151         nop
    152         move    s0,$31
    153 #endif
    154 
    155         li      v0, SR_CU1|SR_PE|SR_FR|SR_KX|SR_SX|SR_UX
    156         mtc0    v0, C0_SR
    157         mtc0    zero, C0_CAUSE
    158 
    159 /* Check for FPU presence */
    160 #ifndef __mips_soft_float
    161 /* This doesn't work if there is no FPU.  We get illegal instruction
    162    exceptions.  */
    163         li      t2,0xAAAA5555
    164         mtc1    t2,fp0          /* write to FPR 0 */
    165         mtc1    zero,fp1        /* write to FPR 1 */
    166         mfc1    t0,fp0
    167         mfc1    t1,fp1
    168         nop
    169         bne     t0,t2,1f        /* check for match */
    170         nop
    171         bne     t1,zero,1f      /* double check */
    172         nop
    173 #ifndef __mips64  /* Clear the FR bit */
    174         li      v0, SR_CU1|SR_PE|SR_KX|SR_SX|SR_UX
    175         mtc0    v0, C0_SR
    176 #endif
    177         j       2f
    178         nop
    179 #endif
     316
     317   /*
     318   ** Print 'S'.  Already in RAM no need to reference EEPROM address.
     319   */
     320   li a0,'S'
     321   jal putch_rom
     322   nop
     323
     324   la  gp, _gp         /* set the global data pointer */
     325   .end _start_in_ram
     326
     327
     328/**********************************************************************
     329**
     330** Function: zerobss
     331*/
     332   .globl  __memsize
     333   .globl  zerobss
     334   .ent    zerobss
     335zerobss:
     336
     337   /*
     338   ** Print 'z'.  Starting to zero out bss.
     339   */
     340   li a0,'z'
     341   jal putch_rom
     342   nop
     343
     344   la v0, _fbss
     345   la v1, _end
     3463:
     347   sw zero,0(v0)
     348   bltu v0,v1,3b
     349   addiu v0,v0,4               /* executed in delay slot */
     350
     351   la  t0, _stack_init         /* initialize stack so we */
     352
     353   /*
     354   ** We must subtract 24 bytes for the 3 8 byte arguments to main, in
     355   ** case main wants to write them back to the stack.  The caller is
     356   ** supposed to allocate stack space for parameters in registers in
     357   ** the old MIPS ABIs.  We must do this even though we aren't passing
     358   ** arguments, because main might be declared to have them.
     359   **
     360   ** Some ports need a larger alignment for the stack, so we subtract
     361   ** 32, which satisifes the stack for the arguments and keeps the
     362   ** stack pointer better aligned.
     363   */
     364   subu    t0,t0,32
     365   move    sp,t0               /* set stack pointer */
     366   nop
     367
     368   /*
     369   ** Print 'Z'.  Finished zeroing bss.
     370   */
     371   li a0,'Z'
     372   jal putch_rom
     373   nop
     374
     375   .end    zerobss
     376
     377
     378/**********************************************************************
     379**
     380** Function: _init
     381*/
     382   .globl  exit .text
     383   .globl  _init
     384   .ent    _init
     385_init:
     386
     387   /*
     388   ** Print 'i'.  Starting to initialize RTEMS.
     389   */
     390   li a0, 'i'
     391   jal putch_rom
     392   nop
     393
     394   move    a0,zero         /* set argc to 0 */
     395   jal boot_card           /* call the program start function */
     396   nop
     397
     398   /*
     399   ** fall through to the "exit" routine
     400   */
     401   jal _sys_exit
     402   nop
     403   .end _init
     404
     405
     406/**********************************************************************
     407**
     408** Function: _sys_exit
     409**
     410** Exit from the application by jumping to PMON address in EEPROM.
     411*/
     412   .globl  _sys_exit
     413   .ent _sys_exit
     414_sys_exit:
     415   la  t0, PMON_ADDRESS
     416   jal t0
     417   .end _sys_exit
     418
     419
     420
     421/**********************************************************************
     422**
     423** function: putch
     424** input   : ASCII character in A0
     425** registers used: ra, a0, t0, t1
     426**
     427*/
     428   .globl putch_rom
     429   .ent   putch_rom
     430putch_rom:
     431
     432   /*
     433   ** Delay for UART
     434   */
     435   li   t0, 1000
     436   move t1, zero
     4372:
     438   beq  t0, t1, 3f
     439   addu t1, 1
     440   b    2b
     441   nop
     442
     4433:
     444   /*
     445   ** Print a character out from a0
     446   */
     447
     448   li   t0, MG5_INT_STATUS_REG      /* load uart register base address */
     449   lw   t1, 0(t0)                   /* Read status */
     450   nop
     451   and  t1, t1, UART_0_TX_READY_BIT /* see if the transmitter is ready */
     452   beq  t1 , zero , 1f              /* skip uart output if not ready */
     453   nop
     454   la   t0, MG5_UART_0_TX_REG
     455   sw   a0, 0(t0)
     456   nop
     457
     4581: /*
     459   ** if jumped to here, UART was not ready...forget it
     460   */
     461   j    ra
     462  .end putch_rom
     463
     464
     465/**********************************************************************
     466**
     467** function: config_uart
     468** registers used: ra, t0, t1
     469**
     470*/
     471
     472   .globl config_uart
     473   .ent   config_uart
     474config_uart:
     475
     476   /*
     477   **  Configure UART 0
     478   */
     479
     480   /* First, reset the uart */
     481   la   t0, MG5_COMMAND_REG
     482   li   t1, UART_RESET_BIT
     483   sw   t1, 0(t0)
     484
     485   /* Next, set the baud rate register for 19200 with a clock speed of 12 Mhz*/
     486   la   t0, MG5_UART_0_BAUD_REG
     487   li   t1, 0x02700270
     488   sw   t1, 0(t0)
     489
     490   /* Now, clear the reset bit & set the tx enable bit */
     491   la   t0, MG5_COMMAND_REG
     492   li   t1, UART_0_TX_ENABLE_BIT
     493   sw   t1, 0(t0)
     494
     495   /*
     496   ** return
     497   */
     498   j    ra
     499.end config_uart
     500
     501
     502/*************************************************************
     503* CpuInit:
     504*   Perform CPU-specific initialization
     505*   This routine is only callable from assembly because it
     506*   clobbers s7. It should be called from your ROM-based startup
     507*   code. It returns:
     508*       s0 = address of cache flush routine
     509*/
     510
     511   .globl  _cpuinit
     512   .ent _cpuinit
     513_cpuinit:
     514
     515   #
     516   # BIU/Cache config register setup
     517   #
     518   # RES    = 0: 31 -> 18 : Reserved
     519   # RES    = 1: 17       : Reserved must be set to 1 (Synova Manual)
     520   # RES    = 0: 16       : Reserved must be set to 0 (Synova Manual)
     521   # BGNT   = 0: 15       : Disable Bus Grant (set to 0)
     522   # NOPAD  = 1: 14       : No padding of waitstates between transactions
     523   # RDPRI  = 1: 13       : Loads have priority over stores
     524   # INTP   = 1: 12       : Interrupts are active high
     525   # IS1    = 1: 11       : Enable I-Cache
     526   # IS0    = 0: 10       : Hardwired to zero
     527   # IBLKSZ =10:  9 ->  8 : I-Cache refill size = 8 words
     528   # DS     = 1:  7       : Enable D-Cache
     529   # RES    = 0:  6       : Hardwared to zero
     530   # DBLKSZ =10:  5 ->  4 : D-Cache refill block size 8 words
     531   # RAM    = 0:  3       : No Scratchpad RAM
     532   # TAG    = 0:  2       : Disable tag test
     533   # INV    = 0:  1       : Disable invalidate mode
     534   # LOCK   = 0:  0       : Disable cache lock
     535   #
     536   li  t0,0x00027AA0
     537   sw  t0,M_BIU
     538
     539   #
     540   # Refresh register setup
     541   #
     542   # set 94 clock cycles at 12Mhz
     543   #
     544   li  t1,M_RTIC
     545   li  t0,0x5E
     546   sw  t0,(t1)
     547
     548   #
     549   # DRAM register setup
     550   #
     551   #
     552   # RESERVED=0: 31 -> 29 : Reserved
     553   # SYNC  = 0 : 27       : No Syncronous DRAM
     554   # SCFG  = 0 : 26       : No Syncronous DRAM
     555   # DMARDY =1 : 25       : Internal DRDY for DMA
     556   # DMABLK =0 : 24 -> 22 : 2 word blk size for DMA transfers
     557   # DPTH = 0  : 21 -> 20 : No interleaved or syncronous memory
     558   # RDYW = 0  : 19       : No interleaved or syncronous memory
     559   # PGSZ = 110: 18 -> 16 : Page size = 1K
     560   # PGMW = 0  : 15       : Disable page mode write
     561   # RFWE = 0  : 14 -> 13 : Allow BIU to do non-DRAM work during refresh
     562   # RFEN = 1  : 12       : Enable Refresh generator
     563   # RDYEN = 1 : 11       : Internal DRDY
     564   # BFD =   1 : 10       : Block fetch disable
     565   # PE =    0 : 9        : No parity checking
     566   # RPC =   0 : 8 -> 7   : RAS Precharge = 2 SYSCLK cycles
     567   # RCD =   1 : 6 -> 5   : RAS-to-CAS delay = 3 cycles
     568   # CS  =   0 : 4        : CAS shortened by 1/2 cycle
     569   # CL  =   1 : 3 -> 1   : 2.5 cycle CAS pulse width
     570   # DCE =   1 : 0        : Enable DRAM controller
     571   li  s0,0x02061C23
     572   sw  s0,M_DRAM
     573
     574   #
     575   # SRAM setup
     576   # Dont Care about this, we are not using SRAM
     577   # Power on default of 0x0 is ok
     578   #
     579   li  t0,0
     580   sw  t0,M_SRAM
     581
     582   #
     583   # SPEC0 setup
     584   #
     585   # SPEC0 contains the BCRT registers, BCRT Shared RAM and EEPROM
     586   # This area is configured to use an external waitstate generator
     587   # and Data Ready signal.
     588   # Also, I see no need to cache this data. It could confuse the
     589   # BCRT.
     590   #
     591   # - 9/29/99 - APC - set NOSNOOP to 1 and EXTGNT to 1
     592   #  Bit 23 = 1 : EXTGNT External data ready = 1
     593   #  Bit 19 = 1 : NOSNOOP No Snoop = 1
     594   li  t0,0x00880000         # use external waitstates
     595   sw  t0,M_SPEC0
     596
     597   #
     598   # SPEC1 setup
     599   #
     600   # This is where most of the SDB I/O is.
     601   #
     602   #  Important fields:
     603   #
     604   #  Bit 19 =1 : NOSNOOP = 1
     605   #  Bit 6 = 1 : Enable DAWG
     606   #  Bit 5 -> 0  = 1 : 1 Wait state
     607   #
     608   li  t0,0x00880000      /* Bit23 EXTGNT set to 1, Bit19 NOSNOOP set to 1 */
     609   sw  t0,M_SPEC1
     610
     611   #
     612   # SPEC2 setup
     613   #
     614   # SPEC2 is not currently used on the SDB.
     615   # Bit 19 = 1 : NOSNOOP = 1
     616   #
     617   #li t0, 0x00080000
     618   #sw t0,M_SPEC2
     619   #
     620   li  t0, 0x0
     621   sw  t0,M_SPEC2
     622
     623
     624   #
     625   # SPEC3 Setup
     626   # SPEC3 will be used for the SONIC ethernet controller.
     627   # Use the same # of waitstates that the turborocket board uses.
     628   # Bit 19 = 1 : NOSNOOP = 1
     629   #
     630   #li t0, (SPC_CACHED | SPC_WAITENA | (16<<SPC_WAITSHFT))
     631   #sw t0,M_SPEC3
     632   #
     633   li  t0, 0x0
     634   sw  t0,M_SPEC3
     635
     636   #
     637   # Finally, delay to allow RAM to stabilize
     638   #
     639   li  t0,2000
     6401: subu    t0,1
     641   bne t0,zero,1b
     642   nop
     643
     644   #
     645   # Init Mongoose V registers.
     646   #
     647
     648   /*
     649   ** Mongoose V Control Register Setup
     650   ** For now just setup UART defaults, turn edac off.
     651   ** May not even need to put anything in here...
     652   */
     653   li  t0,0
     654   sw  t0,MG5_COMMAND_REG
     655
     656   /*
     657   ** Setup Mongoose V extended interrupt mask
     658   */
     659   li  t0,0
     660   sw  t0,MG5_INT_MASK_REG
     661
     662   /*
     663   ** Clear Mongoose V extended interrupts
     664   ** Clear all of the pulse interrupts that may be pending.
     665   */
     666   li  t0,( EDAC_SERR_BIT | EDAC_MERR_BIT | UART_0_RX_OVERRUN_BIT | UART_0_FRAME_ERR_BIT | UART_1_RX_OVERRUN_BIT | UART_1_FRAME_ERR_BIT | MAVN_WRITE_ACC_BIT | MAVN_READ_ACC_BIT )
     667   sw  t0,MG5_INT_STATUS_REG
     668
     669   /*
     670   ** Setup MAVN Access Priv Register
     671   */
     672   li  t0,0x7FFFFFFF  /* Default reset value */
     673   sw  t0,MG5_MAVN_PRIVLEGE_REG
     674
     675   /*
     676   ** Mavn Range Register 0 -- 0 and 1 cover EEPROM
     677   ** 0xbfc00000 -> 0xbfe00000
     678   */
     679   li  t0,( 0xBFC00000 | 0x15 )
     680   sw  t0,MG5_MAVN_RANGE_0_REG
     681
     682   /*
     683   ** Mavn Range Register 1
     684   ** 0xbfe00000 -> 0xc0000000
     685   */
     686   li  t0,( 0xBFE00000 | 0x15 )
     687   sw  t0,MG5_MAVN_RANGE_1_REG
     688
     689   /*
     690   ** Mavn Range Register 2 -- 2 and 3 cover the first RAM
     691   ** 0x80000000 -> 0x80200000
     692   */
     693   li  t0,( 0x80000000 | 0x15 )
     694   sw  t0,MG5_MAVN_RANGE_2_REG
     695
     696   /*
     697   ** Mavn Range Register 3
     698   ** 0x80200000 -> 0x80400000
     699   */
     700   li  t0, ( 0x80200000 | 0x15 )
     701   sw  t0, MG5_MAVN_RANGE_3_REG
     702
     703   /*
     704   ** Mavn Range Register 4 -- IO Space 1
     705   ** 0xBE00000 -> 0xBe0000200
     706   */
     707   li  t0, ( 0xBe000000 | 0x09 )
     708   sw  t0, MG5_MAVN_RANGE_4_REG
     709
     710   /*
     711   ** Mavn Range Register 5 -- IO Space 2
     712   ** 0xBe200000 -> 0xbe400000
     713   */
     714   li  t0, ( 0xBE200000 | 0x15 )
     715   sw  t0, MG5_MAVN_RANGE_5_REG
     716
     717   /*
     718   ** MAVN Error Address Register ( Unstick )
     719   */
     720   la      t0, MG5_MAVN_VIOLATION_REG
     721   lw      t1, 0(t0)
     722
     723   /*
     724   ** Read EDAC Error Register to unstick it
     725   */
     726   la      t0, MG5_EDAC_ADDR_REG
     727   lw      t1, 0(t0)
     728
     729   /*
     730   ** Enable Mongoose V EDAC
     731   */
     732   la      t0, MG5_COMMAND_REG
     733   li      t1, EDAC_ENABLE_BIT
     734   sw      t1, 0(t0)
     735   nop
     736
     737   /*
     738   ** Program Watchdog to 10 seconds - If PMON will
     739   ** run, it will be set to MAX later.
     740   */
     741   la      t0, 0xBE000000
     742   li      t1, 0xA0
     743   sw      t1, 0(t0)
     744
     7453: nop
     746
     747   j ra
     748   .end _cpuinit
     749
     750
     751/*******************************************************************************
     752** Function Name:   IcacheFlush
     753** Description:     This functions flushes the on chip icache.
     754*/
     755
     756     .globl IcacheFlush
     757     .ent IcacheFlush
     758IcacheFlush:
     759
    1807601:
    181         li      v0, SR_PE|SR_FR|SR_KX|SR_SX|SR_UX
    182         mtc0    v0, C0_SR
    183 2:
    184 /* Fix high bits, if any, of the PC so that exception handling
    185    doesn't get confused.  */
    186         LA (v0, 3f)
    187         jr      v0
    188         nop
    189 3:
    190         LA (gp, _gp)                            # set the global data pointer
    191         .end _start
    192 
    193 /*
    194  * zero out the bss section.
    195  */
    196         .globl  __memsize
    197         .globl  zerobss
    198         .ent    zerobss
    199 zerobss:
    200         LA (v0, _fbss)
    201         LA (v1, _end)
    202 3:
    203         sw      zero,0(v0)
    204         bltu    v0,v1,3b
    205         addiu   v0,v0,4                         # executed in delay slot
    206 
    207         la      t0, _stack_init                 # initialize stack so we
    208         /* We must subtract 24 bytes for the 3 8 byte arguments to main, in
    209            case main wants to write them back to the stack.  The caller is
    210            supposed to allocate stack space for parameters in registers in
    211            the old MIPS ABIs.  We must do this even though we aren't passing
    212            arguments, because main might be declared to have them.
    213 
    214            Some ports need a larger alignment for the stack, so we subtract
    215            32, which satisifes the stack for the arguments and keeps the
    216            stack pointer better aligned.  */
    217         subu    t0,t0,32
    218         move    sp,t0                           # set stack pointer
    219         .end    zerobss
    220 
    221         .globl  exit .text
    222         .globl  init
    223         .ent    init
    224 init:
    225 
    226         move    a0,zero                         # set argc to 0
    227         jal     boot_card                       # call the program start function
    228         nop
    229 
    230         # fall through to the "exit" routine
    231         jal     _sys_exit                       # call libc exit to run the G++
    232                                                 # destructors
    233         move    a0,v0                           # pass through the exit code
    234         .end    init
    235        
    236 /*
    237  * _sys_exit -- Exit from the application. Normally we cause a user trap
    238  *          to return to the ROM monitor for another run. NOTE: This is
    239  *          the only other routine we provide in the crt0.o object, since
    240  *          it may be tied to the "_start" routine. It also allows
    241  *          executables that contain a complete world to be linked with
    242  *          just the crt0.o object.
    243  */
    244         .globl  _sys_exit
    245         .ent _sys_exit
    246 _sys_exit:
    247 #ifdef GCRT0
    248         jal     _mcleanup
    249         nop
    250 #endif
    251 
    252         /* return non-zero if we want default behavior, else return to pmon */
    253         bne     a0,zero,7f
    254         nop
    255 
    256         li      t0,PMON_UTIL_ROUTINES           /* base address of PMON's util_routines table */
    257         lw      t0,UTIL_WARMSTART_VECTOR(t0)    /* retrieve _warmstart vector at offset 21*4 */
    258         nop
    259         j       t0                      /* and jump */
    260         nop
    261 
    262         # break instruction can cope with 0xfffff, but GAS limits the range:
    263 7:      break   1023
    264         nop
    265         b       7b                              # but loop back just in-case
    266         nop
    267         .end _sys_exit
    268 
    269 /* EOF crt0.S */
     761     # Assume I cache is already enabled in BIU/Cache setup
     762     # Get contents of M_BIU register and save in t1
     763     li        t0, M_BIU
     764     lw        t1, 0(t0)
     765
     766     .set noreorder
     767
     768     # Isolate I cache
     769     mfc0      t3, C0_SR        /* Read Status Register */
     770     nop
     771     or        t0, t3, SR_ISC   /* Isolate Cache so we don't propagate operations */
     772     mtc0      t0, C0_SR        /* Write it back to Status Register */
     773     nop
     774
     775     # Setup for cache flush
     776     li        t8, 0            /* Store zero */
     777     li        t9, LR33300_IC_SIZE
     778
     779icache_write:
     780     sw        zero, 0(t8)          /* Store zero to memory addres in t8 */
     781     addu      t8, 4                /* Increment t8 addres by 4 */
     782     bltu      t8, t9, icache_write /* check to see if we are done */
     783     nop
     784
     785
     786     # De-isolate I cache
     787     mtc0      t3, C0_SR        /* Load unchanged t3 to Status Register */
     788     nop
     789
     790     jal       ra
     791     nop
     792     .set reorder
     793     .end IcacheFlush
     794
     795
     796/********************************************************
     797** Function Name:   DcacheFlush
     798** Description:     This functions flushes the on chip dcache.
     799*/
     800
     801     .globl DcacheFlush
     802     .ent DcacheFlush
     803DcacheFlush:
     804
     805     # isolate icache
     806     .set noreorder
     807     mfc0      t3,C0_SR
     808     nop
     809     or        t0, t3, SR_ISC
     810     mtc0      t0, C0_SR
     811     nop
     812
     813     # Setup up for cache flush
     814     li        t8, 0
     815     li        t9, LR33300_DC_SIZE
     816
     817dcache_write:
     818     sw        zero, 0(t8)
     819     addu      t8, 4
     820     bltu      t8, t9, dcache_write /* check to see if we are done */
     821     nop
     822
     823     # De-isolate cache
     824     mtc0      t3, C0_SR
     825     nop
     826
     827     jal       ra
     828     nop
     829     .set reorder
     830     .end DcacheFlush
     831
     832
     833/* EOF start.S */

  • c/src/lib/libbsp/mips/genmongoosev/startup/bspstart.c

    r2835b3a5 r7de58239  
    11/*
    2  *  This routine starts the application.  It includes application,
    3  *  board, and monitor specific initialization and configuration.
    4  *  The generic CPU dependent initialization has been performed
    5  *  before this routine is invoked.
    6  *
    7  *  COPYRIGHT (c) 1989-2001.
    8  *  On-Line Applications Research Corporation (OAR).
    9  *
    10  *  The license and distribution terms for this file may be
    11  *  found in the file LICENSE in this distribution or at
    12  *  http://www.OARcorp.com/rtems/license.html.
    13  *
    14  *  $Id$
    15  */
     2**  This routine starts the application.  It includes application,
     3**  board, and monitor specific initialization and configuration.
     4**  The generic CPU dependent initialization has been performed
     5**  before this routine is invoked.
     6**
     7**  COPYRIGHT (c) 1989-2001.
     8**  On-Line Applications Research Corporation (OAR).
     9**
     10**  The license and distribution terms for this file may be
     11**  found in the file LICENSE in this distribution or at
     12**  http://www.OARcorp.com/rtems/license.html.
     13**
     14**  $Id$
     15**
     16** Modification History:
     17**        12/10/01  A.Ferrer, NASA/GSFC, Code 582
     18**           Set interrupt mask to 0xAF00 (Line 139).
     19*/
    1620
    1721#include <string.h>
    … …  
    4044 *  Use the shared implementations of the following routines
    4145 */
    42  
     46
    4347void bsp_postdriver_hook(void);
    4448void bsp_libc_init( void *, unsigned32, int );
    … …  
    5761 *
    5862 */
    59  
     63
    6064void bsp_pretasking_hook(void)
    6165{
    … …  
    8488void bsp_start( void )
    8589{
    86   extern int _end;
    8790  extern int WorkspaceBase;
     91  extern void mips_install_isr_entries();
    8892
    8993  /* Configure Number of Register Caches */
    … …  
    9498
    9599  /* HACK -- tied to value linkcmds */
    96   if ( BSP_Configuration.work_space_size >(4096*1024) )
    97    _sys_exit( 1 );
     100  if ( BSP_Configuration.work_space_size > (4096*1024) )
     101     _sys_exit( 1 );
    98102
    99103  BSP_Configuration.work_space_start = (void *) &WorkspaceBase;
     104
     105  /* mask off any interrupts */
     106  MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_MASK_REGISTER, 0 );
    100107
    101108  MONGOOSEV_WRITE( MONGOOSEV_WATCHDOG, 0xA0 );
    … …  
    113120  MONGOOSEV_WRITE_REGISTER( MONGOOSEV_TIMER2_BASE, MONGOOSEV_TIMER_CONTROL_REGISTER, 0);
    114121
    115   MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_FUNCTION_INTERRUPT_MASK_REGISTER, 0 );
     122  /* clear any pending interrupts */
    116123  MONGOOSEV_WRITE( MONGOOSEV_PERIPHERAL_STATUS_REGISTER, 0xffffffff );
    117124
    … …  
    119126  mips_set_cause( 0 );
    120127
    121   /*all interrupts unmasked but globally off.  depend on the IRC to take care of things */
    122   mips_set_sr( (SR_CU0 | SR_CU1 | 0xff00) );
     128  /* set interrupt mask, but globally off. */
     129
     130  /*
     131  **  Bit 15 | Bit 14 | Bit 13 | Bit 12 | Bit 11 | Bit 10 | Bit  9 | Bit  8 |
     132  **  periph | unused |  FPU   | unused | timer2 | timer1 | swint1 | swint2 |
     133  **  extern |        |        |        |        |        |        |        |
     134  **
     135  **    1        0        1        0        0        1        0        0
     136  **
     137  **    0x8C00   Enable only internal Mongoose V timers.
     138  **    0xA400   Enable Peripherial ints, FPU and timer1
     139  */
     140
     141  mips_set_sr( (SR_CU0 | SR_CU1 | 0xA400) );
    123142
    124143  mips_install_isr_entries();
    … …  
    141160
    142161
    143 void
    144 get_mem_info (mem)
    145      struct s_mem *mem;
     162
     163extern unsigned32 _RamSize;
     164
     165void get_mem_info ( struct s_mem *mem )
    146166{
    147   mem->size = 0x1000000;        /* XXX figure out something here */
     167   mem->size = (unsigned32)&_RamSize;
    148168}
    149169

  • c/src/lib/libbsp/mips/genmongoosev/startup/linkcmds

    r2835b3a5 r7de58239  
    66 */
    77
     8/*    . = 0x80020000; */
     9
    810/*
    911 * Declare some sizes.
    1012 */
     13
    1114_RamBase = DEFINED(_RamBase) ? _RamBase : 0x80000000;
    1215_RamSize = DEFINED(_RamSize) ? _RamSize : 32M;
    13 HeapSize = DEFINED(HeapSize) ? HeapSize : 0x10000;
     16HeapSize = DEFINED(HeapSize) ? HeapSize : 0x40000;
    1417_StackSize = DEFINED(_StackSize) ? _StackSize : 0x1000;
    1518ClockRate = DEFINED(ClockRate) ? ClockRate : 12000000;
    1619
     20
     21
     22MEMORY
     23{
     24   romstore : ORIGIN = 0xbfc40000, LENGTH = 4M
     25   ram      : ORIGIN = 0x80020000, LENGTH = 4M
     26}
     27
    1728SECTIONS
    1829{
    19 /*
    20 Ken's response is correct.  Locate it at 0x80020000 or higher.  The PMON
    21 data segment after the exception vectors and below 0x80020000,
    22 
    23 . = 0x80020000;
    24 */
    25     . = 0x80020000;
    2630    .text :
    2731    {
    … …  
    3640      PROVIDE (__runtime_reloc_start = .);
    3741      *(.rel.sdata)
     42      *(.rel.dyn)
    3843      PROVIDE (__runtime_reloc_stop = .);
    3944      *(.fini)
    40        etext  =  .;
    41        _etext  =  .;
    42     } 
    43   .ctors    :
     45    } >ram  AT>romstore
     46
     47  .ctors    :
    4448  {
    4549    /* gcc uses crtbegin.o to find the start of
    … …  
    6367    KEEP (*(SORT(.ctors.*)))
    6468    KEEP (*(.ctors))
    65   }
     69  } >ram  AT>romstore
    6670
    67   .dtors    :
     71  .dtors    : 
    6872  {
    6973    KEEP (*crtbegin.o(.dtors))
    … …  
    7175    KEEP (*(SORT(.dtors.*)))
    7276    KEEP (*(.dtors))
    73   }
    7477
    75     . = .;
    76   .rdata : {
     78    etext  =  .;
     79    _etext  =  .;
     80  } >ram  AT>romstore
     81
     82/*    . = .; */
     83
     84  .rdata :
     85  {
    7786    *(.rdata)
    7887    *(.rodata)
    7988    *(.rodata.*)
    8089    *(.gnu.linkonce.r*)
    81   }
    82    _fdata = ALIGN(16);
    83   .data : {
     90  } >ram  AT>romstore
     91
     92  .data :
     93  {
     94    _fdata = ALIGN(16);
     95
    8496    *(.data)
    8597    *(.data.*)
    8698    *(.gnu.linkonce.d*)
    87   }
    88   . = ALIGN(8);
    89   _gp = . + 0x8000;
    90   __global = _gp;
    91   .lit8 : {
     99  } >ram  AT>romstore
     100
     101
     102  .lit8 :
     103  {
     104    . = ALIGN(8);
     105
     106    _gp = . + 0x8000;
     107    __global = _gp;
    92108    *(.lit8)
    93   }
    94   .lit4 : {
     109  } >ram  AT>romstore
     110
     111  .lit4 :
     112  {
    95113    *(.lit4)
    96   }
    97   .sdata : {
     114  } >ram  AT>romstore
     115
     116  .sdata :   
     117  {
    98118    *(.sdata)
    99119    *(.sdata.*)
    100120    *(.gnu.linkonce.s*)
    101   }
     121  } >ram  AT>romstore
     122
     123  .sbss :
     124  {
    102125  . = ALIGN(4);
    103126   edata  =  .;
    104127   _edata  =  .;
    105128   _fbss = .;
    106   .sbss : {
    107129    *(.sbss)
    108130    *(.scommon)
    109   }
    110   .bss : {
     131  } >ram  AT>romstore
     132
     133
     134  .bss :
     135  {
    111136    _bss_start = . ;
    112137    *(.bss)
     138    *(.reginfo)
    113139    *(COMMON)
    114140    . = ALIGN (64);
    … …  
    121147    . += HeapSize;    /* reserve some memory for heap */
    122148    WorkspaceBase = .;
    123   }
    124  end = .;
    125  _end = .;
     149    end = .;
     150    _end = .;
     151  } >ram  AT>romstore
    126152
    127153
    128 /* Put starting stack in SRAM (8 Kb); this size is the same as the stack from
    129       the original script (when everything was in SRAM). */
    130    /* __stack = 0x8000A000; */
    131   /* DWARF debug sections.
    132      Symbols in the DWARF debugging sections are relative to
    133      the beginning of the section so we begin them at 0.  */
     154/*
     155** DWARF debug sections.
     156** Symbols in the DWARF debugging sections are relative to
     157** the beginning of the section so we begin them at 0. 
     158*/
    134159
    135160  /* DWARF 1 */
    136   .debug          0 : { *(.debug) }
    137   .line           0 : { *(.line) }
     161  .debug          0 : { *(.debug) } AT>romstore
     162  .line           0 : { *(.line) } AT>romstore
    138163
    139164  /* GNU DWARF 1 extensions */
    140   .debug_srcinfo  0 : { *(.debug_srcinfo) }
    141   .debug_sfnames  0 : { *(.debug_sfnames) }
     165  .debug_srcinfo  0 : { *(.debug_srcinfo) } AT>romstore
     166  .debug_sfnames  0 : { *(.debug_sfnames) } AT>romstore
    142167
    143168  /* DWARF 1.1 and DWARF 2 */
    144   .debug_aranges  0 : { *(.debug_aranges) }
    145   .debug_pubnames 0 : { *(.debug_pubnames) }
     169  .debug_aranges  0 : { *(.debug_aranges) } AT>romstore
     170  .debug_pubnames 0 : { *(.debug_pubnames) } AT>romstore
    146171
    147172  /* DWARF 2 */
    148   .debug_info     0 : { *(.debug_info) }
    149   .debug_abbrev   0 : { *(.debug_abbrev) }
    150   .debug_line     0 : { *(.debug_line) }
    151   .debug_frame    0 : { *(.debug_frame) }
    152   .debug_str      0 : { *(.debug_str) }
    153   .debug_loc      0 : { *(.debug_loc) }
    154   .debug_macinfo  0 : { *(.debug_macinfo) }
     173  .debug_info     0 : { *(.debug_info) }    AT>romstore
     174  .debug_abbrev   0 : { *(.debug_abbrev) }  AT>romstore
     175  .debug_line     0 : { *(.debug_line) }    AT>romstore
     176  .debug_frame    0 : { *(.debug_frame)}    AT>romstore
     177  .debug_str      0 : { *(.debug_str) }     AT>romstore
     178  .debug_loc      0 : { *(.debug_loc) }     AT>romstore
     179  .debug_macinfo  0 : { *(.debug_macinfo) } AT>romstore
    155180
    156181  /* SGI/MIPS DWARF 2 extensions */
    157   .debug_weaknames 0 : { *(.debug_weaknames) }
    158   .debug_funcnames 0 : { *(.debug_funcnames) }
    159   .debug_typenames 0 : { *(.debug_typenames) }
    160   .debug_varnames  0 : { *(.debug_varnames) }
     182  .debug_weaknames 0 : { *(.debug_weaknames) } AT>romstore
     183  .debug_funcnames 0 : { *(.debug_funcnames) } AT>romstore
     184  .debug_typenames 0 : { *(.debug_typenames) } AT>romstore
     185  .debug_varnames  0 : { *(.debug_varnames) }  AT>romstore
    161186}

  • c/src/lib/libbsp/mips/genmongoosev/timer/timer.c

    r2835b3a5 r7de58239  
    5555#define LEAST_VALID       1  /* Don't trust a value lower than this */
    5656                             /* mongoose-v can count cycles. :) */
    57 #include <rtems/bspIo.h>
     57#include <bspIo.h>
    5858
    5959int Read_timer()
Note: See TracChangeset for help on using the changeset viewer.