Ignore:
Timestamp:
Sep 21, 2014, 6:07:41 PM (6 years ago)
Author:
Tomasz Gregorek <tomasz.gregorek@…>
Branches:
4.11, master
Children:
56ed56a6
Parents:
9a8b2984
git-author:
Tomasz Gregorek <tomasz.gregorek@…> (09/21/14 18:07:41)
git-committer:
Sebastian Huber <sebastian.huber@…> (10/02/14 05:54:52)
Message:

bsp/stm32f4XXXX: System clock configuration

Added simple math to caclulate register values for the PLL
and for the prescalers. It will try to keep 48MHz for the USB OTG FS.
Also it will set latency on the Flash memory for the high speeds.

Limitations:
It is assumed that 1MHz resolution is enough.
Best fits for the clocks are achieved with multiplies of 42MHz.
Even though APB1, APB2 and AHB are calculated user is still required
to provide correct values for the bsp configuration for the:
STM32F4_PCLK1
STM32F4_PCLK2
STM32F4_HCLK (= system clock)
as those are used for the peripheral clocking calculations.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/stm32f4/include/stm32f4xxxx_rcc.h

    r9a8b2984 r7db6953  
    3232
    3333typedef struct {
    34         uint32_t cr;
    35         uint32_t pllcfgr;
    36         uint32_t cfgr;
    37         uint32_t cir;
    38         uint32_t ahbrstr [3];
    39         uint32_t reserved_1c;
    40         uint32_t apbrstr [2];
    41         uint32_t reserved_28 [2];
    42         uint32_t ahbenr [3];
    43         uint32_t reserved_3c;
    44         uint32_t apbenr [2];
    45         uint32_t reserved_48 [2];
    46         uint32_t ahblpenr [3];
    47         uint32_t reserved_5c;
    48         uint32_t apblpenr [2];
    49         uint32_t reserved_68 [2];
    50         uint32_t bdcr;
    51         uint32_t csr;
    52         uint32_t reserved_78 [2];
    53         uint32_t sscgr;
    54         uint32_t plli2scfgr;
     34  uint32_t cr;
     35  uint32_t pllcfgr;
     36  uint32_t cfgr;
     37  uint32_t cir;
     38  uint32_t ahbrstr[ 3 ];
     39  uint32_t reserved_1c;
     40  uint32_t apbrstr[ 2 ];
     41  uint32_t reserved_28[ 2 ];
     42  uint32_t ahbenr[ 3 ];
     43  uint32_t reserved_3c;
     44  uint32_t apbenr[ 2 ];
     45  uint32_t reserved_48[ 2 ];
     46  uint32_t ahblpenr[ 3 ];
     47  uint32_t reserved_5c;
     48  uint32_t apblpenr[ 2 ];
     49  uint32_t reserved_68[ 2 ];
     50  uint32_t bdcr;
     51  uint32_t csr;
     52  uint32_t reserved_78[ 2 ];
     53  uint32_t sscgr;
     54  uint32_t plli2scfgr;
    5555} stm32f4_rcc;
    5656
    5757/** @} */
    5858
     59#define RCC_CR_HSION BSP_BIT32( 0 )
     60#define RCC_CR_HSIRDY BSP_BIT32( 1 )
     61#define RCC_CR_HSITRIM( val ) BSP_FLD32( val, 3, 7 )
     62#define RCC_CR_HSITRIM_MSK BSP_MSK32( 3, 7 )
     63#define RCC_CR_HSICAL( val ) BSP_FLD32( val, 8, 15 )
     64#define RCC_CR_HSICAL_MSK BSP_MSK32( 8, 15 )
     65#define RCC_CR_HSEON BSP_BIT32( 16 )
     66#define RCC_CR_HSERDY BSP_BIT32( 17 )
     67#define RCC_CR_HSEBYP BSP_BIT32( 18 )
     68#define RCC_CR_CSSON BSP_BIT32( 19 )
     69#define RCC_CR_PLLON BSP_BIT32( 24 )
     70#define RCC_CR_PLLRDY BSP_BIT32( 25 )
     71#define RCC_CR_PLLI2SON BSP_BIT32( 26 )
     72#define RCC_CR_PLLI2SRDY BSP_BIT32( 27 )
     73
     74#define RCC_PLLCFGR_PLLM( val ) BSP_FLD32( val, 0, 5 )
     75#define RCC_PLLCFGR_PLLM_MSK BSP_MSK32( 0, 5 )
     76#define RCC_PLLCFGR_PLLN( val ) BSP_FLD32( val, 6, 14 )
     77#define RCC_PLLCFGR_PLLN_MSK BSP_MSK32( 6, 14 )
     78
     79#define RCC_PLLCFGR_PLLP 16
     80#define RCC_PLLCFGR_PLLP_MSK BSP_MSK32( 16, 17 )
     81#define RCC_PLLCFGR_PLLP_BY_2 0
     82#define RCC_PLLCFGR_PLLP_BY_4 BSP_FLD32( 1, 16, 17 )
     83#define RCC_PLLCFGR_PLLP_BY_6 BSP_FLD32( 2, 16, 17 )
     84#define RCC_PLLCFGR_PLLP_BY_8 BSP_FLD32( 3, 16, 17 )
     85
     86#define RCC_PLLCFGR_PLLSRC_HSE BSP_BIT32( 22 )
     87#define RCC_PLLCFGR_PLLSRC_HSI 0
     88
     89#define RCC_PLLCFGR_PLLQ( val ) BSP_FLD32( val, 24, 27 )
     90#define RCC_PLLCFGR_PLLQ_MSK BSP_MSK32( 24, 27 )
     91
     92#define RCC_CFGR_SW 0
     93#define RCC_CFGR_SW_MSK BSP_MSK32( 0, 1 )
     94#define RCC_CFGR_SW_HSI 0
     95#define RCC_CFGR_SW_HSE 1
     96#define RCC_CFGR_SW_PLL 2
     97
     98#define RCC_CFGR_SWS 2
     99#define RCC_CFGR_SWS_MSK BSP_MSK32( 2, 3 )
     100#define RCC_CFGR_SWS_HSI 0
     101#define RCC_CFGR_SWS_HSE BSP_FLD32( 1, 2, 3 )
     102#define RCC_CFGR_SWS_PLL BSP_FLD32( 2, 2, 3 )
     103
     104#define RCC_CFGR_HPRE 4
     105#define RCC_CFGR_HPRE_BY_1 0
     106#define RCC_CFGR_HPRE_BY_2 BSP_FLD32( 8, 4, 7 )
     107#define RCC_CFGR_HPRE_BY_4 BSP_FLD32( 9, 4, 7 )
     108#define RCC_CFGR_HPRE_BY_8 BSP_FLD32( 10, 4, 7 )
     109#define RCC_CFGR_HPRE_BY_16 BSP_FLD32( 11, 4, 7 )
     110#define RCC_CFGR_HPRE_BY_64 BSP_FLD32( 12, 4, 7 )
     111#define RCC_CFGR_HPRE_BY_128 BSP_FLD32( 13, 4, 7 )
     112#define RCC_CFGR_HPRE_BY_256 BSP_FLD32( 14, 4, 7 )
     113#define RCC_CFGR_HPRE_BY_512 BSP_FLD32( 15, 4, 7 )
     114
     115#define RCC_CFGR_PPRE1 10
     116#define RCC_CFGR_PPRE1_BY_1 0
     117#define RCC_CFGR_PPRE1_BY_2 BSP_FLD32( 4, 10, 12 )
     118#define RCC_CFGR_PPRE1_BY_4 BSP_FLD32( 5, 10, 12 )
     119#define RCC_CFGR_PPRE1_BY_8 BSP_FLD32( 6, 10, 12 )
     120#define RCC_CFGR_PPRE1_BY_16 BSP_FLD32( 7, 10, 12 )
     121
     122#define RCC_CFGR_PPRE2 13
     123#define RCC_CFGR_PPRE2 BSP_MSK32( 13, 15 )
     124#define RCC_CFGR_PPRE2_BY_1 0
     125#define RCC_CFGR_PPRE2_BY_2 BSP_FLD32( 4, 13, 15 )
     126#define RCC_CFGR_PPRE2_BY_4 BSP_FLD32( 5, 13, 15 )
     127#define RCC_CFGR_PPRE2_BY_8 BSP_FLD32( 6, 13, 15 )
     128#define RCC_CFGR_PPRE2_BY_16 BSP_FLD32( 7, 13, 15 )
     129
     130#define RCC_CFGR_RTCPRE( val ) BSP_FLD32( val, 16, 20 )
     131#define RCC_CFGR_RTCPRE_MSK BSP_MSK32( 16, 20 )
     132
     133#define RCC_CFGR_MCO1 21
     134#define RCC_CFGR_MCO1_MSK BSP_MSK32( 21, 22 )
     135#define RCC_CFGR_MCO1_HSI 0
     136#define RCC_CFGR_MCO1_LSE BSP_FLD32( 1, 21, 22 )
     137#define RCC_CFGR_MCO1_HSE BSP_FLD32( 2, 21, 22 )
     138#define RCC_CFGR_MCO1_PLL BSP_FLD32( 3, 21, 22 )
     139
     140#define RCC_CFGR_I2SSRC BSP_BIT32( 23 )
     141
     142#define RCC_CFGR_MCO1PRE 24
     143#define RCC_CFGR_MCO1PRE_MSK BSP_MSK32( 24, 26 )
     144#define RCC_CFGR_MCO1PRE_BY_1 0
     145#define RCC_CFGR_MCO1PRE_BY_2 BSP_FLD32( 4, 24, 26 )
     146#define RCC_CFGR_MCO1PRE_BY_3 BSP_FLD32( 5, 24, 26 )
     147#define RCC_CFGR_MCO1PRE_BY_4 BSP_FLD32( 6, 24, 26 )
     148#define RCC_CFGR_MCO1PRE_BY_5 BSP_FLD32( 7, 24, 26 )
     149
     150#define RCC_CFGR_MCO2PRE 27
     151#define RCC_CFGR_MCO2PRE_MSK BSP_MSK32( 27, 29 )
     152#define RCC_CFGR_MCO2PRE_BY_1 0
     153#define RCC_CFGR_MCO2PRE_BY_2 BSP_FLD32( 4, 27, 29 )
     154#define RCC_CFGR_MCO2PRE_BY_3 BSP_FLD32( 5, 27, 29 )
     155#define RCC_CFGR_MCO2PRE_BY_4 BSP_FLD32( 6, 27, 29 )
     156#define RCC_CFGR_MCO2PRE_BY_5 BSP_FLD32( 7, 27, 29 )
     157
     158#define RCC_CFGR_MCO2 30
     159#define RCC_CFGR_MCO2_MSK BSP_MSK32( 30, 31 )
     160#define RCC_CFGR_MCO2_SYSCLK 0
     161#define RCC_CFGR_MCO2_PLLI2S BSP_FLD32( 1, 30, 31 )
     162#define RCC_CFGR_MCO2_HSE BSP_FLD32( 2, 30, 31 )
     163#define RCC_CFGR_MCO2_PLL BSP_FLD32( 3, 30, 31 )
     164
    59165#endif /* LIBBSP_ARM_STM32F4_STM32F4XXXX_RCC_H */
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