Ignore:
Timestamp:
Sep 21, 2014, 6:07:41 PM (6 years ago)
Author:
Tomasz Gregorek <tomasz.gregorek@…>
Branches:
4.11, master
Children:
56ed56a6
Parents:
9a8b2984
git-author:
Tomasz Gregorek <tomasz.gregorek@…> (09/21/14 18:07:41)
git-committer:
Sebastian Huber <sebastian.huber@…> (10/02/14 05:54:52)
Message:

bsp/stm32f4XXXX: System clock configuration

Added simple math to caclulate register values for the PLL
and for the prescalers. It will try to keep 48MHz for the USB OTG FS.
Also it will set latency on the Flash memory for the high speeds.

Limitations:
It is assumed that 1MHz resolution is enough.
Best fits for the clocks are achieved with multiplies of 42MHz.
Even though APB1, APB2 and AHB are calculated user is still required
to provide correct values for the bsp configuration for the:
STM32F4_PCLK1
STM32F4_PCLK2
STM32F4_HCLK (= system clock)
as those are used for the peripheral clocking calculations.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/stm32f4/Makefile.am

    r9a8b2984 r7db6953  
    5252include_bsp_HEADERS += include/stm32f4xxxx_gpio.h
    5353include_bsp_HEADERS += include/stm32f4xxxx_rcc.h
     54include_bsp_HEADERS += include/stm32f4xxxx_flash.h
    5455include_bsp_HEADERS += include/stm32_i2c.h
    5556include_bsp_HEADERS += include/i2c.h
Note: See TracChangeset for help on using the changeset viewer.