Changeset 7d953c2 in rtems


Ignore:
Timestamp:
Oct 12, 2001, 5:46:47 PM (20 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
59e73f37
Parents:
bc5fc7a6
Message:

2001-10-12 Joel Sherrill <joel@…>

  • asm.h, cpu.c, rtems.c, rtems/score/cpu.h, rtems/score/sh.h, rtems/score/sh_io.h, rtems/score/shtypes.h: Consistency changes and made sure there were no includes from the libcpu tree.
Files:
17 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/sh/ChangeLog

    rbc5fc7a6 r7d953c2  
     12001-10-12      Joel Sherrill <joel@OARcorp.com>
     2
     3        * asm.h, cpu.c, rtems.c, rtems/score/cpu.h, rtems/score/sh.h,
     4        rtems/score/sh_io.h, rtems/score/shtypes.h: Consistency changes
     5        and made sure there were no includes from the libcpu tree.
     6
    172001-10-12      Alexandra Kossovsky <sasha@oktet.ru>
    28
  • c/src/exec/score/cpu/sh/asm.h

    rbc5fc7a6 r7d953c2  
    2828 *
    2929 *
    30  *  COPYRIGHT (c) 1998.
     30 *  COPYRIGHT (c) 1998-2001.
    3131 *  On-Line Applications Research Corporation (OAR).
    32  *  Copyright assigned to U.S. Government, 1994.
    3332 *
    3433 *  The license and distribution terms for this file may be
  • c/src/exec/score/cpu/sh/cpu.c

    rbc5fc7a6 r7d953c2  
    1313 *
    1414 *
    15  *  COPYRIGHT (c) 1998.
     15 *  COPYRIGHT (c) 1998-2001.
    1616 *  On-Line Applications Research Corporation (OAR).
    17  *  Copyright assigned to U.S. Government, 1994.
    1817 *
    1918 *  The license and distribution terms for this file may be
     
    2928#include <rtems/score/cpu.h>
    3029#include <rtems/score/sh.h>
    31 
    32 /* FIXME: This should not be here */
    33 #if defined(__SH4__)
    34 #include <rtems/score/sh4_regs.h>
    35 #endif
    3630
    3731/* referenced in start.S */
  • c/src/exec/score/cpu/sh/rtems.c

    rbc5fc7a6 r7d953c2  
    1616 *
    1717 *
    18  *  COPYRIGHT (c) 1998.
     18 *  COPYRIGHT (c) 1998-2001.
    1919 *  On-Line Applications Research Corporation (OAR).
    20  *  Copyright assigned to U.S. Government, 1994.
    2120 *
    2221 *  The license and distribution terms for this file may be
  • c/src/exec/score/cpu/sh/rtems/score/cpu.h

    rbc5fc7a6 r7d953c2  
    1313 *
    1414 *
    15  *  COPYRIGHT (c) 1998.
     15 *  COPYRIGHT (c) 1998-2001.
    1616 *  On-Line Applications Research Corporation (OAR).
    17  *  Copyright assigned to U.S. Government, 1994.
    1817 *
    1918 *  The license and distribution terms for this file may be
     
    136135
    137136#if SH_HAS_FPU
    138 /* FIXME: What about CPU_SOFTWARE_FP ? */
    139137#define CPU_HARDWARE_FP TRUE
     138#define CPU_SOFTWARE_FP FALSE
    140139#else
    141140#define CPU_SOFTWARE_FP FALSE
     
    212211#define CPU_USE_DEFERRED_FP_SWITCH      FALSE
    213212#else
    214 /* FIXME: Is this needed?
    215  * Only here for backward compatibility with previous versions
    216  */
    217213#define CPU_USE_DEFERRED_FP_SWITCH      TRUE
    218214#endif
  • c/src/exec/score/cpu/sh/rtems/score/sh.h

    rbc5fc7a6 r7d953c2  
    1414 *
    1515 *
    16  *  COPYRIGHT (c) 1998.
     16 *  COPYRIGHT (c) 1998-2001.
    1717 *  On-Line Applications Research Corporation (OAR).
    18  *  Copyright assigned to U.S. Government, 1994.
    1918 *
    2019 *  The license and distribution terms for this file may be
     
    220219#endif /* !ASM */
    221220
     221/*
     222 * Bits on SH-4 registers.
     223 * See SH-4 Programming manual for more details.
     224 *
     225 * Added by Alexandra Kossovsky <sasha@oktet.ru>
     226 */
     227
     228#if defined(__SH4__)
     229#define SH4_SR_MD          0x40000000 /* Priveleged mode */
     230#define SH4_SR_RB          0x20000000 /* General register bank specifier */
     231#define SH4_SR_BL          0x10000000 /* Exeption/interrupt masking bit */
     232#define SH4_SR_FD          0x00008000 /* FPU disable bit */
     233#define SH4_SR_M           0x00000200 /* For signed division:
     234                                         divisor (module) is negative */
     235#define SH4_SR_Q           0x00000100 /* For signed division:
     236                                         dividend (and quotient) is negative */
     237#define SH4_SR_IMASK       0x000000f0 /* Interrupt mask level */
     238#define SH4_SR_IMASK_S     4
     239#define SH4_SR_S           0x00000002 /* Saturation for MAC instruction:
     240                                         if set, data in MACH/L register
     241                                         is restricted to 48/32 bits
     242                                         for MAC.W/L instructions */
     243#define SH4_SR_T           0x00000001 /* 1 if last condiyion was true */
     244#define SH4_SR_RESERV      0x8fff7d0d /* Reserved bits, read/write as 0 */
     245
     246/* FPSCR -- FPU Starus/Control Register */
     247#define SH4_FPSCR_FR       0x00200000 /* FPU register bank specifier */
     248#define SH4_FPSCR_SZ       0x00100000 /* FMOV 64-bit transfer mode */
     249#define SH4_FPSCR_PR       0x00080000 /* Double-percision floating-point
     250                                         operations flag */
     251                                      /* SH4_FPSCR_SZ & SH4_FPSCR_PR != 1 */
     252#define SH4_FPSCR_DN       0x00040000 /* Treat denormalized number as zero */
     253#define SH4_FPSCR_CAUSE    0x0003f000 /* FPU exeption cause field */
     254#define SH4_FPSCR_CAUSE_S  12
     255#define SH4_FPSCR_ENABLE   0x00000f80 /* FPU exeption enable field */
     256#define SH4_FPSCR_ENABLE_s 7
     257#define SH4_FPSCR_FLAG     0x0000007d /* FPU exeption flag field */
     258#define SH4_FPSCR_FLAG_S   2
     259#define SH4_FPSCR_RM       0x00000001 /* Rounding mode:
     260                                         1/0 -- round to zero/nearest */
     261#define SH4_FPSCR_RESERV   0xffd00000 /* Reserved bits, read/write as 0 */
     262
     263#endif
     264
    222265#ifdef __cplusplus
    223266}
  • c/src/exec/score/cpu/sh/rtems/score/sh_io.h

    rbc5fc7a6 r7d953c2  
    1515 *
    1616 *
    17  *  COPYRIGHT (c) 1998.
     17 *  COPYRIGHT (c) 1998-2001.
    1818 *  On-Line Applications Research Corporation (OAR).
    19  *  Copyright assigned to U.S. Government, 1994.
    2019 *
    2120 *  The license and distribution terms for this file may be
  • c/src/exec/score/cpu/sh/rtems/score/shtypes.h

    rbc5fc7a6 r7d953c2  
    1313 *
    1414 *
    15  *  COPYRIGHT (c) 1998.
     15 *  COPYRIGHT (c) 1998-2001.
    1616 *  On-Line Applications Research Corporation (OAR).
    17  *  Copyright assigned to U.S. Government, 1994.
    1817 *
    1918 *  The license and distribution terms for this file may be
  • c/src/exec/score/cpu/sh/rtems/score/types.h

    rbc5fc7a6 r7d953c2  
    1313 *
    1414 *
    15  *  COPYRIGHT (c) 1998.
     15 *  COPYRIGHT (c) 1998-2001.
    1616 *  On-Line Applications Research Corporation (OAR).
    17  *  Copyright assigned to U.S. Government, 1994.
    1817 *
    1918 *  The license and distribution terms for this file may be
  • cpukit/score/cpu/sh/ChangeLog

    rbc5fc7a6 r7d953c2  
     12001-10-12      Joel Sherrill <joel@OARcorp.com>
     2
     3        * asm.h, cpu.c, rtems.c, rtems/score/cpu.h, rtems/score/sh.h,
     4        rtems/score/sh_io.h, rtems/score/shtypes.h: Consistency changes
     5        and made sure there were no includes from the libcpu tree.
     6
    172001-10-12      Alexandra Kossovsky <sasha@oktet.ru>
    28
  • cpukit/score/cpu/sh/asm.h

    rbc5fc7a6 r7d953c2  
    2828 *
    2929 *
    30  *  COPYRIGHT (c) 1998.
     30 *  COPYRIGHT (c) 1998-2001.
    3131 *  On-Line Applications Research Corporation (OAR).
    32  *  Copyright assigned to U.S. Government, 1994.
    3332 *
    3433 *  The license and distribution terms for this file may be
  • cpukit/score/cpu/sh/cpu.c

    rbc5fc7a6 r7d953c2  
    1313 *
    1414 *
    15  *  COPYRIGHT (c) 1998.
     15 *  COPYRIGHT (c) 1998-2001.
    1616 *  On-Line Applications Research Corporation (OAR).
    17  *  Copyright assigned to U.S. Government, 1994.
    1817 *
    1918 *  The license and distribution terms for this file may be
     
    2928#include <rtems/score/cpu.h>
    3029#include <rtems/score/sh.h>
    31 
    32 /* FIXME: This should not be here */
    33 #if defined(__SH4__)
    34 #include <rtems/score/sh4_regs.h>
    35 #endif
    3630
    3731/* referenced in start.S */
  • cpukit/score/cpu/sh/rtems/asm.h

    rbc5fc7a6 r7d953c2  
    2828 *
    2929 *
    30  *  COPYRIGHT (c) 1998.
     30 *  COPYRIGHT (c) 1998-2001.
    3131 *  On-Line Applications Research Corporation (OAR).
    32  *  Copyright assigned to U.S. Government, 1994.
    3332 *
    3433 *  The license and distribution terms for this file may be
  • cpukit/score/cpu/sh/rtems/score/cpu.h

    rbc5fc7a6 r7d953c2  
    1313 *
    1414 *
    15  *  COPYRIGHT (c) 1998.
     15 *  COPYRIGHT (c) 1998-2001.
    1616 *  On-Line Applications Research Corporation (OAR).
    17  *  Copyright assigned to U.S. Government, 1994.
    1817 *
    1918 *  The license and distribution terms for this file may be
     
    136135
    137136#if SH_HAS_FPU
    138 /* FIXME: What about CPU_SOFTWARE_FP ? */
    139137#define CPU_HARDWARE_FP TRUE
     138#define CPU_SOFTWARE_FP FALSE
    140139#else
    141140#define CPU_SOFTWARE_FP FALSE
     
    212211#define CPU_USE_DEFERRED_FP_SWITCH      FALSE
    213212#else
    214 /* FIXME: Is this needed?
    215  * Only here for backward compatibility with previous versions
    216  */
    217213#define CPU_USE_DEFERRED_FP_SWITCH      TRUE
    218214#endif
  • cpukit/score/cpu/sh/rtems/score/sh.h

    rbc5fc7a6 r7d953c2  
    1414 *
    1515 *
    16  *  COPYRIGHT (c) 1998.
     16 *  COPYRIGHT (c) 1998-2001.
    1717 *  On-Line Applications Research Corporation (OAR).
    18  *  Copyright assigned to U.S. Government, 1994.
    1918 *
    2019 *  The license and distribution terms for this file may be
     
    220219#endif /* !ASM */
    221220
     221/*
     222 * Bits on SH-4 registers.
     223 * See SH-4 Programming manual for more details.
     224 *
     225 * Added by Alexandra Kossovsky <sasha@oktet.ru>
     226 */
     227
     228#if defined(__SH4__)
     229#define SH4_SR_MD          0x40000000 /* Priveleged mode */
     230#define SH4_SR_RB          0x20000000 /* General register bank specifier */
     231#define SH4_SR_BL          0x10000000 /* Exeption/interrupt masking bit */
     232#define SH4_SR_FD          0x00008000 /* FPU disable bit */
     233#define SH4_SR_M           0x00000200 /* For signed division:
     234                                         divisor (module) is negative */
     235#define SH4_SR_Q           0x00000100 /* For signed division:
     236                                         dividend (and quotient) is negative */
     237#define SH4_SR_IMASK       0x000000f0 /* Interrupt mask level */
     238#define SH4_SR_IMASK_S     4
     239#define SH4_SR_S           0x00000002 /* Saturation for MAC instruction:
     240                                         if set, data in MACH/L register
     241                                         is restricted to 48/32 bits
     242                                         for MAC.W/L instructions */
     243#define SH4_SR_T           0x00000001 /* 1 if last condiyion was true */
     244#define SH4_SR_RESERV      0x8fff7d0d /* Reserved bits, read/write as 0 */
     245
     246/* FPSCR -- FPU Starus/Control Register */
     247#define SH4_FPSCR_FR       0x00200000 /* FPU register bank specifier */
     248#define SH4_FPSCR_SZ       0x00100000 /* FMOV 64-bit transfer mode */
     249#define SH4_FPSCR_PR       0x00080000 /* Double-percision floating-point
     250                                         operations flag */
     251                                      /* SH4_FPSCR_SZ & SH4_FPSCR_PR != 1 */
     252#define SH4_FPSCR_DN       0x00040000 /* Treat denormalized number as zero */
     253#define SH4_FPSCR_CAUSE    0x0003f000 /* FPU exeption cause field */
     254#define SH4_FPSCR_CAUSE_S  12
     255#define SH4_FPSCR_ENABLE   0x00000f80 /* FPU exeption enable field */
     256#define SH4_FPSCR_ENABLE_s 7
     257#define SH4_FPSCR_FLAG     0x0000007d /* FPU exeption flag field */
     258#define SH4_FPSCR_FLAG_S   2
     259#define SH4_FPSCR_RM       0x00000001 /* Rounding mode:
     260                                         1/0 -- round to zero/nearest */
     261#define SH4_FPSCR_RESERV   0xffd00000 /* Reserved bits, read/write as 0 */
     262
     263#endif
     264
    222265#ifdef __cplusplus
    223266}
  • cpukit/score/cpu/sh/rtems/score/sh_io.h

    rbc5fc7a6 r7d953c2  
    1515 *
    1616 *
    17  *  COPYRIGHT (c) 1998.
     17 *  COPYRIGHT (c) 1998-2001.
    1818 *  On-Line Applications Research Corporation (OAR).
    19  *  Copyright assigned to U.S. Government, 1994.
    2019 *
    2120 *  The license and distribution terms for this file may be
  • cpukit/score/cpu/sh/rtems/score/types.h

    rbc5fc7a6 r7d953c2  
    1313 *
    1414 *
    15  *  COPYRIGHT (c) 1998.
     15 *  COPYRIGHT (c) 1998-2001.
    1616 *  On-Line Applications Research Corporation (OAR).
    17  *  Copyright assigned to U.S. Government, 1994.
    1817 *
    1918 *  The license and distribution terms for this file may be
Note: See TracChangeset for help on using the changeset viewer.