Changeset 7d7cbf3c in rtems


Ignore:
Timestamp:
Jun 6, 2019, 5:53:09 AM (5 months ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
master
Children:
a3818705
Parents:
98fc6014
git-author:
Sebastian Huber <sebastian.huber@…> (06/06/19 05:53:09)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/06/19 06:40:43)
Message:

sparc: Improve _CPU_Context_validate()

Use the FPU and check that the condition codes in the PSR are preserved.

Update #3756.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/sparc/sparc-context-validate.S

    r98fc6014 r7d7cbf3c  
    4444  ((FRAME_END + CPU_STACK_ALIGNMENT - 1) & ~(CPU_STACK_ALIGNMENT - 1))
    4545
     46/*
     47 * The FSR pattern is masked with undefined fields, reserved fields, ftt
     48 * (cleared by fmovs), cexc (cleared by fmovs), and system-specific values
     49 * (e.g. FPU architecture version, FP queue).
     50 */
     51#define FSR_PATTERN_MASK 0xcf800fe0
     52
    4653.macro check_register reg
    4754        sub     %g1, 1, %g1
     
    5461        sub     %g1, 1, %g1
    5562        st      \reg, [%sp + FRAME_OFFSET_BUFFER_0]
     63        cmp     %g0, %sp
     64        fmovs   \reg, \reg
     65        be      restore_registers
     66         nop
     67        cmp     %g0, %g0
     68        fmovs   \reg, \reg
     69        bne     restore_registers
     70         nop
    5671        ld      [%sp + FRAME_OFFSET_BUFFER_0], %o1
    5772        cmp     %g1, %o1
     
    129144         nop
    130145
    131         /*
    132          * Write pattern to FSR.  FSR is masked with undefined, reserved or
    133          * system-specific values (e.g. FPU architecture version, FP queue).
    134          */
     146        /* Write masked pattern to FSR */
    135147        st      %fsr, [%sp + FRAME_OFFSET_BUFFER_0]
    136148        ld      [%sp + FRAME_OFFSET_BUFFER_0], %o1
    137149        add     %g1, 1, %g1
    138         sethi   %hi(0xCF800000), %g3
    139         or      %g3, %lo(0x0FFF), %g3
     150        sethi   %hi(FSR_PATTERN_MASK), %g3
     151        or      %g3, %lo(FSR_PATTERN_MASK), %g3
    140152        and     %g1, %g3, %g3
    141153        or      %o1, %g3, %g3
     
    325337        sub     %g1, 1, %g1
    326338        clr     %g3
    327         sethi   %hi(0xCF800000), %g3
    328         or      %g3, %lo(0x0FFF), %g3
     339        sethi   %hi(FSR_PATTERN_MASK), %g3
     340        or      %g3, %lo(FSR_PATTERN_MASK), %g3
    329341        and     %g1, %g3, %g3
    330342        and     %o1, %g3, %o1
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