Changeset 7d066fc in rtems


Ignore:
Timestamp:
Feb 13, 2014, 2:39:18 PM (6 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
4.11, master
Children:
0344ce03
Parents:
8a9568d
git-author:
Sebastian Huber <sebastian.huber@…> (02/13/14 14:39:18)
git-committer:
Sebastian Huber <sebastian.huber@…> (02/17/14 07:46:38)
Message:

smptests/smplock01: Use atomic operations

File:
1 edited

Legend:

Unmodified
Added
Removed
  • testsuites/smptests/smplock01/init.c

    r8a9568d r7d066fc  
    11/*
    2  * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
     2 * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
    33 *
    44 *  embedded brains GmbH
     
    1717#endif
    1818
     19#include <rtems/score/smplock.h>
     20#include <rtems/score/atomic.h>
    1921#include <rtems.h>
    2022
    2123#include "tmacros.h"
    2224
    23 /* FIXME: Use C11 for atomic operations */
    24 
    25 static void atomic_store(int *addr, int value)
    26 {
    27   *addr = value;
    28 
    29   RTEMS_COMPILER_MEMORY_BARRIER();
    30 }
    31 
    32 static unsigned int atomic_load(const int *addr)
    33 {
    34   RTEMS_COMPILER_MEMORY_BARRIER();
    35 
    36   return *addr;
    37 }
    38 
    3925/* FIXME: Add barrier to Score */
    4026
    4127typedef struct {
    42         int value;
    43         int sense;
    44   SMP_lock_Control lock;
     28        Atomic_Uint value;
     29        Atomic_Uint sense;
    4530} barrier_control;
    4631
    4732typedef struct {
    48         int sense;
     33        unsigned int sense;
    4934} barrier_state;
    5035
    51 #define BARRIER_CONTROL_INITIALIZER { 0, 0, SMP_LOCK_INITIALIZER }
     36#define BARRIER_CONTROL_INITIALIZER \
     37  { ATOMIC_INITIALIZER_UINT(0), ATOMIC_INITIALIZER_UINT(0) }
    5238
    5339#define BARRIER_STATE_INITIALIZER { 0 }
     
    5642  barrier_control *control,
    5743  barrier_state *state,
    58   int cpu_count
    59 )
    60 {
    61   int sense = ~state->sense;
    62   int value;
     44  unsigned int cpu_count
     45)
     46{
     47  unsigned int sense = ~state->sense;
     48  unsigned int value;
    6349
    6450  state->sense = sense;
    6551
    66   _SMP_lock_Acquire(&control->lock);
    67   value = control->value;
    68   ++value;
    69   control->value = value;
    70   _SMP_lock_Release(&control->lock);
    71 
    72   if (value == cpu_count) {
    73     atomic_store(&control->value, 0);
    74     atomic_store(&control->sense, sense);
    75   }
    76 
    77   while (atomic_load(&control->sense) != sense) {
    78     /* Wait */
     52  value = _Atomic_Fetch_add_uint(&control->value, 1, ATOMIC_ORDER_RELAXED);
     53
     54  if (value + 1 == cpu_count) {
     55    _Atomic_Store_uint(&control->value, 0, ATOMIC_ORDER_RELAXED);
     56    _Atomic_Store_uint(&control->sense, sense, ATOMIC_ORDER_RELEASE);
     57  } else {
     58    while (_Atomic_Load_uint(&control->sense, ATOMIC_ORDER_ACQUIRE) != sense) {
     59      /* Wait */
     60    }
    7961  }
    8062}
     
    9375
    9476typedef struct {
    95   int state;
     77  Atomic_Uint state;
    9678  barrier_control barrier;
    9779  rtems_id timer_id;
     
    10385
    10486static global_context context = {
    105   .state = INITIAL,
     87  .state = ATOMIC_INITIALIZER_UINT(INITIAL),
    10688  .barrier = BARRIER_CONTROL_INITIALIZER,
    10789  .lock = SMP_LOCK_INITIALIZER
     
    120102  global_context *ctx = arg;
    121103
    122   atomic_store(&ctx->state, STOP_TEST);
     104  _Atomic_Store_uint(&ctx->state, STOP_TEST, ATOMIC_ORDER_RELEASE);
    123105}
    124106
    125107static void wait_for_state(global_context *ctx, int desired_state)
    126108{
    127   while (atomic_load(&ctx->state) != desired_state) {
     109  while (
     110    _Atomic_Load_uint(&ctx->state, ATOMIC_ORDER_ACQUIRE) != desired_state
     111  ) {
    128112    /* Wait */
    129113  }
     
    132116static bool assert_state(global_context *ctx, int desired_state)
    133117{
    134   return atomic_load(&ctx->state) == desired_state;
     118  return _Atomic_Load_uint(&ctx->state, ATOMIC_ORDER_RELAXED) == desired_state;
    135119}
    136120
     
    139123  global_context *ctx,
    140124  barrier_state *bs,
    141   int cpu_count,
    142   int cpu_self
     125  unsigned int cpu_count,
     126  unsigned int cpu_self
    143127);
    144128
     
    147131  global_context *ctx,
    148132  barrier_state *bs,
    149   int cpu_count,
    150   int cpu_self
     133  unsigned int cpu_count,
     134  unsigned int cpu_self
    151135)
    152136{
     
    166150  global_context *ctx,
    167151  barrier_state *bs,
    168   int cpu_count,
    169   int cpu_self
     152  unsigned int cpu_count,
     153  unsigned int cpu_self
    170154)
    171155{
     
    186170  global_context *ctx,
    187171  barrier_state *bs,
    188   int cpu_count,
    189   int cpu_self
     172  unsigned int cpu_count,
     173  unsigned int cpu_self
    190174)
    191175{
     
    206190  global_context *ctx,
    207191  barrier_state *bs,
    208   int cpu_count,
    209   int cpu_self
     192  unsigned int cpu_count,
     193  unsigned int cpu_self
    210194)
    211195{
     
    239223  global_context *ctx,
    240224  barrier_state *bs,
    241   int cpu_count,
    242   int cpu_self
     225  unsigned int cpu_count,
     226  unsigned int cpu_self
    243227)
    244228{
     
    266250  global_context *ctx,
    267251  barrier_state *bs,
    268   int cpu_count,
    269   int cpu_self,
     252  unsigned int cpu_count,
     253  unsigned int cpu_self,
    270254  bool master
    271255)
     
    285269      rtems_test_assert(sc == RTEMS_SUCCESSFUL);
    286270
    287       atomic_store(&ctx->state, START_TEST);
     271      _Atomic_Store_uint(&ctx->state, START_TEST, ATOMIC_ORDER_RELEASE);
    288272    }
    289273
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