Index: c/src/lib/libcpu/mips/ChangeLog
===================================================================
--- c/src/lib/libcpu/mips/ChangeLog	(revision 549e88f62312dd972d0b1c9353999611404934bd)
+++ c/src/lib/libcpu/mips/ChangeLog	(revision 7c990076419ff4a80999dcc04985688cd5bea5ce)
@@ -1,6 +1,12 @@
+2006-06-08	Bruce Robinson <brucer@pmccorp.com>
+
+	* Makefile.am: add interruptmask.c
+	* shared/interrupts/interuptmask.c: TX49 conditional mask computation
+	* shared/interrupts/vectorexceptions.c: Corrections to exception codes 
+	   & descriptions
+
 2006-05-16	Ralf CorsÃ©pius <ralf.corsepius@rtems.org>
 
 	* configure.ac: Use RTEMS_AMPOLISH3.
-
 2006-04-02	Ralf CorsÃ©pius <ralf.corsepius@rtems.org>
 
Index: c/src/lib/libcpu/mips/Makefile.am
===================================================================
--- c/src/lib/libcpu/mips/Makefile.am	(revision 549e88f62312dd972d0b1c9353999611404934bd)
+++ c/src/lib/libcpu/mips/Makefile.am	(revision 7c990076419ff4a80999dcc04985688cd5bea5ce)
@@ -42,5 +42,6 @@
 noinst_PROGRAMS += shared/interrupts.rel
 shared_interrupts_rel_SOURCES = shared/interrupts/installisrentries.c \
-    shared/interrupts/vectorexceptions.c shared/interrupts/isr_entries.S
+    shared/interrupts/vectorexceptions.c shared/interrupts/interruptmask.c \
+    shared/interrupts/isr_entries.S
 shared_interrupts_rel_CPPFLAGS = $(AM_CPPFLAGS) $(interrupts_CPPFLAGS)
 shared_interrupts_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
Index: c/src/lib/libcpu/mips/shared/interrupts/interruptmask.c
===================================================================
--- c/src/lib/libcpu/mips/shared/interrupts/interruptmask.c	(revision 7c990076419ff4a80999dcc04985688cd5bea5ce)
+++ c/src/lib/libcpu/mips/shared/interrupts/interruptmask.c	(revision 7c990076419ff4a80999dcc04985688cd5bea5ce)
@@ -0,0 +1,24 @@
+/*
+ *  $Id: interruptmask.c,v 1.0 2006/04/04 05:18:49
+ */
+
+#include <rtems.h>
+
+/*
+ *  This function returns a mask value which is used to select the bits
+ *  in the processor status register that can be set to enable interrupts.
+ *  The mask value should not include the 2 software interrupt enable bits.
+ */
+
+uint32_t mips_interrupt_mask( void )
+{
+	uint32_t interrupt_mask;
+
+#ifdef TX49
+	interrupt_mask = 0x00000400;			/* Toshiba TX49 processors have a non-standard interrupt mask */
+#else
+	interrupt_mask = 0x0000fc00;
+#endif
+
+	return(interrupt_mask);
+}
Index: c/src/lib/libcpu/mips/shared/interrupts/vectorexceptions.c
===================================================================
--- c/src/lib/libcpu/mips/shared/interrupts/vectorexceptions.c	(revision 549e88f62312dd972d0b1c9353999611404934bd)
+++ c/src/lib/libcpu/mips/shared/interrupts/vectorexceptions.c	(revision 7c990076419ff4a80999dcc04985688cd5bea5ce)
@@ -25,15 +25,16 @@
   /*  6 */ "Instruction Bus Error",
   /*  7 */ "Data Bus Error",
-  /*  9 */ "Syscall",
-  /* 10 */ "Breakpoint",
-  /* 11 */ "Reserved Instruction",
-  /* 12 */ "Coprocessor Unuseable",
-  /* 13 */ "Overflow",
-  /* 14 */ "Trap",
-  /* 15 */ "Instruction Virtual Coherency Error",
-  /* 16 */ "FP Exception",
+  /*  8 */ "Syscall",
+  /*  9 */ "Breakpoint",
+  /* 10 */ "Reserved Instruction",
+  /* 11 */ "Coprocessor Unuseable",
+  /* 12 */ "Overflow",
+  /* 13 */ "Trap",
+  /* 14 */ "Instruction Virtual Coherency Error",
+  /* 15 */ "FP Exception",
+  /* 16 */ "Reserved 16",
   /* 17 */ "Reserved 17",
-  /* 18 */ "Reserved 17",
-  /* 19 */ "Reserved 17",
+  /* 18 */ "Reserved 18",
+  /* 19 */ "Reserved 19",
   /* 20 */ "Reserved 20",
   /* 21 */ "Reserved 21",
Index: cpukit/score/cpu/mips/ChangeLog
===================================================================
--- cpukit/score/cpu/mips/ChangeLog	(revision 549e88f62312dd972d0b1c9353999611404934bd)
+++ cpukit/score/cpu/mips/ChangeLog	(revision 7c990076419ff4a80999dcc04985688cd5bea5ce)
@@ -1,2 +1,10 @@
+2006-06-08 Bruce Robinson <brucer@pmccorp.com>
+
+	* cpu.c: Add int64 types for __mips==3 cpus, incorporate 
+	   mips_interrupt_mask() into mask computations
+	* cpu_asm.S: Add int64 register save/restores for __mips==3 cpus.  Adjustment 
+	   of mips1 vs mips3 macros.
+	* cpu.h: Add int64 types for __mips==3 cpus.
+	
 2006-03-17	Ralf Corsepius <ralf.corsepius@rtems.org>
 
Index: cpukit/score/cpu/mips/cpu.c
===================================================================
--- cpukit/score/cpu/mips/cpu.c	(revision 549e88f62312dd972d0b1c9353999611404934bd)
+++ cpukit/score/cpu/mips/cpu.c	(revision 7c990076419ff4a80999dcc04985688cd5bea5ce)
@@ -51,9 +51,16 @@
 
 /* 
-** local dword used in cpu_asm to pass the exception stack frame to the
-** context switch code.
+** Exception stack frame pointer used in cpu_asm to pass the exception stack frame 
+** address to the context switch code.
 */
-unsigned __exceptionStackFrame = 0; 
-
+#if (__mips == 1)
+typedef uint32_t ESF_PTR_TYPE;
+#elif (__mips == 3)
+typedef uint64_t ESF_PTR_TYPE;
+#else
+#error "unknown MIPS ISA"
+#endif
+
+ESF_PTR_TYPE __exceptionStackFrame = 0; 
 
 
@@ -108,9 +115,9 @@
 #if (__mips == 3) || (__mips == 32)
 /* IE bit and shift down hardware ints into bits 1 thru 6 */
-  sr = (sr & SR_IE) | ((sr & 0xfc00) >> 9);
+  sr = (sr & SR_IE) | ((sr & mips_interrupt_mask()) >> 9);
 
 #elif __mips == 1
 /* IEC bit and shift down hardware ints into bits 1 thru 6 */
-  sr = (sr & SR_IEC) | ((sr & 0xfc00) >> 9);
+  sr = (sr & SR_IEC) | ((sr & mips_interrupt_mask()) >> 9);
 
 #else
@@ -143,6 +150,6 @@
    srbits = sr & ~(0xfc00 | SR_IE);
 
-   sr = srbits | ((new_level==0)? (0xfc00 | SR_IE): \
-		 (((new_level<<9) & 0xfc00) | \
+   sr = srbits | ((new_level==0)? (mips_interrupt_mask() | SR_IE): \
+		 (((new_level<<9) & mips_interrupt_mask()) | \
                    ((new_level & 1)?SR_IE:0)));
 /*
Index: cpukit/score/cpu/mips/cpu_asm.S
===================================================================
--- cpukit/score/cpu/mips/cpu_asm.S	(revision 549e88f62312dd972d0b1c9353999611404934bd)
+++ cpukit/score/cpu/mips/cpu_asm.S	(revision 7c990076419ff4a80999dcc04985688cd5bea5ce)
@@ -93,16 +93,18 @@
 /* 64 bit register operations */
 #define NOP	nop
-/*
 #define ADD	dadd
-#define MFCO	dmfc0
-#define MTCO	dmtc0
-*/
-#define ADD	add	
-#define MFCO	mfc0
-#define MTCO	mtc0
 #define STREG	sd
 #define LDREG	ld
+#define MFCO	dmfc0		/* Only use this op for coprocessor registers that are 64 bit in R4000 architecture */
+#define MTCO	dmtc0		/* Only use this op for coprocessor registers that are 64 bit in R4000 architecture */
 #define ADDU	addu
 #define ADDIU	addiu
+#if (__mips_fpr==32)
+#define STREGC1	swc1
+#define LDREGC1	lwc1
+#elif (__mips_fpr==64)		/* Use these instructions if there are 64 bit floating point registers. This requires FR bit to be set in C0_SR */
+#define STREGC1	sdc1
+#define LDREGC1	ldc1
+#endif
 #define R_SZ	8
 #define F_SZ	8
@@ -122,4 +124,6 @@
 #define ADDU	add
 #define ADDIU	addi
+#define STREGC1	swc1
+#define LDREGC1	lwc1
 #define R_SZ	4
 #define F_SZ	4
@@ -224,10 +228,10 @@
 	** integer task is switching out with a FP task switching in.
 	*/
-	MFC0	t0,C0_SR
+	mfc0	t0,C0_SR
 	li	t2,SR_CU1	
 	move	t1,t0
 	or	t0,t2		/* turn on the fpu */
-#if __mips == 3
-	li	t2,SR_EXL | SR_IE
+#if (__mips == 3) || (__mips == 32)
+	li	t2,SR_IE
 #elif __mips == 1
 	li	t2,SR_IEC
@@ -235,7 +239,7 @@
 	not	t2
 	and	t0,t2		/* turn off interrupts */	
-	MTC0	t0,C0_SR	
-		
-	ld	a1,(a0)
+	mtc0	t0,C0_SR
+	
+	lw	a1,(a0)		/* get address of context storage area */
 	move	t0,ra
 	jal	_CPU_Context_save_fp_from_exception
@@ -245,42 +249,42 @@
 	** Reassert the task's state because we've not saved it yet.
 	*/
-	MTC0	t1,C0_SR	
-	j	t0	
+	mtc0	t1,C0_SR
+	j	t0
 	NOP
 	
 	.globl _CPU_Context_save_fp_from_exception
 _CPU_Context_save_fp_from_exception:
-        swc1 $f0,FP0_OFFSET*F_SZ(a1)
-        swc1 $f1,FP1_OFFSET*F_SZ(a1)
-        swc1 $f2,FP2_OFFSET*F_SZ(a1)
-        swc1 $f3,FP3_OFFSET*F_SZ(a1)
-        swc1 $f4,FP4_OFFSET*F_SZ(a1)
-        swc1 $f5,FP5_OFFSET*F_SZ(a1)
-        swc1 $f6,FP6_OFFSET*F_SZ(a1)
-        swc1 $f7,FP7_OFFSET*F_SZ(a1)
-        swc1 $f8,FP8_OFFSET*F_SZ(a1)
-        swc1 $f9,FP9_OFFSET*F_SZ(a1)
-        swc1 $f10,FP10_OFFSET*F_SZ(a1)
-        swc1 $f11,FP11_OFFSET*F_SZ(a1)
-        swc1 $f12,FP12_OFFSET*F_SZ(a1)
-        swc1 $f13,FP13_OFFSET*F_SZ(a1)
-        swc1 $f14,FP14_OFFSET*F_SZ(a1)
-        swc1 $f15,FP15_OFFSET*F_SZ(a1)
-        swc1 $f16,FP16_OFFSET*F_SZ(a1)
-        swc1 $f17,FP17_OFFSET*F_SZ(a1)
-        swc1 $f18,FP18_OFFSET*F_SZ(a1)
-        swc1 $f19,FP19_OFFSET*F_SZ(a1)
-        swc1 $f20,FP20_OFFSET*F_SZ(a1)
-        swc1 $f21,FP21_OFFSET*F_SZ(a1)
-        swc1 $f22,FP22_OFFSET*F_SZ(a1)
-        swc1 $f23,FP23_OFFSET*F_SZ(a1)
-        swc1 $f24,FP24_OFFSET*F_SZ(a1)
-        swc1 $f25,FP25_OFFSET*F_SZ(a1)
-        swc1 $f26,FP26_OFFSET*F_SZ(a1)
-        swc1 $f27,FP27_OFFSET*F_SZ(a1)
-        swc1 $f28,FP28_OFFSET*F_SZ(a1)
-        swc1 $f29,FP29_OFFSET*F_SZ(a1)
-        swc1 $f30,FP30_OFFSET*F_SZ(a1)
-        swc1 $f31,FP31_OFFSET*F_SZ(a1)
+        STREGC1 $f0,FP0_OFFSET*F_SZ(a1)
+        STREGC1 $f1,FP1_OFFSET*F_SZ(a1)
+        STREGC1 $f2,FP2_OFFSET*F_SZ(a1)
+        STREGC1 $f3,FP3_OFFSET*F_SZ(a1)
+        STREGC1 $f4,FP4_OFFSET*F_SZ(a1)
+        STREGC1 $f5,FP5_OFFSET*F_SZ(a1)
+        STREGC1 $f6,FP6_OFFSET*F_SZ(a1)
+        STREGC1 $f7,FP7_OFFSET*F_SZ(a1)
+        STREGC1 $f8,FP8_OFFSET*F_SZ(a1)
+        STREGC1 $f9,FP9_OFFSET*F_SZ(a1)
+        STREGC1 $f10,FP10_OFFSET*F_SZ(a1)
+        STREGC1 $f11,FP11_OFFSET*F_SZ(a1)
+        STREGC1 $f12,FP12_OFFSET*F_SZ(a1)
+        STREGC1 $f13,FP13_OFFSET*F_SZ(a1)
+        STREGC1 $f14,FP14_OFFSET*F_SZ(a1)
+        STREGC1 $f15,FP15_OFFSET*F_SZ(a1)
+        STREGC1 $f16,FP16_OFFSET*F_SZ(a1)
+        STREGC1 $f17,FP17_OFFSET*F_SZ(a1)
+        STREGC1 $f18,FP18_OFFSET*F_SZ(a1)
+        STREGC1 $f19,FP19_OFFSET*F_SZ(a1)
+        STREGC1 $f20,FP20_OFFSET*F_SZ(a1)
+        STREGC1 $f21,FP21_OFFSET*F_SZ(a1)
+        STREGC1 $f22,FP22_OFFSET*F_SZ(a1)
+        STREGC1 $f23,FP23_OFFSET*F_SZ(a1)
+        STREGC1 $f24,FP24_OFFSET*F_SZ(a1)
+        STREGC1 $f25,FP25_OFFSET*F_SZ(a1)
+        STREGC1 $f26,FP26_OFFSET*F_SZ(a1)
+        STREGC1 $f27,FP27_OFFSET*F_SZ(a1)
+        STREGC1 $f28,FP28_OFFSET*F_SZ(a1)
+        STREGC1 $f29,FP29_OFFSET*F_SZ(a1)
+        STREGC1 $f30,FP30_OFFSET*F_SZ(a1)
+        STREGC1 $f31,FP31_OFFSET*F_SZ(a1)
         cfc1 a0,$31                    /* Read FP status/conrol reg */
         cfc1 a0,$31                    /* Two reads clear pipeline */
@@ -323,10 +327,10 @@
 	** integer task is switching out with a FP task switching in.
 	*/
-	MFC0	t0,C0_SR
+	mfc0	t0,C0_SR
 	li	t2,SR_CU1	
 	move	t1,t0
 	or	t0,t2		/* turn on the fpu */
-#if __mips == 3
-	li	t2,SR_EXL | SR_IE
+#if (__mips == 3) || (__mips == 32)
+	li	t2,SR_IE
 #elif __mips == 1
 	li	t2,SR_IEC
@@ -334,7 +338,7 @@
 	not	t2
 	and	t0,t2		/* turn off interrupts */	
-	MTC0	t0,C0_SR	
-
-	ld	a1,(a0)
+	mtc0	t0,C0_SR
+	
+	lw	a1,(a0)		/* get address of context storage area */
 	move	t0,ra
 	jal	_CPU_Context_restore_fp_from_exception
@@ -345,5 +349,5 @@
 	** new one yet.
 	*/
-	MTC0	t1,C0_SR	
+	mtc0	t1,C0_SR
 	j	t0
 	NOP
@@ -351,41 +355,41 @@
 	.globl _CPU_Context_restore_fp_from_exception
 _CPU_Context_restore_fp_from_exception:
-        lwc1 $f0,FP0_OFFSET*4(a1)
-        lwc1 $f1,FP1_OFFSET*4(a1)
-        lwc1 $f2,FP2_OFFSET*4(a1)
-        lwc1 $f3,FP3_OFFSET*4(a1)
-        lwc1 $f4,FP4_OFFSET*4(a1)
-        lwc1 $f5,FP5_OFFSET*4(a1)
-        lwc1 $f6,FP6_OFFSET*4(a1)
-        lwc1 $f7,FP7_OFFSET*4(a1)
-        lwc1 $f8,FP8_OFFSET*4(a1)
-        lwc1 $f9,FP9_OFFSET*4(a1)
-        lwc1 $f10,FP10_OFFSET*4(a1)
-        lwc1 $f11,FP11_OFFSET*4(a1)
-        lwc1 $f12,FP12_OFFSET*4(a1)
-        lwc1 $f13,FP13_OFFSET*4(a1)
-        lwc1 $f14,FP14_OFFSET*4(a1)
-        lwc1 $f15,FP15_OFFSET*4(a1)
-        lwc1 $f16,FP16_OFFSET*4(a1)
-        lwc1 $f17,FP17_OFFSET*4(a1)
-        lwc1 $f18,FP18_OFFSET*4(a1)
-        lwc1 $f19,FP19_OFFSET*4(a1)
-        lwc1 $f20,FP20_OFFSET*4(a1)
-        lwc1 $f21,FP21_OFFSET*4(a1)
-        lwc1 $f22,FP22_OFFSET*4(a1)
-        lwc1 $f23,FP23_OFFSET*4(a1)
-        lwc1 $f24,FP24_OFFSET*4(a1)
-        lwc1 $f25,FP25_OFFSET*4(a1)
-        lwc1 $f26,FP26_OFFSET*4(a1)
-        lwc1 $f27,FP27_OFFSET*4(a1)
-        lwc1 $f28,FP28_OFFSET*4(a1)
-        lwc1 $f29,FP29_OFFSET*4(a1)
-        lwc1 $f30,FP30_OFFSET*4(a1)
-        lwc1 $f31,FP31_OFFSET*4(a1)
+        LDREGC1 $f0,FP0_OFFSET*F_SZ(a1)
+        LDREGC1 $f1,FP1_OFFSET*F_SZ(a1)
+        LDREGC1 $f2,FP2_OFFSET*F_SZ(a1)
+        LDREGC1 $f3,FP3_OFFSET*F_SZ(a1)
+        LDREGC1 $f4,FP4_OFFSET*F_SZ(a1)
+        LDREGC1 $f5,FP5_OFFSET*F_SZ(a1)
+        LDREGC1 $f6,FP6_OFFSET*F_SZ(a1)
+        LDREGC1 $f7,FP7_OFFSET*F_SZ(a1)
+        LDREGC1 $f8,FP8_OFFSET*F_SZ(a1)
+        LDREGC1 $f9,FP9_OFFSET*F_SZ(a1)
+        LDREGC1 $f10,FP10_OFFSET*F_SZ(a1)
+        LDREGC1 $f11,FP11_OFFSET*F_SZ(a1)
+        LDREGC1 $f12,FP12_OFFSET*F_SZ(a1)
+        LDREGC1 $f13,FP13_OFFSET*F_SZ(a1)
+        LDREGC1 $f14,FP14_OFFSET*F_SZ(a1)
+        LDREGC1 $f15,FP15_OFFSET*F_SZ(a1)
+        LDREGC1 $f16,FP16_OFFSET*F_SZ(a1)
+        LDREGC1 $f17,FP17_OFFSET*F_SZ(a1)
+        LDREGC1 $f18,FP18_OFFSET*F_SZ(a1)
+        LDREGC1 $f19,FP19_OFFSET*F_SZ(a1)
+        LDREGC1 $f20,FP20_OFFSET*F_SZ(a1)
+        LDREGC1 $f21,FP21_OFFSET*F_SZ(a1)
+        LDREGC1 $f22,FP22_OFFSET*F_SZ(a1)
+        LDREGC1 $f23,FP23_OFFSET*F_SZ(a1)
+        LDREGC1 $f24,FP24_OFFSET*F_SZ(a1)
+        LDREGC1 $f25,FP25_OFFSET*F_SZ(a1)
+        LDREGC1 $f26,FP26_OFFSET*F_SZ(a1)
+        LDREGC1 $f27,FP27_OFFSET*F_SZ(a1)
+        LDREGC1 $f28,FP28_OFFSET*F_SZ(a1)
+        LDREGC1 $f29,FP29_OFFSET*F_SZ(a1)
+        LDREGC1 $f30,FP30_OFFSET*F_SZ(a1)
+        LDREGC1 $f31,FP31_OFFSET*F_SZ(a1)
         cfc1 a0,$31                  /* Read from FP status/control reg */
         cfc1 a0,$31                  /* Two reads clear pipeline */
         NOP                          /* NOPs ensure execution */
         NOP
-        lw a0,FPCS_OFFSET*4(a1)      /* Load saved FPCS value */
+        lw a0,FPCS_OFFSET*F_SZ(a1)   /* Load saved FPCS value */
         NOP
         ctc1 a0,$31                  /* Restore FPCS register */
@@ -411,5 +415,5 @@
         .set noreorder
 
-        MFC0	t0,C0_SR
+        mfc0	t0,C0_SR
 #if (__mips == 3) || (__mips == 32)
 	li	t1,SR_IE
@@ -420,5 +424,5 @@
 	not	t1
         and	t0,t1				/* mask off interrupts while we context switch */
-        MTC0	t0,C0_SR
+        mtc0	t0,C0_SR
 	NOP
 
@@ -456,7 +460,7 @@
 	LDREG	t0,R_EPC*R_SZ(t1)		/* get the userspace EPC from the frame */
 	b	2f
-	nop
+	NOP
 		
-1:	la    t0,_Thread_Dispatch		/* if ==0, we're switched out */
+1:	la      t0,_Thread_Dispatch		/* if ==0, we're switched out */
 
 2:	STREG   t0,C0_EPC_OFFSET*R_SZ(a0)
@@ -479,5 +483,5 @@
 	
 /*	NOP */
-/*#if __mips == 3 */
+/*#if (__mips == 3) || (__mips == 32) */
 /*        andi  t0,SR_EXL */
 /*        bnez  t0,_CPU_Context_1 */   /* set exception level from restore context */
@@ -531,5 +535,5 @@
 	** Save IE
 	*/
-	or	t2, SR_IE
+	or	t2,SR_IE
 #elif __mips == 1
 	/* 
@@ -544,9 +548,9 @@
 	and	t0,t2		/* keep only the per-task bits */
 		
-	MFC0	t1,C0_SR	/* grab the current SR */
+	mfc0	t1,C0_SR	/* grab the current SR */
 	not	t2		
 	and	t1,t2		/* mask off the old task's per-task bits */
 	or	t1,t0		/* or in the new task's bits */
-        MTC0	t1,C0_SR	/* and load the new SR */
+        mtc0	t1,C0_SR	/* and load the new SR */
 	NOP
 	
@@ -579,9 +583,9 @@
 
 	
-ASM_EXTERN(_ISR_Nest_level, SZ_INT)
-ASM_EXTERN(_Thread_Dispatch_disable_level,SZ_INT)
-ASM_EXTERN(_Context_Switch_necessary,SZ_INT)
-ASM_EXTERN(_ISR_Signals_to_thread_executing,SZ_INT)
-ASM_EXTERN(_Thread_Executing,SZ_INT)
+ASM_EXTERN(_ISR_Nest_level,4)
+ASM_EXTERN(_Thread_Dispatch_disable_level,4)
+ASM_EXTERN(_Context_Switch_necessary,4)
+ASM_EXTERN(_ISR_Signals_to_thread_executing,4)
+ASM_EXTERN(_Thread_Executing,4)
 	
 .extern _Thread_Dispatch
@@ -649,5 +653,5 @@
 
         /* wastes a lot of stack space for context?? */
-        ADDIU    sp,sp,-EXCP_STACK_SIZE
+	ADDIU    sp,sp,-EXCP_STACK_SIZE
 
         STREG ra, R_RA*R_SZ(sp)  /* store ra on the stack */ 
@@ -679,9 +683,9 @@
         .set at
 
-        MFC0     t0,C0_SR
-	MFC0     t1,C0_EPC
+        mfc0     t0,C0_SR
+	MFCO     t1,C0_EPC
         STREG    t0,R_SR*R_SZ(sp)
         STREG    t1,R_EPC*R_SZ(sp)
-	
+
 
 #ifdef INSTRUMENT_EXECUTING_THREAD
@@ -690,8 +694,8 @@
 	sw t2, 0x8001FFF0
 #endif
-	
+
 	/* determine if an interrupt generated this exception */
 
-        MFC0     t0,C0_CAUSE
+        mfc0     t0,C0_CAUSE
 	NOP
 
@@ -726,7 +730,7 @@
 
 #if __mips == 1
-	MFC0	 t0,C0_TAR
-#endif
-        MFC0     t1,C0_BADVADDR
+	mfc0	 t0,C0_TAR
+#endif
+        MFCO     t1,C0_BADVADDR
 	
 #if __mips == 1
@@ -738,5 +742,5 @@
 	
 #if ( CPU_HARDWARE_FP == TRUE )
-        MFC0     t0,C0_SR                 /* we have a FPU, save state if enabled */
+        mfc0     t0,C0_SR                 /* FPU is enabled, save state */
 	NOP
         srl      t0,t0,16
@@ -748,6 +752,6 @@
         jal      _CPU_Context_save_fp_from_exception 
         NOP
-        MFC1     t0,C1_REVISION
-        MFC1     t1,C1_STATUS
+        mfc1     t0,C1_REVISION
+        mfc1     t1,C1_STATUS
         STREG    t0,R_FEIR*R_SZ(sp)
         STREG    t1,R_FCSR*R_SZ(sp)
@@ -830,5 +834,5 @@
 		
 #if ( CPU_HARDWARE_FP == TRUE )
-        MFC0     t0,C0_SR               /* FPU is present, restore state if enabled */
+        mfc0     t0,C0_SR               /* FPU is enabled, restore state */
 	NOP
         srl      t0,t0,16
@@ -842,6 +846,6 @@
         LDREG    t0,R_FEIR*R_SZ(sp)
         LDREG    t1,R_FCSR*R_SZ(sp)
-        MTC1     t0,C1_REVISION
-        MTC1     t1,C1_STATUS
+        mtc1     t0,C1_REVISION
+        mtc1     t1,C1_STATUS
 2:
 #endif
@@ -871,5 +875,5 @@
 _ISR_Handler_1:
 
-        MFC0     t1,C0_SR
+        mfc0     t1,C0_SR
         and      t0,CAUSE_IPMASK
         and      t0,t1
@@ -880,8 +884,7 @@
 	
 	beq      t0,zero,_ISR_Handler_exit
-	nop
-	
-	
-		
+	NOP
+
+	
   /*
    *  save some or all context on stack
@@ -894,18 +897,19 @@
    */
 
+
   /*
    *  _ISR_Nest_level++;
    */
-        LDREG  t0,_ISR_Nest_level
-	NOP
-        ADD    t0,t0,1
-        STREG  t0,_ISR_Nest_level
+        lw	t0,_ISR_Nest_level
+	NOP
+        add	t0,t0,1
+        sw	t0,_ISR_Nest_level
   /*
    *  _Thread_Dispatch_disable_level++;
    */
-        LDREG  t1,_Thread_Dispatch_disable_level
-	NOP
-        ADD    t1,t1,1
-        STREG  t1,_Thread_Dispatch_disable_level
+        lw	t1,_Thread_Dispatch_disable_level
+	NOP
+        add	t1,t1,1
+        sw	t1,_Thread_Dispatch_disable_level
 
   /*
@@ -913,5 +917,5 @@
    *  interrupt source and actually vector to device ISR handlers.
    */
-	
+
 #ifdef INSTRUMENT_ISR_VECTORING
 	NOP
@@ -923,5 +927,5 @@
         jal      mips_vector_isr_handlers
         NOP
-	
+
 #ifdef INSTRUMENT_ISR_VECTORING
 	li	t1, 0
@@ -929,19 +933,19 @@
 	NOP
 #endif
-		
+
   /*
    *  --_ISR_Nest_level;
    */
-        LDREG  t2,_ISR_Nest_level
-	NOP
-        ADD    t2,t2,-1
-        STREG  t2,_ISR_Nest_level
+        lw	t2,_ISR_Nest_level
+	NOP
+        add	t2,t2,-1
+        sw	t2,_ISR_Nest_level
   /*
    *  --_Thread_Dispatch_disable_level;
    */
-        LDREG  t1,_Thread_Dispatch_disable_level
-	NOP
-        ADD    t1,t1,-1
-        STREG  t1,_Thread_Dispatch_disable_level
+        lw	t1,_Thread_Dispatch_disable_level
+	NOP
+        add	t1,t1,-1
+        sw	t1,_Thread_Dispatch_disable_level
   /*
    *  if ( _Thread_Dispatch_disable_level || _ISR_Nest_level )
@@ -953,6 +957,4 @@
 
 
-
-	
   /*
    *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
@@ -963,9 +965,9 @@
    *    goto the label "exit interrupt (simple case)"
    */
-        LDREG t0,_Context_Switch_necessary
-        LDREG t1,_ISR_Signals_to_thread_executing
-	NOP
-        or    t0,t0,t1
-        beq   t0,zero,_ISR_Handler_exit
+        lw	t0,_Context_Switch_necessary
+        lw	t1,_ISR_Signals_to_thread_executing
+	NOP
+        or	t0,t0,t1
+        beq	t0,zero,_ISR_Handler_exit
         NOP
 
@@ -985,5 +987,5 @@
 */
 
-        MFC0    t0, C0_SR
+        mfc0    t0, C0_SR
 #if __mips == 1
 	
@@ -1002,5 +1004,5 @@
 	
 #endif
-        MTC0    t0, C0_SR
+        mtc0    t0, C0_SR
 	NOP
 
@@ -1024,5 +1026,5 @@
 ** a badly timed interrupt won't mess things up
 */
-        MFC0    t0, C0_SR
+        mfc0    t0, C0_SR
 
 #if __mips == 1
@@ -1032,35 +1034,34 @@
 	not	t1
 	and	t0, t1
-        MTC0    t0, C0_SR
+        mtc0    t0, C0_SR
  	NOP
 
- #elif (__mips == 3) || (__mips == 32)
-
- 	move	t2, t0
-	
-  /* make sure XL & IE are clear so ints are disabled & we can update EPC for the return */ 
-        li   t1,SR_EXL | SR_IE 
+#elif (__mips == 3) || (__mips == 32)
+
+	/* make sure EXL and IE are set so ints are disabled & we can update EPC for the return */ 
+        li   t1,SR_IE		/* Clear IE first (recommended) */
         not  t1 
         and  t0,t1 
-        MTC0 t0,C0_SR
+        mtc0 t0,C0_SR
   	NOP
   	
- 	/* store new EPC value, which we can do since XL=0 */
+ 	/* apply task's SR with EXL set so the eret will return properly */
+ 	or	t0, SR_EXL | SR_IE
+ 	mtc0    t0, C0_SR
+ 	NOP
+
+ 	/* store new EPC value, which we can do since EXL=0 */
         LDREG   t0, R_EPC*R_SZ(sp)
 	NOP
- 	MTC0	t0, C0_EPC
+ 	MTCO	t0, C0_EPC
  	NOP
  	
- 	/* apply task's SR with XL set so the eret will return properly */
- 	or	t2, SR_EXL
- 	MTC0	t2, C0_SR
- 	NOP
-#endif
- 
- 
- 
- 
- 
-	
+#endif
+
+
+
+
+
+
 #ifdef INSTRUMENT_EXECUTING_THREAD
 	lw	t0,_Thread_Executing
Index: cpukit/score/cpu/mips/rtems/score/cpu.h
===================================================================
--- cpukit/score/cpu/mips/rtems/score/cpu.h	(revision 549e88f62312dd972d0b1c9353999611404934bd)
+++ cpukit/score/cpu/mips/rtems/score/cpu.h	(revision 7c990076419ff4a80999dcc04985688cd5bea5ce)
@@ -443,5 +443,5 @@
     __MIPS_FPU_REGISTER_TYPE fp30;
     __MIPS_FPU_REGISTER_TYPE fp31;
-    __MIPS_FPU_REGISTER_TYPE fpcs;
+    uint32_t fpcs;
 #endif
 } Context_Control_fp;
@@ -768,4 +768,11 @@
 
 /*
+ *  Declare the function that is present in the shared libcpu directory,
+ *  that returns the processor dependent interrupt mask.
+ */
+
+uint32_t mips_interrupt_mask( void );
+
+/*
  *  Disable all interrupts for an RTEMS critical section.  The previous
  *  level is returned in _level.
@@ -873,10 +880,14 @@
 #if (__mips == 3) || (__mips == 32)
 #define _INTON	        SR_IE
+#if __mips_fpr==64
+#define _EXTRABITS      SR_FR
+#else
 #define _EXTRABITS      0
-#endif
+#endif /* __mips_fpr==64 */
+#endif /* __mips == 3 */
 #if __mips == 1
 #define _INTON          SR_IEC
 #define _EXTRABITS      0  /* make sure we're in user mode on MIPS1 processors */
-#endif
+#endif /* __mips == 1 */
 
 #define _CPU_Context_Initialize( _the_context, _stack_base, _size, _isr, _entry_point, _is_fp ) \
@@ -889,7 +900,6 @@
   	(_the_context)->fp = _stack_tmp; \
 	(_the_context)->ra = (__MIPS_REGISTER_TYPE)_entry_point; \
-	(_the_context)->c0_sr = ((_intlvl==0)?(0xFF00 | _INTON):( ((_intlvl<<9) & 0xfc00) | \
-						       0x300 | \
-						       ((_intlvl & 1)?_INTON:0)) ) | \
+	(_the_context)->c0_sr = ((_intlvl==0)?(mips_interrupt_mask() | 0x300 | _INTON): \
+		( ((_intlvl<<9) & mips_interrupt_mask()) | 0x300 | ((_intlvl & 1)?_INTON:0)) ) | \
 				SR_CU0 | ((_is_fp)?SR_CU1:0) | _EXTRABITS; \
   }
Index: make/ChangeLog
===================================================================
--- make/ChangeLog	(revision 549e88f62312dd972d0b1c9353999611404934bd)
+++ make/ChangeLog	(revision 7c990076419ff4a80999dcc04985688cd5bea5ce)
@@ -1,5 +1,10 @@
+2006-06-08	Bruce Robinson <brucer@pmccorp.com>
+	
+        * custom/rbtx4925.cfg:  Fix CPU_CFLAGS defines.
+	* custom/rbtx4938.cfg:  Fix CPU_CFLAGS defines.
+
 2005-04-10	Eric Norum <norume@aps.anl.gov>
 
-    *  custom/uC5282.cfg: Keep frame pointer -- gdb is much more useful.
+        *  custom/uC5282.cfg: Keep frame pointer -- gdb is much more useful.
 
 2006-03-16	Ralf Corsepius <ralf.corsepius@rtems.org>
Index: make/custom/rbtx4925.cfg
===================================================================
--- make/custom/rbtx4925.cfg	(revision 549e88f62312dd972d0b1c9353999611404934bd)
+++ make/custom/rbtx4925.cfg	(revision 7c990076419ff4a80999dcc04985688cd5bea5ce)
@@ -14,5 +14,5 @@
 #  This contains the compiler options necessary to select the CPU model
 #  and (hopefully) optimize for it. 
-CPU_CFLAGS = -mips3 -G0 -EL -DCPU_TX49
+CPU_CFLAGS = -mips3 -G0 -EL
 
 # optimize flag: typically -0, could use -O4 or -fast
Index: make/custom/rbtx4938.cfg
===================================================================
--- make/custom/rbtx4938.cfg	(revision 549e88f62312dd972d0b1c9353999611404934bd)
+++ make/custom/rbtx4938.cfg	(revision 7c990076419ff4a80999dcc04985688cd5bea5ce)
@@ -14,5 +14,5 @@
 #  This contains the compiler options necessary to select the CPU model
 #  and (hopefully) optimize for it. 
-CPU_CFLAGS = -mips3 -G0 -EL -DCPU_TX49
+CPU_CFLAGS = -mips3 -G0 -EL
 
 # optimize flag: typically -0, could use -O4 or -fast
