Changeset 7c99007 in rtems


Ignore:
Timestamp:
Jun 8, 2006, 6:03:55 PM (14 years ago)
Author:
Greg Menke <gregory.menke@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
0243b0d
Parents:
549e88f
Message:

B.Robinson MIPS patch

Files:
1 added
10 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/mips/ChangeLog

    r549e88f r7c99007  
     12006-06-08      Bruce Robinson <brucer@pmccorp.com>
     2
     3        * Makefile.am: add interruptmask.c
     4        * shared/interrupts/interuptmask.c: TX49 conditional mask computation
     5        * shared/interrupts/vectorexceptions.c: Corrections to exception codes
     6           & descriptions
     7
    182006-05-16      Ralf Corsépius <ralf.corsepius@rtems.org>
    29
    310        * configure.ac: Use RTEMS_AMPOLISH3.
    4 
    5112006-04-02      Ralf Corsépius <ralf.corsepius@rtems.org>
    612
  • c/src/lib/libcpu/mips/Makefile.am

    r549e88f r7c99007  
    4242noinst_PROGRAMS += shared/interrupts.rel
    4343shared_interrupts_rel_SOURCES = shared/interrupts/installisrentries.c \
    44     shared/interrupts/vectorexceptions.c shared/interrupts/isr_entries.S
     44    shared/interrupts/vectorexceptions.c shared/interrupts/interruptmask.c \
     45    shared/interrupts/isr_entries.S
    4546shared_interrupts_rel_CPPFLAGS = $(AM_CPPFLAGS) $(interrupts_CPPFLAGS)
    4647shared_interrupts_rel_LDFLAGS = $(RTEMS_RELLDFLAGS)
  • c/src/lib/libcpu/mips/shared/interrupts/vectorexceptions.c

    r549e88f r7c99007  
    2525  /*  6 */ "Instruction Bus Error",
    2626  /*  7 */ "Data Bus Error",
    27   /*  9 */ "Syscall",
    28   /* 10 */ "Breakpoint",
    29   /* 11 */ "Reserved Instruction",
    30   /* 12 */ "Coprocessor Unuseable",
    31   /* 13 */ "Overflow",
    32   /* 14 */ "Trap",
    33   /* 15 */ "Instruction Virtual Coherency Error",
    34   /* 16 */ "FP Exception",
     27  /*  8 */ "Syscall",
     28  /*  9 */ "Breakpoint",
     29  /* 10 */ "Reserved Instruction",
     30  /* 11 */ "Coprocessor Unuseable",
     31  /* 12 */ "Overflow",
     32  /* 13 */ "Trap",
     33  /* 14 */ "Instruction Virtual Coherency Error",
     34  /* 15 */ "FP Exception",
     35  /* 16 */ "Reserved 16",
    3536  /* 17 */ "Reserved 17",
    36   /* 18 */ "Reserved 17",
    37   /* 19 */ "Reserved 17",
     37  /* 18 */ "Reserved 18",
     38  /* 19 */ "Reserved 19",
    3839  /* 20 */ "Reserved 20",
    3940  /* 21 */ "Reserved 21",
  • cpukit/score/cpu/mips/ChangeLog

    r549e88f r7c99007  
     12006-06-08 Bruce Robinson <brucer@pmccorp.com>
     2
     3        * cpu.c: Add int64 types for __mips==3 cpus, incorporate
     4           mips_interrupt_mask() into mask computations
     5        * cpu_asm.S: Add int64 register save/restores for __mips==3 cpus.  Adjustment
     6           of mips1 vs mips3 macros.
     7        * cpu.h: Add int64 types for __mips==3 cpus.
     8       
    192006-03-17      Ralf Corsepius <ralf.corsepius@rtems.org>
    210
  • cpukit/score/cpu/mips/cpu.c

    r549e88f r7c99007  
    5151
    5252/*
    53 ** local dword used in cpu_asm to pass the exception stack frame to the
    54 ** context switch code.
     53** Exception stack frame pointer used in cpu_asm to pass the exception stack frame
     54** address to the context switch code.
    5555*/
    56 unsigned __exceptionStackFrame = 0;
    57 
     56#if (__mips == 1)
     57typedef uint32_t ESF_PTR_TYPE;
     58#elif (__mips == 3)
     59typedef uint64_t ESF_PTR_TYPE;
     60#else
     61#error "unknown MIPS ISA"
     62#endif
     63
     64ESF_PTR_TYPE __exceptionStackFrame = 0;
    5865
    5966
     
    108115#if (__mips == 3) || (__mips == 32)
    109116/* IE bit and shift down hardware ints into bits 1 thru 6 */
    110   sr = (sr & SR_IE) | ((sr & 0xfc00) >> 9);
     117  sr = (sr & SR_IE) | ((sr & mips_interrupt_mask()) >> 9);
    111118
    112119#elif __mips == 1
    113120/* IEC bit and shift down hardware ints into bits 1 thru 6 */
    114   sr = (sr & SR_IEC) | ((sr & 0xfc00) >> 9);
     121  sr = (sr & SR_IEC) | ((sr & mips_interrupt_mask()) >> 9);
    115122
    116123#else
     
    143150   srbits = sr & ~(0xfc00 | SR_IE);
    144151
    145    sr = srbits | ((new_level==0)? (0xfc00 | SR_IE): \
    146                  (((new_level<<9) & 0xfc00) | \
     152   sr = srbits | ((new_level==0)? (mips_interrupt_mask() | SR_IE): \
     153                 (((new_level<<9) & mips_interrupt_mask()) | \
    147154                   ((new_level & 1)?SR_IE:0)));
    148155/*
  • cpukit/score/cpu/mips/cpu_asm.S

    r549e88f r7c99007  
    9393/* 64 bit register operations */
    9494#define NOP     nop
    95 /*
    9695#define ADD     dadd
    97 #define MFCO    dmfc0
    98 #define MTCO    dmtc0
    99 */
    100 #define ADD     add     
    101 #define MFCO    mfc0
    102 #define MTCO    mtc0
    10396#define STREG   sd
    10497#define LDREG   ld
     98#define MFCO    dmfc0           /* Only use this op for coprocessor registers that are 64 bit in R4000 architecture */
     99#define MTCO    dmtc0           /* Only use this op for coprocessor registers that are 64 bit in R4000 architecture */
    105100#define ADDU    addu
    106101#define ADDIU   addiu
     102#if (__mips_fpr==32)
     103#define STREGC1 swc1
     104#define LDREGC1 lwc1
     105#elif (__mips_fpr==64)          /* Use these instructions if there are 64 bit floating point registers. This requires FR bit to be set in C0_SR */
     106#define STREGC1 sdc1
     107#define LDREGC1 ldc1
     108#endif
    107109#define R_SZ    8
    108110#define F_SZ    8
     
    122124#define ADDU    add
    123125#define ADDIU   addi
     126#define STREGC1 swc1
     127#define LDREGC1 lwc1
    124128#define R_SZ    4
    125129#define F_SZ    4
     
    224228        ** integer task is switching out with a FP task switching in.
    225229        */
    226         MFC0    t0,C0_SR
     230        mfc0    t0,C0_SR
    227231        li      t2,SR_CU1       
    228232        move    t1,t0
    229233        or      t0,t2           /* turn on the fpu */
    230 #if __mips == 3
    231         li      t2,SR_EXL | SR_IE
     234#if (__mips == 3) || (__mips == 32)
     235        li      t2,SR_IE
    232236#elif __mips == 1
    233237        li      t2,SR_IEC
     
    235239        not     t2
    236240        and     t0,t2           /* turn off interrupts */       
    237         MTC0    t0,C0_SR       
    238                
    239         ld      a1,(a0)
     241        mtc0    t0,C0_SR
     242       
     243        lw      a1,(a0)         /* get address of context storage area */
    240244        move    t0,ra
    241245        jal     _CPU_Context_save_fp_from_exception
     
    245249        ** Reassert the task's state because we've not saved it yet.
    246250        */
    247         MTC0    t1,C0_SR       
    248         j       t0     
     251        mtc0    t1,C0_SR
     252        j       t0
    249253        NOP
    250254       
    251255        .globl _CPU_Context_save_fp_from_exception
    252256_CPU_Context_save_fp_from_exception:
    253         swc1 $f0,FP0_OFFSET*F_SZ(a1)
    254         swc1 $f1,FP1_OFFSET*F_SZ(a1)
    255         swc1 $f2,FP2_OFFSET*F_SZ(a1)
    256         swc1 $f3,FP3_OFFSET*F_SZ(a1)
    257         swc1 $f4,FP4_OFFSET*F_SZ(a1)
    258         swc1 $f5,FP5_OFFSET*F_SZ(a1)
    259         swc1 $f6,FP6_OFFSET*F_SZ(a1)
    260         swc1 $f7,FP7_OFFSET*F_SZ(a1)
    261         swc1 $f8,FP8_OFFSET*F_SZ(a1)
    262         swc1 $f9,FP9_OFFSET*F_SZ(a1)
    263         swc1 $f10,FP10_OFFSET*F_SZ(a1)
    264         swc1 $f11,FP11_OFFSET*F_SZ(a1)
    265         swc1 $f12,FP12_OFFSET*F_SZ(a1)
    266         swc1 $f13,FP13_OFFSET*F_SZ(a1)
    267         swc1 $f14,FP14_OFFSET*F_SZ(a1)
    268         swc1 $f15,FP15_OFFSET*F_SZ(a1)
    269         swc1 $f16,FP16_OFFSET*F_SZ(a1)
    270         swc1 $f17,FP17_OFFSET*F_SZ(a1)
    271         swc1 $f18,FP18_OFFSET*F_SZ(a1)
    272         swc1 $f19,FP19_OFFSET*F_SZ(a1)
    273         swc1 $f20,FP20_OFFSET*F_SZ(a1)
    274         swc1 $f21,FP21_OFFSET*F_SZ(a1)
    275         swc1 $f22,FP22_OFFSET*F_SZ(a1)
    276         swc1 $f23,FP23_OFFSET*F_SZ(a1)
    277         swc1 $f24,FP24_OFFSET*F_SZ(a1)
    278         swc1 $f25,FP25_OFFSET*F_SZ(a1)
    279         swc1 $f26,FP26_OFFSET*F_SZ(a1)
    280         swc1 $f27,FP27_OFFSET*F_SZ(a1)
    281         swc1 $f28,FP28_OFFSET*F_SZ(a1)
    282         swc1 $f29,FP29_OFFSET*F_SZ(a1)
    283         swc1 $f30,FP30_OFFSET*F_SZ(a1)
    284         swc1 $f31,FP31_OFFSET*F_SZ(a1)
     257        STREGC1 $f0,FP0_OFFSET*F_SZ(a1)
     258        STREGC1 $f1,FP1_OFFSET*F_SZ(a1)
     259        STREGC1 $f2,FP2_OFFSET*F_SZ(a1)
     260        STREGC1 $f3,FP3_OFFSET*F_SZ(a1)
     261        STREGC1 $f4,FP4_OFFSET*F_SZ(a1)
     262        STREGC1 $f5,FP5_OFFSET*F_SZ(a1)
     263        STREGC1 $f6,FP6_OFFSET*F_SZ(a1)
     264        STREGC1 $f7,FP7_OFFSET*F_SZ(a1)
     265        STREGC1 $f8,FP8_OFFSET*F_SZ(a1)
     266        STREGC1 $f9,FP9_OFFSET*F_SZ(a1)
     267        STREGC1 $f10,FP10_OFFSET*F_SZ(a1)
     268        STREGC1 $f11,FP11_OFFSET*F_SZ(a1)
     269        STREGC1 $f12,FP12_OFFSET*F_SZ(a1)
     270        STREGC1 $f13,FP13_OFFSET*F_SZ(a1)
     271        STREGC1 $f14,FP14_OFFSET*F_SZ(a1)
     272        STREGC1 $f15,FP15_OFFSET*F_SZ(a1)
     273        STREGC1 $f16,FP16_OFFSET*F_SZ(a1)
     274        STREGC1 $f17,FP17_OFFSET*F_SZ(a1)
     275        STREGC1 $f18,FP18_OFFSET*F_SZ(a1)
     276        STREGC1 $f19,FP19_OFFSET*F_SZ(a1)
     277        STREGC1 $f20,FP20_OFFSET*F_SZ(a1)
     278        STREGC1 $f21,FP21_OFFSET*F_SZ(a1)
     279        STREGC1 $f22,FP22_OFFSET*F_SZ(a1)
     280        STREGC1 $f23,FP23_OFFSET*F_SZ(a1)
     281        STREGC1 $f24,FP24_OFFSET*F_SZ(a1)
     282        STREGC1 $f25,FP25_OFFSET*F_SZ(a1)
     283        STREGC1 $f26,FP26_OFFSET*F_SZ(a1)
     284        STREGC1 $f27,FP27_OFFSET*F_SZ(a1)
     285        STREGC1 $f28,FP28_OFFSET*F_SZ(a1)
     286        STREGC1 $f29,FP29_OFFSET*F_SZ(a1)
     287        STREGC1 $f30,FP30_OFFSET*F_SZ(a1)
     288        STREGC1 $f31,FP31_OFFSET*F_SZ(a1)
    285289        cfc1 a0,$31                    /* Read FP status/conrol reg */
    286290        cfc1 a0,$31                    /* Two reads clear pipeline */
     
    323327        ** integer task is switching out with a FP task switching in.
    324328        */
    325         MFC0    t0,C0_SR
     329        mfc0    t0,C0_SR
    326330        li      t2,SR_CU1       
    327331        move    t1,t0
    328332        or      t0,t2           /* turn on the fpu */
    329 #if __mips == 3
    330         li      t2,SR_EXL | SR_IE
     333#if (__mips == 3) || (__mips == 32)
     334        li      t2,SR_IE
    331335#elif __mips == 1
    332336        li      t2,SR_IEC
     
    334338        not     t2
    335339        and     t0,t2           /* turn off interrupts */       
    336         MTC0    t0,C0_SR       
    337 
    338         ld      a1,(a0)
     340        mtc0    t0,C0_SR
     341       
     342        lw      a1,(a0)         /* get address of context storage area */
    339343        move    t0,ra
    340344        jal     _CPU_Context_restore_fp_from_exception
     
    345349        ** new one yet.
    346350        */
    347         MTC0    t1,C0_SR       
     351        mtc0    t1,C0_SR
    348352        j       t0
    349353        NOP
     
    351355        .globl _CPU_Context_restore_fp_from_exception
    352356_CPU_Context_restore_fp_from_exception:
    353         lwc1 $f0,FP0_OFFSET*4(a1)
    354         lwc1 $f1,FP1_OFFSET*4(a1)
    355         lwc1 $f2,FP2_OFFSET*4(a1)
    356         lwc1 $f3,FP3_OFFSET*4(a1)
    357         lwc1 $f4,FP4_OFFSET*4(a1)
    358         lwc1 $f5,FP5_OFFSET*4(a1)
    359         lwc1 $f6,FP6_OFFSET*4(a1)
    360         lwc1 $f7,FP7_OFFSET*4(a1)
    361         lwc1 $f8,FP8_OFFSET*4(a1)
    362         lwc1 $f9,FP9_OFFSET*4(a1)
    363         lwc1 $f10,FP10_OFFSET*4(a1)
    364         lwc1 $f11,FP11_OFFSET*4(a1)
    365         lwc1 $f12,FP12_OFFSET*4(a1)
    366         lwc1 $f13,FP13_OFFSET*4(a1)
    367         lwc1 $f14,FP14_OFFSET*4(a1)
    368         lwc1 $f15,FP15_OFFSET*4(a1)
    369         lwc1 $f16,FP16_OFFSET*4(a1)
    370         lwc1 $f17,FP17_OFFSET*4(a1)
    371         lwc1 $f18,FP18_OFFSET*4(a1)
    372         lwc1 $f19,FP19_OFFSET*4(a1)
    373         lwc1 $f20,FP20_OFFSET*4(a1)
    374         lwc1 $f21,FP21_OFFSET*4(a1)
    375         lwc1 $f22,FP22_OFFSET*4(a1)
    376         lwc1 $f23,FP23_OFFSET*4(a1)
    377         lwc1 $f24,FP24_OFFSET*4(a1)
    378         lwc1 $f25,FP25_OFFSET*4(a1)
    379         lwc1 $f26,FP26_OFFSET*4(a1)
    380         lwc1 $f27,FP27_OFFSET*4(a1)
    381         lwc1 $f28,FP28_OFFSET*4(a1)
    382         lwc1 $f29,FP29_OFFSET*4(a1)
    383         lwc1 $f30,FP30_OFFSET*4(a1)
    384         lwc1 $f31,FP31_OFFSET*4(a1)
     357        LDREGC1 $f0,FP0_OFFSET*F_SZ(a1)
     358        LDREGC1 $f1,FP1_OFFSET*F_SZ(a1)
     359        LDREGC1 $f2,FP2_OFFSET*F_SZ(a1)
     360        LDREGC1 $f3,FP3_OFFSET*F_SZ(a1)
     361        LDREGC1 $f4,FP4_OFFSET*F_SZ(a1)
     362        LDREGC1 $f5,FP5_OFFSET*F_SZ(a1)
     363        LDREGC1 $f6,FP6_OFFSET*F_SZ(a1)
     364        LDREGC1 $f7,FP7_OFFSET*F_SZ(a1)
     365        LDREGC1 $f8,FP8_OFFSET*F_SZ(a1)
     366        LDREGC1 $f9,FP9_OFFSET*F_SZ(a1)
     367        LDREGC1 $f10,FP10_OFFSET*F_SZ(a1)
     368        LDREGC1 $f11,FP11_OFFSET*F_SZ(a1)
     369        LDREGC1 $f12,FP12_OFFSET*F_SZ(a1)
     370        LDREGC1 $f13,FP13_OFFSET*F_SZ(a1)
     371        LDREGC1 $f14,FP14_OFFSET*F_SZ(a1)
     372        LDREGC1 $f15,FP15_OFFSET*F_SZ(a1)
     373        LDREGC1 $f16,FP16_OFFSET*F_SZ(a1)
     374        LDREGC1 $f17,FP17_OFFSET*F_SZ(a1)
     375        LDREGC1 $f18,FP18_OFFSET*F_SZ(a1)
     376        LDREGC1 $f19,FP19_OFFSET*F_SZ(a1)
     377        LDREGC1 $f20,FP20_OFFSET*F_SZ(a1)
     378        LDREGC1 $f21,FP21_OFFSET*F_SZ(a1)
     379        LDREGC1 $f22,FP22_OFFSET*F_SZ(a1)
     380        LDREGC1 $f23,FP23_OFFSET*F_SZ(a1)
     381        LDREGC1 $f24,FP24_OFFSET*F_SZ(a1)
     382        LDREGC1 $f25,FP25_OFFSET*F_SZ(a1)
     383        LDREGC1 $f26,FP26_OFFSET*F_SZ(a1)
     384        LDREGC1 $f27,FP27_OFFSET*F_SZ(a1)
     385        LDREGC1 $f28,FP28_OFFSET*F_SZ(a1)
     386        LDREGC1 $f29,FP29_OFFSET*F_SZ(a1)
     387        LDREGC1 $f30,FP30_OFFSET*F_SZ(a1)
     388        LDREGC1 $f31,FP31_OFFSET*F_SZ(a1)
    385389        cfc1 a0,$31                  /* Read from FP status/control reg */
    386390        cfc1 a0,$31                  /* Two reads clear pipeline */
    387391        NOP                          /* NOPs ensure execution */
    388392        NOP
    389         lw a0,FPCS_OFFSET*4(a1)      /* Load saved FPCS value */
     393        lw a0,FPCS_OFFSET*F_SZ(a1)   /* Load saved FPCS value */
    390394        NOP
    391395        ctc1 a0,$31                  /* Restore FPCS register */
     
    411415        .set noreorder
    412416
    413         MFC0    t0,C0_SR
     417        mfc0    t0,C0_SR
    414418#if (__mips == 3) || (__mips == 32)
    415419        li      t1,SR_IE
     
    420424        not     t1
    421425        and     t0,t1                           /* mask off interrupts while we context switch */
    422         MTC0    t0,C0_SR
     426        mtc0    t0,C0_SR
    423427        NOP
    424428
     
    456460        LDREG   t0,R_EPC*R_SZ(t1)               /* get the userspace EPC from the frame */
    457461        b       2f
    458         nop
     462        NOP
    459463               
    460 1:      la    t0,_Thread_Dispatch               /* if ==0, we're switched out */
     4641:      la      t0,_Thread_Dispatch             /* if ==0, we're switched out */
    461465
    4624662:      STREG   t0,C0_EPC_OFFSET*R_SZ(a0)
     
    479483       
    480484/*      NOP */
    481 /*#if __mips == 3 */
     485/*#if (__mips == 3) || (__mips == 32) */
    482486/*        andi  t0,SR_EXL */
    483487/*        bnez  t0,_CPU_Context_1 */   /* set exception level from restore context */
     
    531535        ** Save IE
    532536        */
    533         or      t2, SR_IE
     537        or      t2,SR_IE
    534538#elif __mips == 1
    535539        /*
     
    544548        and     t0,t2           /* keep only the per-task bits */
    545549               
    546         MFC0    t1,C0_SR        /* grab the current SR */
     550        mfc0    t1,C0_SR        /* grab the current SR */
    547551        not     t2             
    548552        and     t1,t2           /* mask off the old task's per-task bits */
    549553        or      t1,t0           /* or in the new task's bits */
    550         MTC0    t1,C0_SR        /* and load the new SR */
     554        mtc0    t1,C0_SR        /* and load the new SR */
    551555        NOP
    552556       
     
    579583
    580584       
    581 ASM_EXTERN(_ISR_Nest_level, SZ_INT)
    582 ASM_EXTERN(_Thread_Dispatch_disable_level,SZ_INT)
    583 ASM_EXTERN(_Context_Switch_necessary,SZ_INT)
    584 ASM_EXTERN(_ISR_Signals_to_thread_executing,SZ_INT)
    585 ASM_EXTERN(_Thread_Executing,SZ_INT)
     585ASM_EXTERN(_ISR_Nest_level,4)
     586ASM_EXTERN(_Thread_Dispatch_disable_level,4)
     587ASM_EXTERN(_Context_Switch_necessary,4)
     588ASM_EXTERN(_ISR_Signals_to_thread_executing,4)
     589ASM_EXTERN(_Thread_Executing,4)
    586590       
    587591.extern _Thread_Dispatch
     
    649653
    650654        /* wastes a lot of stack space for context?? */
    651         ADDIU    sp,sp,-EXCP_STACK_SIZE
     655        ADDIU    sp,sp,-EXCP_STACK_SIZE
    652656
    653657        STREG ra, R_RA*R_SZ(sp)  /* store ra on the stack */
     
    679683        .set at
    680684
    681         MFC0     t0,C0_SR
    682         MFC0     t1,C0_EPC
     685        mfc0     t0,C0_SR
     686        MFCO     t1,C0_EPC
    683687        STREG    t0,R_SR*R_SZ(sp)
    684688        STREG    t1,R_EPC*R_SZ(sp)
    685        
     689
    686690
    687691#ifdef INSTRUMENT_EXECUTING_THREAD
     
    690694        sw t2, 0x8001FFF0
    691695#endif
    692        
     696
    693697        /* determine if an interrupt generated this exception */
    694698
    695         MFC0     t0,C0_CAUSE
     699        mfc0     t0,C0_CAUSE
    696700        NOP
    697701
     
    726730
    727731#if __mips == 1
    728         MFC0     t0,C0_TAR
    729 #endif
    730         MFC0     t1,C0_BADVADDR
     732        mfc0     t0,C0_TAR
     733#endif
     734        MFCO     t1,C0_BADVADDR
    731735       
    732736#if __mips == 1
     
    738742       
    739743#if ( CPU_HARDWARE_FP == TRUE )
    740         MFC0     t0,C0_SR                 /* we have a FPU, save state if enabled */
     744        mfc0     t0,C0_SR                 /* FPU is enabled, save state */
    741745        NOP
    742746        srl      t0,t0,16
     
    748752        jal      _CPU_Context_save_fp_from_exception
    749753        NOP
    750         MFC1     t0,C1_REVISION
    751         MFC1     t1,C1_STATUS
     754        mfc1     t0,C1_REVISION
     755        mfc1     t1,C1_STATUS
    752756        STREG    t0,R_FEIR*R_SZ(sp)
    753757        STREG    t1,R_FCSR*R_SZ(sp)
     
    830834               
    831835#if ( CPU_HARDWARE_FP == TRUE )
    832         MFC0     t0,C0_SR               /* FPU is present, restore state if enabled */
     836        mfc0     t0,C0_SR               /* FPU is enabled, restore state */
    833837        NOP
    834838        srl      t0,t0,16
     
    842846        LDREG    t0,R_FEIR*R_SZ(sp)
    843847        LDREG    t1,R_FCSR*R_SZ(sp)
    844         MTC1     t0,C1_REVISION
    845         MTC1     t1,C1_STATUS
     848        mtc1     t0,C1_REVISION
     849        mtc1     t1,C1_STATUS
    8468502:
    847851#endif
     
    871875_ISR_Handler_1:
    872876
    873         MFC0     t1,C0_SR
     877        mfc0     t1,C0_SR
    874878        and      t0,CAUSE_IPMASK
    875879        and      t0,t1
     
    880884       
    881885        beq      t0,zero,_ISR_Handler_exit
    882         nop
    883        
    884        
    885                
     886        NOP
     887
     888       
    886889  /*
    887890   *  save some or all context on stack
     
    894897   */
    895898
     899
    896900  /*
    897901   *  _ISR_Nest_level++;
    898902   */
    899         LDREG  t0,_ISR_Nest_level
    900         NOP
    901         ADD    t0,t0,1
    902         STREG  t0,_ISR_Nest_level
     903        lw      t0,_ISR_Nest_level
     904        NOP
     905        add     t0,t0,1
     906        sw      t0,_ISR_Nest_level
    903907  /*
    904908   *  _Thread_Dispatch_disable_level++;
    905909   */
    906         LDREG  t1,_Thread_Dispatch_disable_level
    907         NOP
    908         ADD    t1,t1,1
    909         STREG  t1,_Thread_Dispatch_disable_level
     910        lw      t1,_Thread_Dispatch_disable_level
     911        NOP
     912        add     t1,t1,1
     913        sw      t1,_Thread_Dispatch_disable_level
    910914
    911915  /*
     
    913917   *  interrupt source and actually vector to device ISR handlers.
    914918   */
    915        
     919
    916920#ifdef INSTRUMENT_ISR_VECTORING
    917921        NOP
     
    923927        jal      mips_vector_isr_handlers
    924928        NOP
    925        
     929
    926930#ifdef INSTRUMENT_ISR_VECTORING
    927931        li      t1, 0
     
    929933        NOP
    930934#endif
    931                
     935
    932936  /*
    933937   *  --_ISR_Nest_level;
    934938   */
    935         LDREG  t2,_ISR_Nest_level
    936         NOP
    937         ADD    t2,t2,-1
    938         STREG  t2,_ISR_Nest_level
     939        lw      t2,_ISR_Nest_level
     940        NOP
     941        add     t2,t2,-1
     942        sw      t2,_ISR_Nest_level
    939943  /*
    940944   *  --_Thread_Dispatch_disable_level;
    941945   */
    942         LDREG  t1,_Thread_Dispatch_disable_level
    943         NOP
    944         ADD    t1,t1,-1
    945         STREG  t1,_Thread_Dispatch_disable_level
     946        lw      t1,_Thread_Dispatch_disable_level
     947        NOP
     948        add     t1,t1,-1
     949        sw      t1,_Thread_Dispatch_disable_level
    946950  /*
    947951   *  if ( _Thread_Dispatch_disable_level || _ISR_Nest_level )
     
    953957
    954958
    955 
    956        
    957959  /*
    958960   *  #if ( CPU_HAS_SOFTWARE_INTERRUPT_STACK == TRUE )
     
    963965   *    goto the label "exit interrupt (simple case)"
    964966   */
    965         LDREG t0,_Context_Switch_necessary
    966         LDREG t1,_ISR_Signals_to_thread_executing
    967         NOP
    968         or    t0,t0,t1
    969         beq   t0,zero,_ISR_Handler_exit
     967        lw      t0,_Context_Switch_necessary
     968        lw      t1,_ISR_Signals_to_thread_executing
     969        NOP
     970        or      t0,t0,t1
     971        beq     t0,zero,_ISR_Handler_exit
    970972        NOP
    971973
     
    985987*/
    986988
    987         MFC0    t0, C0_SR
     989        mfc0    t0, C0_SR
    988990#if __mips == 1
    989991       
     
    10021004       
    10031005#endif
    1004         MTC0    t0, C0_SR
     1006        mtc0    t0, C0_SR
    10051007        NOP
    10061008
     
    10241026** a badly timed interrupt won't mess things up
    10251027*/
    1026         MFC0    t0, C0_SR
     1028        mfc0    t0, C0_SR
    10271029
    10281030#if __mips == 1
     
    10321034        not     t1
    10331035        and     t0, t1
    1034         MTC0    t0, C0_SR
     1036        mtc0    t0, C0_SR
    10351037        NOP
    10361038
    1037  #elif (__mips == 3) || (__mips == 32)
    1038 
    1039         move    t2, t0
    1040        
    1041   /* make sure XL & IE are clear so ints are disabled & we can update EPC for the return */
    1042         li   t1,SR_EXL | SR_IE
     1039#elif (__mips == 3) || (__mips == 32)
     1040
     1041        /* make sure EXL and IE are set so ints are disabled & we can update EPC for the return */
     1042        li   t1,SR_IE           /* Clear IE first (recommended) */
    10431043        not  t1
    10441044        and  t0,t1
    1045         MTC0 t0,C0_SR
     1045        mtc0 t0,C0_SR
    10461046        NOP
    10471047       
    1048         /* store new EPC value, which we can do since XL=0 */
     1048        /* apply task's SR with EXL set so the eret will return properly */
     1049        or      t0, SR_EXL | SR_IE
     1050        mtc0    t0, C0_SR
     1051        NOP
     1052
     1053        /* store new EPC value, which we can do since EXL=0 */
    10491054        LDREG   t0, R_EPC*R_SZ(sp)
    10501055        NOP
    1051         MTC0    t0, C0_EPC
     1056        MTCO    t0, C0_EPC
    10521057        NOP
    10531058       
    1054         /* apply task's SR with XL set so the eret will return properly */
    1055         or      t2, SR_EXL
    1056         MTC0    t2, C0_SR
    1057         NOP
    1058 #endif
    1059  
    1060  
    1061  
    1062  
    1063  
    1064        
     1059#endif
     1060
     1061
     1062
     1063
     1064
     1065
    10651066#ifdef INSTRUMENT_EXECUTING_THREAD
    10661067        lw      t0,_Thread_Executing
  • cpukit/score/cpu/mips/rtems/score/cpu.h

    r549e88f r7c99007  
    443443    __MIPS_FPU_REGISTER_TYPE fp30;
    444444    __MIPS_FPU_REGISTER_TYPE fp31;
    445     __MIPS_FPU_REGISTER_TYPE fpcs;
     445    uint32_t fpcs;
    446446#endif
    447447} Context_Control_fp;
     
    768768
    769769/*
     770 *  Declare the function that is present in the shared libcpu directory,
     771 *  that returns the processor dependent interrupt mask.
     772 */
     773
     774uint32_t mips_interrupt_mask( void );
     775
     776/*
    770777 *  Disable all interrupts for an RTEMS critical section.  The previous
    771778 *  level is returned in _level.
     
    873880#if (__mips == 3) || (__mips == 32)
    874881#define _INTON          SR_IE
     882#if __mips_fpr==64
     883#define _EXTRABITS      SR_FR
     884#else
    875885#define _EXTRABITS      0
    876 #endif
     886#endif /* __mips_fpr==64 */
     887#endif /* __mips == 3 */
    877888#if __mips == 1
    878889#define _INTON          SR_IEC
    879890#define _EXTRABITS      0  /* make sure we're in user mode on MIPS1 processors */
    880 #endif
     891#endif /* __mips == 1 */
    881892
    882893#define _CPU_Context_Initialize( _the_context, _stack_base, _size, _isr, _entry_point, _is_fp ) \
     
    889900        (_the_context)->fp = _stack_tmp; \
    890901        (_the_context)->ra = (__MIPS_REGISTER_TYPE)_entry_point; \
    891         (_the_context)->c0_sr = ((_intlvl==0)?(0xFF00 | _INTON):( ((_intlvl<<9) & 0xfc00) | \
    892                                                        0x300 | \
    893                                                        ((_intlvl & 1)?_INTON:0)) ) | \
     902        (_the_context)->c0_sr = ((_intlvl==0)?(mips_interrupt_mask() | 0x300 | _INTON): \
     903                ( ((_intlvl<<9) & mips_interrupt_mask()) | 0x300 | ((_intlvl & 1)?_INTON:0)) ) | \
    894904                                SR_CU0 | ((_is_fp)?SR_CU1:0) | _EXTRABITS; \
    895905  }
  • make/ChangeLog

    r549e88f r7c99007  
     12006-06-08      Bruce Robinson <brucer@pmccorp.com>
     2       
     3        * custom/rbtx4925.cfg:  Fix CPU_CFLAGS defines.
     4        * custom/rbtx4938.cfg:  Fix CPU_CFLAGS defines.
     5
    162005-04-10      Eric Norum <norume@aps.anl.gov>
    27
    3     *  custom/uC5282.cfg: Keep frame pointer -- gdb is much more useful.
     8        *  custom/uC5282.cfg: Keep frame pointer -- gdb is much more useful.
    49
    5102006-03-16      Ralf Corsepius <ralf.corsepius@rtems.org>
  • make/custom/rbtx4925.cfg

    r549e88f r7c99007  
    1414#  This contains the compiler options necessary to select the CPU model
    1515#  and (hopefully) optimize for it.
    16 CPU_CFLAGS = -mips3 -G0 -EL -DCPU_TX49
     16CPU_CFLAGS = -mips3 -G0 -EL
    1717
    1818# optimize flag: typically -0, could use -O4 or -fast
  • make/custom/rbtx4938.cfg

    r549e88f r7c99007  
    1414#  This contains the compiler options necessary to select the CPU model
    1515#  and (hopefully) optimize for it.
    16 CPU_CFLAGS = -mips3 -G0 -EL -DCPU_TX49
     16CPU_CFLAGS = -mips3 -G0 -EL
    1717
    1818# optimize flag: typically -0, could use -O4 or -fast
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