Changeset 7c7184a in rtems


Ignore:
Timestamp:
Feb 1, 2005, 3:12:55 PM (15 years ago)
Author:
Eric Norum <WENorum@…>
Branches:
4.10, 4.11, 4.8, 4.9, master
Children:
50fea8b
Parents:
7a6d1a3
Message:

Place FEC buffer descriptors in static RAM. No more cache concerns.

Location:
c/src/lib/libbsp/m68k/uC5282
Files:
3 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/m68k/uC5282/ChangeLog

    r7a6d1a3 r7c7184a  
     12005-02-01  Eric Norum <norume@aps.anl.gov>
     2
     3        * start/start.S, network/network.c: Place FEC buffer descriptors in SRAM.
     4          No longer need to worry about buffer descriptor caching.
     5
    162005-01-31  Eric Norum <norume@aps.anl.gov>
    27
  • c/src/lib/libbsp/m68k/uC5282/network/network.c

    r7a6d1a3 r7c7184a  
    124124
    125125/*
    126  * Allocate buffer descriptors
     126 * Allocate buffer descriptors from (non-cached) on-chip static RAM
    127127 * Ensure 128-bit (16-byte) alignment
    128128 */
     
    130130mcf5282_bd_allocate(unsigned int count)
    131131{
    132     mcf5282BufferDescriptor_t *p;
    133 
    134     p = malloc((count * sizeof(mcf5282BufferDescriptor_t)) + 15, 0, M_NOWAIT);
    135     if (!p)
    136         rtems_panic("FEC BD");
    137     if ((int)p & 0xF)
    138         p = (mcf5282BufferDescriptor_t *)((char *)p + (16 - ((int)p & 0xF)));
     132    extern char __SRAMBASE[];
     133    static mcf5282BufferDescriptor_t *bdp = (mcf5282BufferDescriptor_t *)__SRAMBASE;
     134    mcf5282BufferDescriptor_t *p = bdp;
     135
     136    bdp += count;
     137    if ((int)bdp & 0xF)
     138        bdp = (mcf5282BufferDescriptor_t *)((char *)bdp + (16 - ((int)bdp & 0xF)));
    139139    return p;
    140140}
     
    303303{
    304304    struct mbuf *m, *n;
    305     volatile mcf5282BufferDescriptor_t *txBd;
    306 
    307     for (;;) {
    308         if (sc->txBdActiveCount == 0)
    309             return;
    310         txBd = sc->txBdBase + sc->txBdTail;
    311         rtems_cache_invalidate_multiple_data_lines(txBd, sizeof *txBd);
    312         if ((txBd->status & MCF5282_FEC_TxBD_R) != 0)
    313             return;
     305
     306    while ((sc->txBdActiveCount != 0)
     307        && ((sc->txBdBase[sc->txBdTail].status & MCF5282_FEC_TxBD_R) == 0)) {
    314308        m = sc->txMbuf[sc->txBdTail];
    315309        MFREE(m, n);
     
    360354         * Wait for packet if there's not one ready
    361355         */
    362         rtems_cache_invalidate_multiple_data_lines(rxBd, sizeof *rxBd);
    363356        if ((status = rxBd->status) & MCF5282_FEC_RxBD_E) {
    364 int chkCount=0 ;
    365357            /*
    366358             * Clear old events.
     
    374366             * `if' above, and the clearing of the RXF bit in the EIR.
    375367             */
    376             for (;;) {
     368            while ((status = rxBd->status) & MCF5282_FEC_RxBD_E) {
    377369                rtems_event_set events;
    378370                int level;
    379 
    380                 rtems_cache_invalidate_multiple_data_lines(rxBd, sizeof *rxBd);
    381                 if (((status = rxBd->status) & MCF5282_FEC_RxBD_E) == 0)
    382                     break;
    383371
    384372                rtems_interrupt_disable(level);
     
    404392
    405393            /*
    406              * Invalidate the cache and push the packet up
     394             * Invalidate the cache and push the packet up.
    407395             * The cache is so small that it's more efficient to just
    408396             * invalidate the whole thing unless the packet is very small.
  • c/src/lib/libbsp/m68k/uC5282/start/start.S

    r7a6d1a3 r7c7184a  
    314314    PUBLIC (start)
    315315SYM(start):
    316     move.w  #0x2700,sr                  | Disable interrupts
    317 
    318     move.l  #__SRAMBASE+1,d0     | Enable the MCF5282 internal SRAM
    319     movec   d0,%rambar          | ...so we have a stack
    320     move.l  #__SRAMBASE+SRAM_SIZE-4,sp   | Overwrite the fake stack pointer
     316    move.w  #0x2700,sr                 | Disable interrupts
    321317
    322318    /*
     
    324320     * moved the IPSBAR, we're doomed........
    325321     */
    326     move.l  #__IPSBAR+1,d0      | Enable the MCF5282 internal peripherals
     322    move.l  #__IPSBAR+1,d0             | Enable the MCF5282 internal peripherals
    327323    move.l  d0,DEFAULT_IPSBAR
    328    
     324    move.l  #__SRAMBASE+0x201,d0       | Enable the MCF5282 internal SRAM
     325    movec   d0,%rambar                 | CPU-space copy of RAMBAR
     326    move.l  d0,DEFAULT_IPSBAR+8        | Memory-space copy of RAMBAR
     327    move.l  #__SRAMBASE+SRAM_SIZE-4,sp | Overwrite the fake stack pointer
     328
    329329    /*
    330330     * Copy the vector table to address 0 (VBR must be 0 mod 2^20)
Note: See TracChangeset for help on using the changeset viewer.