Changeset 7c3b0df1 in rtems for cpukit/score/cpu/riscv/cpu.c


Ignore:
Timestamp:
Jun 22, 2018, 11:30:49 AM (3 years ago)
Author:
Sebastian Huber <sebastian.huber@…>
Branches:
5, master
Children:
853c5ef
Parents:
9b2ef07f
git-author:
Sebastian Huber <sebastian.huber@…> (06/22/18 11:30:49)
git-committer:
Sebastian Huber <sebastian.huber@…> (06/28/18 13:02:08)
Message:

riscv: Implement ISR set/get level

Fix prototypes.

Update #3433.

File:
1 edited

Legend:

Unmodified
Added
Removed
  • cpukit/score/cpu/riscv/cpu.c

    r9b2ef07f r7c3b0df1  
    6060}
    6161
    62 void _CPU_ISR_Set_level(unsigned long level)
     62uint32_t _CPU_ISR_Get_level( void )
    6363{
    64   /* Do nothing */
    65 }
     64  if ( _CPU_ISR_Is_enabled( read_csr( mstatus ) ) ) {
     65    return 0;
     66  }
    6667
    67 unsigned long  _CPU_ISR_Get_level( void )
    68 {
    69   /* Do nothing */
    70   return 0;
     68  return 1;
    7169}
    7270
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