Changeset 7c30dca in rtems


Ignore:
Timestamp:
Jan 14, 2021, 1:58:15 PM (7 weeks ago)
Author:
Kinsey Moore <kinsey.moore@…>
Branches:
master
Children:
8ee22b2
Parents:
7696533
git-author:
Kinsey Moore <kinsey.moore@…> (01/14/21 13:58:15)
git-committer:
Joel Sherrill <joel@…> (01/14/21 19:32:06)
Message:

bsps/aarch64: Swap primary ZynqMP UART

Both Qemu and actual hardware treat the second UART in memory map as the
primary UART. This adjusts the ZynqMP BSPs to match.

Location:
bsps/aarch64/xilinx-zynqmp
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • bsps/aarch64/xilinx-zynqmp/console/console.c

    r7696533 r7c30dca  
    4747  {
    4848    .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 0" ),
    49     .regs = (volatile struct zynq_uart *) 0xff000000,
     49    .regs = (volatile struct zynq_uart *) 0xff010000,
    5050    .irq = ZYNQMP_IRQ_UART_0
    5151  }, {
    5252    .base = RTEMS_TERMIOS_DEVICE_CONTEXT_INITIALIZER( "Zynq UART 1" ),
    53     .regs = (volatile struct zynq_uart *) 0xff010000,
     53    .regs = (volatile struct zynq_uart *) 0xff000000,
    5454    .irq = ZYNQMP_IRQ_UART_1
    5555  }
  • bsps/aarch64/xilinx-zynqmp/include/bsp/irq.h

    r7696533 r7c30dca  
    5555#define BSP_TIMER_VIRT_PPI 27
    5656#define BSP_TIMER_PHYS_NS_PPI 30
    57 #define ZYNQMP_IRQ_UART_0 53
    58 #define ZYNQMP_IRQ_UART_1 54
     57#define ZYNQMP_IRQ_UART_0 54
     58#define ZYNQMP_IRQ_UART_1 53
    5959#define ZYNQMP_IRQ_ETHERNET_0 89
    6060#define ZYNQMP_IRQ_ETHERNET_1 91
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