Changeset 7c05d28 in rtems


Ignore:
Timestamp:
May 24, 2001, 7:54:22 PM (20 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
01ec6c0
Parents:
6937dfd6
Message:

2000-05-24 Joel Sherrill <joel@…>

  • mongoosev/include/mongoose-v.h, mongoosev/vectorisrs/vectorisrs.c, r46xx/vectorisrs/vectorisrs.c, tx39/vectorisrs/vectorisrs.c, tx39/include/tx3904.h: All exceptions were given low numbers and thus can be now be installed and processed in a uniform manner just like interrupts. Variances between various MIPS ISA levels are not accounted for at this time.
  • mongoosev/vectorisrs/Makefile.am, mongoosev/vectorisrs/maxvectors.c, r46xx/vectorisrs/Makefile.am, r46xx/vectorisrs/maxvectors.c, tx39/vectorisrs/Makefile.am, tx39/vectorisrs/maxvectors.c, shared/interrupts/maxvectors.c, shared/interrupts/Makefile.am: Split the shared maxvectors.c into a variety of CPU model specific versions to simplify the build process and reduce depdencies. Deleted shared/interrupts/maxvectors.c and created various CPU model versions.
Location:
c/src/lib/libcpu/mips
Files:
3 added
10 edited
1 moved

Legend:

Unmodified
Added
Removed
  • c/src/lib/libcpu/mips/ChangeLog

    r6937dfd6 r7c05d28  
     12000-05-24      Joel Sherrill <joel@OARcorp.com>
     2
     3        * mongoosev/include/mongoose-v.h, mongoosev/vectorisrs/vectorisrs.c,
     4        r46xx/vectorisrs/vectorisrs.c, tx39/vectorisrs/vectorisrs.c,
     5        tx39/include/tx3904.h: All exceptions were given low numbers and thus
     6        can be now be installed and processed in a uniform manner just like interrupts.
     7        Variances between various MIPS ISA levels are not accounted for at this time.
     8        * mongoosev/vectorisrs/Makefile.am, mongoosev/vectorisrs/maxvectors.c,
     9        r46xx/vectorisrs/Makefile.am, r46xx/vectorisrs/maxvectors.c,
     10        tx39/vectorisrs/Makefile.am, tx39/vectorisrs/maxvectors.c,
     11        shared/interrupts/maxvectors.c, shared/interrupts/Makefile.am: Split the
     12        shared maxvectors.c into a variety of CPU model specific versions to simplify
     13        the build process and reduce depdencies.  Deleted shared/interrupts/maxvectors.c
     14        and created various CPU model versions.
     15
    1162001-05-24      Greg Menke <gregory.menke@gsfc.nasa.gov>
    217
  • c/src/lib/libcpu/mips/mongoosev/include/mongoose-v.h

    r6937dfd6 r7c05d28  
    249249 */
    250250
    251 #define MONGOOSEV_IRQ_INT0                    0
     251#define MONGOOSEV_IRQ_INT0                    MIPS_INTERRUPT_BASE+0
    252252#define MONGOOSEV_IRQ_TIMER1                  MONGOOSEV_IRQ_INT0
    253 #define MONGOOSEV_IRQ_INT1                    1
     253#define MONGOOSEV_IRQ_INT1                    MIPS_INTERRUPT_BASE+1
    254254#define MONGOOSEV_IRQ_TIMER2                  MONGOOSEV_IRQ_INT1
    255 #define MONGOOSEV_IRQ_INT2                    2
    256 #define MONGOOSEV_IRQ_INT3                    3
     255#define MONGOOSEV_IRQ_INT2                    MIPS_INTERRUPT_BASE+2
     256#define MONGOOSEV_IRQ_INT3                    MIPS_INTERRUPT_BASE+3
    257257#define MONGOOSEV_IRQ_FPU                     MONGOOSEV_IRQ_INT3
    258258
    259 #define MONGOOSEV_IRQ_INT4                    4
     259#define MONGOOSEV_IRQ_INT4                    MIPS_INTERRUPT_BASE+4
    260260
    261261/* MONGOOSEV_IRQ_INT5 indicates that a peripheral caused the IRQ. */
    262 #define MONGOOSEV_IRQ_PERIPHERAL_BASE         5
     262#define MONGOOSEV_IRQ_PERIPHERAL_BASE         MIPS_INTERRUPT_BASE+5
    263263#define MONGOOSEV_IRQ_XINT0                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 0
    264264#define MONGOOSEV_IRQ_XINT1                  MONGOOSEV_IRQ_PERIPHERAL_BASE + 1
     
    294294#define MONGOOSEV_IRQ_CORRECTABLE_ERROR      MONGOOSEV_IRQ_PERIPHERAL_BASE + 31
    295295
    296 #define MONGOOSEV_IRQ_SOFTWARE_1             37
    297 #define MONGOOSEV_IRQ_SOFTWARE_2             38
    298 
    299 
    300 /* gdm, 5/14.  Added exception vectoring to the ISR table- these
    301 entries are never called by the ISR servicing, only by the exception
    302 servicing routine.  The ISR table is used because vector setup there
    303 is already supported.  Please note exception routines are passed 2
    304 parameters; one of the below vectors and a pointer to the exception's
    305 stack frame, the register layout of which is found in
    306 
    307 exec/score/cpu/mips/iregdef.h
    308 
    309 in conjunction with
    310 
    311 exec/score/cpu/mips/cpu_asm.S
    312 
    313 */
    314 
    315 #define MONGOOSEV_EXCEPTION_BASE 39
    316 
    317 #define MONGOOSEV_EXCEPTION_ADEL             MONGOOSEV_EXCEPTION_BASE+0
    318 #define MONGOOSEV_EXCEPTION_ADES             MONGOOSEV_EXCEPTION_BASE+1
    319 #define MONGOOSEV_EXCEPTION_IBE              MONGOOSEV_EXCEPTION_BASE+2
    320 #define MONGOOSEV_EXCEPTION_DBE              MONGOOSEV_EXCEPTION_BASE+3
    321 #define MONGOOSEV_EXCEPTION_SYSCALL          MONGOOSEV_EXCEPTION_BASE+4
    322 #define MONGOOSEV_EXCEPTION_BREAK            MONGOOSEV_EXCEPTION_BASE+5
    323 #define MONGOOSEV_EXCEPTION_RI               MONGOOSEV_EXCEPTION_BASE+6
    324 #define MONGOOSEV_EXCEPTION_CPU              MONGOOSEV_EXCEPTION_BASE+7
    325 #define MONGOOSEV_EXCEPTION_OVERFLOW         MONGOOSEV_EXCEPTION_BASE+8
    326 
    327 
    328 
    329 
    330 
    331 
    332 #define SR_CUMASK       0xf0000000      /* coproc usable bits */
    333 #define SR_CU3          0x80000000      /* Coprocessor 3 usable */
    334 #define SR_CU2          0x40000000      /* Coprocessor 2 usable */
    335 #define SR_CU1          0x20000000      /* Coprocessor 1 usable */
    336 #define SR_CU0          0x10000000      /* Coprocessor 0 usable */
    337 #define SR_BEV          0x00400000      /* use boot exception vectors */
    338 #define SR_TS           0x00200000      /* TLB shutdown */
    339 #define SR_PE           0x00100000      /* cache parity error */
    340 #define SR_CM           0x00080000      /* cache miss */
    341 #define SR_PZ           0x00040000      /* cache parity zero */
    342 #define SR_SWC          0x00020000      /* swap cache */
    343 #define SR_ISC          0x00010000      /* Isolate data cache */
    344 #define SR_IMASK        0x0000ff00      /* Interrupt mask */
    345 #define SR_IMASK8       0x00000000      /* mask level 8 */
    346 #define SR_IMASK7       0x00008000      /* mask level 7 */
    347 #define SR_IMASK6       0x0000c000      /* mask level 6 */
    348 #define SR_IMASK5       0x0000e000      /* mask level 5 */
    349 #define SR_IMASK4       0x0000f000      /* mask level 4 */
    350 #define SR_IMASK3       0x0000f800      /* mask level 3 */
    351 #define SR_IMASK2       0x0000fc00      /* mask level 2 */
    352 #define SR_IMASK1       0x0000fe00      /* mask level 1 */
    353 #define SR_IMASK0       0x0000ff00      /* mask level 0 */
    354 
    355 #define SR_IBIT8        0x00008000      /* bit level 8 */
    356 #define SR_IBIT7        0x00004000      /* bit level 7 */
    357 #define SR_IBIT6        0x00002000      /* bit level 6 */
    358 #define SR_IBIT5        0x00001000      /* bit level 5 */
    359 #define SR_IBIT4        0x00000800      /* bit level 4 */
    360 #define SR_IBIT3        0x00000400      /* bit level 3 */
    361 #define SR_IBIT2        0x00000200      /* bit level 2 */
    362 #define SR_IBIT1        0x00000100      /* bit level 1 */
    363 
    364 #define SR_KUO          0x00000020      /* old kernel/user, 0 => k, 1 => u */
    365 #define SR_IEO          0x00000010      /* old interrupt enable, 1 => enable */
    366 #define SR_KUP          0x00000008      /* prev kernel/user, 0 => k, 1 => u */
    367 #define SR_IEP          0x00000004      /* prev interrupt enable, 1 => enable */
    368 #define SR_KUC          0x00000002      /* cur kernel/user, 0 => k, 1 => u */
    369 #define SR_IEC          0x00000001      /* cur interrupt enable, 1 => enable */
     296#define MONGOOSEV_IRQ_SOFTWARE_1             MIPS_INTERRUPT_BASE+37
     297#define MONGOOSEV_IRQ_SOFTWARE_2             MIPS_INTERRUPT_BASE+38
     298#define MONGOOSEV_MAXIMUM_VECTORS            MIPS_INTERRUPT_BASE+39
     299
     300
     301/*
     302 *  Status Register Bits
     303 */
     304
     305#define SR_CUMASK       0xf0000000      /* coproc usable bits */
     306#define SR_CU3          0x80000000      /* Coprocessor 3 usable */
     307#define SR_CU2          0x40000000      /* Coprocessor 2 usable */
     308#define SR_CU1          0x20000000      /* Coprocessor 1 usable */
     309#define SR_CU0          0x10000000      /* Coprocessor 0 usable */
     310#define SR_BEV          0x00400000      /* use boot exception vectors */
     311#define SR_TS           0x00200000      /* TLB shutdown */
     312#define SR_PE           0x00100000      /* cache parity error */
     313#define SR_CM           0x00080000      /* cache miss */
     314#define SR_PZ           0x00040000      /* cache parity zero */
     315#define SR_SWC          0x00020000      /* swap cache */
     316#define SR_ISC          0x00010000      /* Isolate data cache */
     317#define SR_IMASK        0x0000ff00      /* Interrupt mask */
     318#define SR_IMASK8       0x00000000      /* mask level 8 */
     319#define SR_IMASK7       0x00008000      /* mask level 7 */
     320#define SR_IMASK6       0x0000c000      /* mask level 6 */
     321#define SR_IMASK5       0x0000e000      /* mask level 5 */
     322#define SR_IMASK4       0x0000f000      /* mask level 4 */
     323#define SR_IMASK3       0x0000f800      /* mask level 3 */
     324#define SR_IMASK2       0x0000fc00      /* mask level 2 */
     325#define SR_IMASK1       0x0000fe00      /* mask level 1 */
     326#define SR_IMASK0       0x0000ff00      /* mask level 0 */
     327
     328#define SR_IBIT8        0x00008000      /* bit level 8 */
     329#define SR_IBIT7        0x00004000      /* bit level 7 */
     330#define SR_IBIT6        0x00002000      /* bit level 6 */
     331#define SR_IBIT5        0x00001000      /* bit level 5 */
     332#define SR_IBIT4        0x00000800      /* bit level 4 */
     333#define SR_IBIT3        0x00000400      /* bit level 3 */
     334#define SR_IBIT2        0x00000200      /* bit level 2 */
     335#define SR_IBIT1        0x00000100      /* bit level 1 */
     336
     337#define SR_KUO          0x00000020      /* old kernel/user, 0 => k, 1 => u */
     338#define SR_IEO          0x00000010      /* old interrupt enable, 1 => enable */
     339#define SR_KUP          0x00000008      /* prev kernel/user, 0 => k, 1 => u */
     340#define SR_IEP          0x00000004      /* prev interrupt enable, 1 => enable */
     341#define SR_KUC          0x00000002      /* cur kernel/user, 0 => k, 1 => u */
     342#define SR_IEC          0x00000001      /* cur interrupt enable, 1 => enable */
    370343#define SR_KUMSK        (SR_KUO|SR_IEO|SR_KUP|SR_IEP|SR_KUC|SR_IEC)
    371344
    372 #define SR_IMASKSHIFT   8
     345#define SR_IMASKSHIFT   8
    373346
    374347#endif
  • c/src/lib/libcpu/mips/mongoosev/vectorisrs/Makefile.am

    r6937dfd6 r7c05d28  
    77PGM = $(ARCH)/vectorisrs.rel
    88
    9 C_FILES = vectorisrs.c
     9C_FILES = maxvectors.c vectorisrs.c
    1010
    1111vectorisrs_rel_OBJECTS = $(C_FILES:%.c=$(ARCH)/%.o) $(S_FILES:%.S=$(ARCH)/%.o)
  • c/src/lib/libcpu/mips/mongoosev/vectorisrs/maxvectors.c

    r6937dfd6 r7c05d28  
    1313 */
    1414
    15 
    1615/*
    17  *  The Toshiba TX3904 attaches 4 of the eight interrupt bits to an
    18  *  on-CPU interrupt controller so that these four bits map to 16
    19  *  unique interrupts.  So you have: 2 software interrupts, an NMI,
    20  *  and 16 others.
     16 *  Reserve first 32 for exceptions.
    2117 */
    22 
    23 #if defined(TX39)
    24 #define MAX_VECTORS 19
    25 #endif
    2618
    2719/*
     
    3224 *  these are reserved but for simplicity in processing, we
    3325 *  reserve slots for those bits anyway.
    34  *
    35  * gdm, 5/14, added 15 more slots so exceptions can be vectored as well.
    3626 */
    3727
    38 #if defined(MONGOOSEV)
    39 #define MAX_VECTORS (38+10)
    40 #endif
     28#include <rtems.h>
     29#include <libcpu/mongoose-v.h>
    4130
    42 #ifndef MAX_VECTORS
    43 #define MAX_VECTORS 8
    44 #endif
     31unsigned int mips_interrupt_number_of_vectors = MONGOOSEV_MAXIMUM_VECTORS;
    4532
    46 unsigned int mips_interrupt_number_of_vectors = MAX_VECTORS;
    4733
  • c/src/lib/libcpu/mips/mongoosev/vectorisrs/vectorisrs.c

    r6937dfd6 r7c05d28  
    2929
    3030#include <bspIo.h>  /* for printk */
    31 
    32 
    33 
    34 
    35 
    3631
    3732void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
     
    118113}
    119114
    120 
    121 
    122 
    123 
    124 
    125 
    126115void mips_default_isr( int vector )
    127116{
     
    132121  mips_get_cause( cause );
    133122
    134   printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n", vector, cause, sr );
     123  printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
     124    vector, cause, sr );
    135125  rtems_fatal_error_occurred(1);
    136126}
    137 
    138 
    139 
    140 
    141 
    142 
    143 
    144127
    145128/* userspace routine to assert either software interrupt */
     
    160143}
    161144
    162 
    163 
    164 
    165 
    166 
    167 
    168 
    169 
    170 
    171 
    172 /* exception vectoring, from vectorexceptions.c  */
    173 
    174 /*#include <rtems.h>
    175 #include <stdlib.h>
    176 #include "iregdef.h"
    177 #include <bsp.h>
    178 #include <bspIo.h>*/
    179 
    180 
    181 
    182 
    183 char *cause_strings[32] =
    184 {
    185   /*  0 */ "Int",
    186   /*  1 */ "TLB Mods",
    187   /*  2 */ "TLB Load",
    188   /*  3 */ "TLB Store",
    189   /*  4 */ "Address Load",
    190   /*  5 */ "Address Store",
    191   /*  6 */ "Instruction Bus Error",
    192   /*  7 */ "Data Bus Error",
    193   /*  9 */ "Syscall",
    194   /* 10 */ "Breakpoint",
    195   /* 11 */ "Reserved Instruction",
    196   /* 12 */ "Coprocessor Unuseable",
    197   /* 13 */ "Overflow",
    198   /* 14 */ "Trap",
    199   /* 15 */ "Instruction Virtual Coherency Error",
    200   /* 16 */ "FP Exception",
    201   /* 17 */ "Reserved 17",
    202   /* 18 */ "Reserved 17",
    203   /* 19 */ "Reserved 17",
    204   /* 20 */ "Reserved 20",
    205   /* 21 */ "Reserved 21",
    206   /* 22 */ "Reserved 22",
    207   /* 23 */ "Watch",
    208   /* 24 */ "Reserved 24",
    209   /* 25 */ "Reserved 25",
    210   /* 26 */ "Reserved 26",
    211   /* 27 */ "Reserved 27",
    212   /* 28 */ "Reserved 28",
    213   /* 29 */ "Reserved 29",
    214   /* 30 */ "Reserved 30",
    215   /* 31 */ "Data Virtual Coherency Error"
    216 };
    217 
    218 
    219 
    220 struct regdef
    221 {
    222       int  offset;
    223       char *name;
    224 };
    225 
    226 
    227 /*
    228  *  this struct holds the set of registers we're going to dump on an
    229  *  exception, the symbols are defined by iregdef.h, and they are set
    230  *  by cpu_asm.S into the CPU_Interrupt_frame passed here by
    231  *  ISR_Handler.  Note not all registers are stored, only those used
    232  *  by the cpu_asm.S code.  Refer to cpu_asm.S
    233  */
    234 
    235 
    236 struct regdef dumpregs[]= { { R_RA, "R_RA" }, { R_V0, "R_V0" }, { R_V1, "R_V1" }, { R_A0, "R_A0" }, { R_A1,   "R_A1" }, { R_A2,   "R_A2" }, \
    237                             { R_A3, "R_A3" }, { R_T0, "R_T0" }, { R_T1, "R_T1" }, { R_T2, "R_T2" }, { R_T3,   "R_T3" }, { R_T4,   "R_T4" }, \
    238                             { R_T5, "R_T5" }, { R_T6, "R_T6" }, { R_T7, "R_T7" }, { R_T8, "R_T8" }, { R_MDLO, "R_MDLO" }, { R_MDHI, "R_MDHI" }, \
    239                             { R_GP, "R_GP" }, { R_FP, "R_FP" }, { R_AT, "R_AT" }, { R_EPC,"R_EPC"}, { -1, NULL } };
    240 
    241 
    242 
    243 void mips_default_exception_code_handler( int exc, CPU_Interrupt_frame *frame )
    244 {
    245   unsigned int sr;
    246   unsigned int cause;
    247   int   i, j;
    248 
    249   mips_get_sr( sr );
    250   mips_get_cause( cause );
    251 
    252   printk( "Unhandled exception %d\n", exc );
    253   printk( "sr: 0x%08x  cause: 0x%08x --> %s\n", sr, cause, cause_strings[(cause >> 2) &0x1f] );
    254 
    255   for(i=0; dumpregs[i].offset > -1; i++)
    256   {
    257      printk("   %s", dumpregs[i].name);
    258      for(j=0; j< 7-strlen(dumpregs[i].name); j++) printk(" ");
    259      printk("  %08X\n", frame->regs[dumpregs[i].offset] );
    260   }
    261  
    262   rtems_fatal_error_occurred(1);
    263 }
    264 
    265 
    266 
    267 
    268 
    269 
    270 
    271 #define CALL_EXC(_vector,_frame) \
    272    do { \
    273         if( _ISR_Vector_table[_vector] ) \
    274              (_ISR_Vector_table[_vector])(_vector,_frame); \
    275           else \
    276              mips_default_exception_code_handler( _vector, _frame ); \
    277    } while(0)
    278 
    279 
    280 
    281 
    282 
    283 void mips_vector_exceptions( CPU_Interrupt_frame *frame )
    284 {
    285   unsigned32 cause;
    286   unsigned32 exc;
    287 
    288   mips_get_cause( cause );
    289   exc = (cause >> 2) & 0x1f;
    290 
    291   if( exc == 4 )
    292      CALL_EXC( MONGOOSEV_EXCEPTION_ADEL, frame );
    293 
    294   else if( exc == 5 )
    295      CALL_EXC( MONGOOSEV_EXCEPTION_ADES, frame );
    296 
    297   else if( exc == 6 )
    298      CALL_EXC( MONGOOSEV_EXCEPTION_IBE, frame );
    299 
    300   else if( exc == 7 )
    301      CALL_EXC( MONGOOSEV_EXCEPTION_DBE, frame );
    302 
    303   else if( exc == 8 )
    304      CALL_EXC( MONGOOSEV_EXCEPTION_SYSCALL, frame );
    305 
    306   else if( exc == 9 )
    307      CALL_EXC( MONGOOSEV_EXCEPTION_BREAK, frame );
    308 
    309   else if( exc == 10 )
    310      CALL_EXC( MONGOOSEV_EXCEPTION_RI, frame );
    311 
    312   else if( exc == 11 )
    313      CALL_EXC( MONGOOSEV_EXCEPTION_CPU, frame );
    314 
    315   else if( exc == 12 )
    316      CALL_EXC( MONGOOSEV_EXCEPTION_OVERFLOW, frame );
    317 
    318   else
    319      mips_default_exception_code_handler( exc, frame );
    320 }
    321 
    322 
    323 // eof
    324 
  • c/src/lib/libcpu/mips/r46xx/vectorisrs/Makefile.am

    r6937dfd6 r7c05d28  
    77PGM = $(ARCH)/vectorisrs.rel
    88
    9 C_FILES = vectorisrs.c
     9C_FILES = maxvectors.c vectorisrs.c
    1010
    1111vectorisrs_rel_OBJECTS = $(C_FILES:%.c=$(ARCH)/%.o) $(S_FILES:%.S=$(ARCH)/%.o)
  • c/src/lib/libcpu/mips/r46xx/vectorisrs/vectorisrs.c

    r6937dfd6 r7c05d28  
    66#include <stdlib.h>
    77
    8 #define mips_get_cause( _cause ) \
     8
     9void mips_default_isr( int vector );
     10
     11#define CALL_ISR(_vector,_frame) \
    912  do { \
    10     asm volatile( "mfc0 %0, $13; nop" : "=r" (_cause) :  ); \
     13    if ( _ISR_Vector_table[_vector] ) \
     14      (_ISR_Vector_table[_vector])(_vector,_frame); \
     15    else \
     16      mips_default_isr(_vector); \
    1117  } while (0)
    1218
    13 #define CALL_ISR(_vector) \
    14   do { \
    15     if ( _ISR_Vector_table[_vector] ) \
    16       (_ISR_Vector_table[_vector])(_vector); \
    17     else \
    18       mips_default_exception(_vector); \
    19   } while (0)
     19#include <bspIo.h>  /* for printk */
    2020
    21 void mips_default_exception( int vector )
    22 {
    23   printk( "Unhandled exception %d\n", vector );
    24   rtems_fatal_error_occurred(1);
    25 }
    26 
    27 void mips_vector_isr_handlers( void )
     21void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
    2822{
    2923  unsigned int sr;
     
    4236  for ( i=1, mask=0x80 ; i<=8 ; i++, mask >>= 1 ) {
    4337    if ( cause & mask )
    44       CALL_ISR( 8 - i );
     38      CALL_ISR( MIPS_EXCEPTION_BASE + 8 - i, frame );
    4539  }
    4640}
     41
     42void mips_default_isr( int vector )
     43{
     44  unsigned int sr;
     45  unsigned int cause;
     46
     47  mips_get_sr( sr );
     48  mips_get_cause( cause );
     49
     50  printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
     51    vector, cause, sr );
     52  rtems_fatal_error_occurred(1);
     53}
     54
  • c/src/lib/libcpu/mips/shared/interrupts/Makefile.am

    r6937dfd6 r7c05d28  
    77PGM = $(ARCH)/interrupts.rel
    88
    9 C_FILES = installisrentries.c maxvectors.c
     9C_FILES = installisrentries.c vectorexceptions.c
    1010
    1111S_FILES = isr_entries.S
  • c/src/lib/libcpu/mips/tx39/include/tx3904.h

    r6937dfd6 r7c05d28  
    4141 */
    4242
    43 #define TX3904_IRQ_INT1        0
    44 #define TX3904_IRQ_INT2        1
    45 #define TX3904_IRQ_INT3        2
    46 #define TX3904_IRQ_INT4        3
    47 #define TX3904_IRQ_INT5        4
    48 #define TX3904_IRQ_INT6        5
    49 #define TX3904_IRQ_INT7        6
    50 #define TX3904_IRQ_DMAC3       7
    51 #define TX3904_IRQ_DMAC2       8
    52 #define TX3904_IRQ_DMAC1       9
    53 #define TX3904_IRQ_DMAC0      10
    54 #define TX3904_IRQ_SIO0       11
    55 #define TX3904_IRQ_SIO1       12
    56 #define TX3904_IRQ_TMR0       13
    57 #define TX3904_IRQ_TMR1       14
    58 #define TX3904_IRQ_TMR2       15
    59 #define TX3904_IRQ_INT0       16
    60 #define TX3904_IRQ_SOFTWARE_1 17
    61 #define TX3904_IRQ_SOFTWARE_2 18
     43#define TX3904_IRQ_INT1        MIPS_INTERRUPT_BASE+0
     44#define TX3904_IRQ_INT2        MIPS_INTERRUPT_BASE+1
     45#define TX3904_IRQ_INT3        MIPS_INTERRUPT_BASE+2
     46#define TX3904_IRQ_INT4        MIPS_INTERRUPT_BASE+3
     47#define TX3904_IRQ_INT5        MIPS_INTERRUPT_BASE+4
     48#define TX3904_IRQ_INT6        MIPS_INTERRUPT_BASE+5
     49#define TX3904_IRQ_INT7        MIPS_INTERRUPT_BASE+6
     50#define TX3904_IRQ_DMAC3       MIPS_INTERRUPT_BASE+7
     51#define TX3904_IRQ_DMAC2       MIPS_INTERRUPT_BASE+8
     52#define TX3904_IRQ_DMAC1       MIPS_INTERRUPT_BASE+9
     53#define TX3904_IRQ_DMAC0       MIPS_INTERRUPT_BASE+10
     54#define TX3904_IRQ_SIO0        MIPS_INTERRUPT_BASE+11
     55#define TX3904_IRQ_SIO1        MIPS_INTERRUPT_BASE+12
     56#define TX3904_IRQ_TMR0        MIPS_INTERRUPT_BASE+13
     57#define TX3904_IRQ_TMR1        MIPS_INTERRUPT_BASE+14
     58#define TX3904_IRQ_TMR2        MIPS_INTERRUPT_BASE+15
     59#define TX3904_IRQ_INT0        MIPS_INTERRUPT_BASE+16
     60#define TX3904_IRQ_SOFTWARE_1  MIPS_INTERRUPT_BASE+17
     61#define TX3904_IRQ_SOFTWARE_2  MIPS_INTERRUPT_BASE+18
     62#define TX3904_MAXIMUM_VECTORS MIPS_INTERRUPT_BASE+19
    6263
    6364#endif
  • c/src/lib/libcpu/mips/tx39/vectorisrs/Makefile.am

    r6937dfd6 r7c05d28  
    77PGM = $(ARCH)/vectorisrs.rel
    88
    9 C_FILES = vectorisrs.c
     9C_FILES = maxvectors.c vectorisrs.c
    1010
    1111vectorisrs_rel_OBJECTS = $(C_FILES:%.c=$(ARCH)/%.o) $(S_FILES:%.S=$(ARCH)/%.o)
  • c/src/lib/libcpu/mips/tx39/vectorisrs/vectorisrs.c

    r6937dfd6 r7c05d28  
    11/*
     2 *  TX3904 Interrupt Vectoring
     3 *
    24 *  $Id$
    35 */
     
    79#include <libcpu/tx3904.h>
    810
    9 #define mips_get_cause( _cause ) \
    10   do { \
    11     asm volatile( "mfc0 %0, $13; nop" : "=r" (_cause) :  ); \
    12   } while (0)
     11void mips_default_isr( int vector );
    1312
    14 #define CALL_ISR(_vector) \
     13#define CALL_ISR(_vector,_frame) \
    1514  do { \
    1615    if ( _ISR_Vector_table[_vector] ) \
    17       (_ISR_Vector_table[_vector])(_vector); \
     16      (_ISR_Vector_table[_vector])(_vector,_frame); \
    1817    else \
    19       mips_default_exception(_vector); \
     18      mips_default_isr(_vector); \
    2019  } while (0)
    2120
    2221#include <bspIo.h>  /* for printk */
    2322
    24 void mips_default_exception( int vector )
    25 {
    26   printk( "Unhandled exception %d\n", vector );
    27   rtems_fatal_error_occurred(1);
    28 }
    29 
    30 void mips_vector_isr_handlers( void )
     23void mips_vector_isr_handlers( CPU_Interrupt_frame *frame )
    3124{
    3225  unsigned int sr;
     
    4033
    4134  if ( cause & 0x80 )       /* IP[5] ==> INT0 */
    42     CALL_ISR( TX3904_IRQ_INT0 );
     35    CALL_ISR( TX3904_IRQ_INT0, frame );
    4336
    4437  if ( cause & 0x40 ) {     /* (IP[4] == 1) ==> IP[0-3] are valid */
    4538    unsigned int v = (cause >> 2) & 0x0f;
    46     CALL_ISR( v );
     39    CALL_ISR( MIPS_INTERRUPT_BASE + v, frame );
    4740  }
    4841   
    4942  if ( cause & 0x02 )       /* SW[0] */
    50     CALL_ISR( TX3904_IRQ_SOFTWARE_1 );
     43    CALL_ISR( TX3904_IRQ_SOFTWARE_1, frame );
    5144
    5245  if ( cause & 0x01 )       /* IP[1] */
    53     CALL_ISR( TX3904_IRQ_SOFTWARE_2 );
     46    CALL_ISR( TX3904_IRQ_SOFTWARE_2, frame );
    5447}
     48
     49void mips_default_isr( int vector )
     50{
     51  unsigned int sr;
     52  unsigned int cause;
     53
     54  mips_get_sr( sr );
     55  mips_get_cause( cause );
     56
     57  printk( "Unhandled isr exception: vector 0x%02x, cause 0x%08X, sr 0x%08X\n",
     58      vector, cause, sr );
     59  rtems_fatal_error_occurred(1);
     60}
     61
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