Changeset 7ae2775 in rtems for c/src/lib/libbsp/arm/lpc24xx


Ignore:
Timestamp:
Jul 17, 2009, 1:53:04 PM (11 years ago)
Author:
Thomas Doerfler <Thomas.Doerfler@…>
Branches:
4.10, 4.11, 5, master
Children:
ec5d4505
Parents:
9832a22
Message:

ARM bsp maintenance

Location:
c/src/lib/libbsp/arm/lpc24xx
Files:
22 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/lpc24xx/ChangeLog

    r9832a22 r7ae2775  
    44        RTEMS_BSP_BOOTCARD_OPTIONS. Add RTEMS_BSP_CLEANUP_OPTIONS so all BSPs
    55        have the same options.
     6
     72009-07-15      Sebastian Huber <sebastian.huber@embedded-brains.de>
     8
     9        * i2c/i2c.c, include/i2c.h, include/idle.h, include/io.h, misc/idle.c,
     10        misc/io.c: New files.
     11        * Makefile.am, README, configure.ac, preinstall.am,
     12        clock/clock-config.c, console/console-config.c, include/irq.h,
     13        include/dma.h, include/lpc24xx.h, include/system-clocks.h, irq/irq.c,
     14        misc/dma.c, misc/system-clocks.c, network/network.c, rtc/rtc-config.c,
     15        startup/bspreset.c, startup/bspstart.c, startup/linkcmds,
     16        startup/linkcmds.lpc2478, startup/linkcmds.lpc2478_ncs,
     17        startup/linkcmds.lpc2478_ncs_ram: Changes throughout.
    618
    7192009-02-27      Sebastian Huber <sebastian.huber@embedded-brains.de>
  • c/src/lib/libbsp/arm/lpc24xx/Makefile.am

    r9832a22 r7ae2775  
    3131include_bsp_HEADERS += ../../shared/include/irq-generic.h
    3232include_bsp_HEADERS += ../../shared/include/irq-info.h
     33include_bsp_HEADERS += ../../shared/include/stackalloc.h
    3334include_bsp_HEADERS += ../../shared/tod.h
    3435include_bsp_HEADERS += ../shared/include/linker-symbols.h
     
    4041include_bsp_HEADERS += include/ssp.h
    4142include_bsp_HEADERS += include/dma.h
     43include_bsp_HEADERS += include/idle.h
     44include_bsp_HEADERS += include/i2c.h
     45include_bsp_HEADERS += include/io.h
    4246
    4347include_HEADERS += ../../shared/include/tm27.h
     
    5458
    5559dist_project_lib_DATA += ../shared/startup/linkcmds.base \
    56         ../shared/startup/linkcmds.rom \
    5760        startup/linkcmds.lpc2478 \
    5861        startup/linkcmds.lpc2478_ncs \
     
    7780        ../../shared/gnatinstallhandler.c \
    7881        ../../shared/sbrk.c \
     82        ../../shared/src/stackalloc.c \
    7983        ../shared/abort/simple_abort.c
    8084
     
    8892        ../../shared/src/irq-info.c \
    8993        ../../shared/src/irq-shell.c \
    90         ../shared/irq/irq_asm.S \
    9194        irq/irq.c
    9295
     
    107110# Misc
    108111libbsp_a_SOURCES += misc/system-clocks.c \
    109         misc/dma.c
     112        misc/dma.c \
     113        misc/idle.c \
     114        misc/io.c
    110115
    111116# SSP
    112117libbsp_a_SOURCES += ssp/ssp.c
     118
     119# I2C
     120libbsp_a_SOURCES += i2c/i2c.c
    113121
    114122###############################################################################
  • c/src/lib/libbsp/arm/lpc24xx/README

    r9832a22 r7ae2775  
    22#  $Id$
    33#
     4
     5Note: A Binutils version with REGION_ALIAS feature is required to link the BSP.
    46
    57Development Board: QVGA Base Board from Embedded Artists
     
    1416        o SSP (SPI mode): This driver is in active development.  Use with care.
    1517        o Network
     18        o I2C
    1619
    1720Howto setup QVGA Base Board?
  • c/src/lib/libbsp/arm/lpc24xx/clock/clock-config.c

    r9832a22 r7ae2775  
    2626#include <bsp/lpc24xx.h>
    2727#include <bsp/irq.h>
     28#include <bsp/io.h>
    2829#include <bsp/system-clocks.h>
    2930
     
    5657    * (uint64_t) rtems_configuration_get_microseconds_per_tick()) / 1000000;
    5758
    58   /* Set timer pclk to cclk */
    59   rtems_interrupt_disable( level);
    60   PCONP = SET_FLAGS( PCONP, 0x02);
    61   PCLKSEL0 = SET_FLAGS( PCLKSEL0, 0x04);
    62   rtems_interrupt_enable( level);
     59  /* Enable module power */
     60  lpc24xx_module_enable( LPC24XX_MODULE_TIMER, 0, LPC24XX_MODULE_CCLK);
    6361
    6462  /* Reset timer */
  • c/src/lib/libbsp/arm/lpc24xx/configure.ac

    r9832a22 r7ae2775  
    2525
    2626RTEMS_BSPOPTS_SET([LPC24XX_OSCILLATOR_MAIN],[*],[12000000U])
    27 RTEMS_BSPOPTS_HELP([LPC24XX_OSCILLATOR_MAIN],[Main oscillator frequency in Hz])
     27RTEMS_BSPOPTS_HELP([LPC24XX_OSCILLATOR_MAIN],[main oscillator frequency in Hz])
    2828
    29 RTEMS_BSPOPTS_SET([LPC24XX_OSCILLATOR_RTC],[*],[32768])
     29RTEMS_BSPOPTS_SET([LPC24XX_OSCILLATOR_RTC],[*],[32768U])
    3030RTEMS_BSPOPTS_HELP([LPC24XX_OSCILLATOR_RTC],[RTC oscillator frequency in Hz])
    3131
    32 RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[*],[72000000])
     32RTEMS_BSPOPTS_SET([LPC24XX_CCLK],[*],[72000000U])
    3333RTEMS_BSPOPTS_HELP([LPC24XX_CCLK],[CPU clock in Hz])
    3434
    35 RTEMS_BSPOPTS_SET([LPC24XX_UART_BAUD],[*],[115200])
    36 RTEMS_BSPOPTS_HELP([LPC24XX_UART_BAUD],[Baud for UARTs])
     35RTEMS_BSPOPTS_SET([LPC24XX_UART_BAUD],[*],[115200U])
     36RTEMS_BSPOPTS_HELP([LPC24XX_UART_BAUD],[baud for UARTs])
    3737
    3838RTEMS_BSPOPTS_SET([LPC24XX_HAS_UBOOT],[lpc2478],[1])
    3939RTEMS_BSPOPTS_SET([LPC24XX_HAS_UBOOT],[lpc2478_ncs_ram],[1])
    40 RTEMS_BSPOPTS_HELP([LPC24XX_HAS_UBOOT],[Enable U-Boot startup])
     40RTEMS_BSPOPTS_HELP([LPC24XX_HAS_UBOOT],[enable U-Boot startup])
    4141
    4242RTEMS_BSPOPTS_SET([LPC24XX_ETHERNET_RMII],[lpc2478_ncs],[1])
    4343RTEMS_BSPOPTS_SET([LPC24XX_ETHERNET_RMII],[lpc2478_ncs_ram],[1])
    44 RTEMS_BSPOPTS_HELP([LPC24XX_ETHERNET_RMII],[Enable RMII for Ethernet])
     44RTEMS_BSPOPTS_HELP([LPC24XX_ETHERNET_RMII],[enable RMII for Ethernet])
    4545
    4646RTEMS_BSPOPTS_SET([LPC24XX_EMC_MICRON],[lpc2478_ncs],[1])
    47 RTEMS_BSPOPTS_HELP([LPC24XX_EMC_MICRON],[Enable RMII for Ethernet])
     47RTEMS_BSPOPTS_HELP([LPC24XX_EMC_MICRON],[use Micron configuration for EMC])
     48
     49RTEMS_BSPOPTS_SET([LPC24XX_CONFIG_CONSOLE],[*],[0])
     50RTEMS_BSPOPTS_HELP([LPC24XX_CONFIG_CONSOLE],[configuration for console (UART 0)])
     51
     52RTEMS_BSPOPTS_SET([LPC24XX_CONFIG_UART_1],[*],[])
     53RTEMS_BSPOPTS_HELP([LPC24XX_CONFIG_UART_1],[configuration for UART 1])
     54
     55RTEMS_BSPOPTS_SET([LPC24XX_CONFIG_UART_2],[*],[])
     56RTEMS_BSPOPTS_HELP([LPC24XX_CONFIG_UART_2],[configuration for UART 2])
     57
     58RTEMS_BSPOPTS_SET([LPC24XX_CONFIG_UART_3],[*],[])
     59RTEMS_BSPOPTS_HELP([LPC24XX_CONFIG_UART_3],[configuration for UART 3])
     60
     61RTEMS_BSPOPTS_SET([LPC24XX_CONFIG_I2C_0],[lpc2478_ncs_ram],[0])
     62RTEMS_BSPOPTS_HELP([LPC24XX_CONFIG_I2C_0],[configuration for I2C 0])
     63
     64RTEMS_BSPOPTS_SET([LPC24XX_CONFIG_I2C_1],[*],[])
     65RTEMS_BSPOPTS_HELP([LPC24XX_CONFIG_I2C_1],[configuration for I2C 1])
     66
     67RTEMS_BSPOPTS_SET([LPC24XX_CONFIG_I2C_2],[*],[])
     68RTEMS_BSPOPTS_HELP([LPC24XX_CONFIG_I2C_2],[configuration for I2C 2])
    4869
    4970RTEMS_BSP_BOOTCARD_OPTIONS
  • c/src/lib/libbsp/arm/lpc24xx/console/console-config.c

    r9832a22 r7ae2775  
    2626#include <bsp/irq.h>
    2727
    28 #define LPC24XX_UART_NUMBER 1
    29 
    3028static uint8_t lpc24xx_uart_register( uint32_t addr, uint8_t i)
    3129{
     
    4240}
    4341
     42rtems_device_minor_number Console_Port_Minor = 0;
     43
     44console_tbl Console_Port_Tbl [] = {
     45  #ifdef LPC24XX_CONFIG_CONSOLE
     46    {
     47      .sDeviceName = "/dev/ttyS0",
     48      .deviceType = SERIAL_NS16550,
     49      .pDeviceFns = &ns16550_fns,
     50      .deviceProbe = NULL,
     51      .pDeviceFlow = NULL,
     52      .ulMargin = 16,
     53      .ulHysteresis = 8,
     54      .pDeviceParams = (void *) LPC24XX_UART_BAUD,
     55      .ulCtrlPort1 = UART0_BASE_ADDR,
     56      .ulCtrlPort2 = 0,
     57      .ulDataPort = UART0_BASE_ADDR,
     58      .getRegister = lpc24xx_uart_register,
     59      .setRegister = lpc24xx_uart_set_register,
     60      .getData = NULL,
     61      .setData = NULL,
     62      .ulClock = LPC24XX_CCLK,
     63      .ulIntVector = LPC24XX_IRQ_UART_0
     64    },
     65  #endif
     66  #ifdef LPC24XX_CONFIG_UART_1
     67    {
     68      .sDeviceName = "/dev/ttyS1",
     69      .deviceType = SERIAL_NS16550,
     70      .pDeviceFns = &ns16550_fns,
     71      .deviceProbe = NULL,
     72      .pDeviceFlow = NULL,
     73      .ulMargin = 16,
     74      .ulHysteresis = 8,
     75      .pDeviceParams = (void *) LPC24XX_UART_BAUD,
     76      .ulCtrlPort1 = UART1_BASE_ADDR,
     77      .ulCtrlPort2 = 0,
     78      .ulDataPort = UART1_BASE_ADDR,
     79      .getRegister = lpc24xx_uart_register,
     80      .setRegister = lpc24xx_uart_set_register,
     81      .getData = NULL,
     82      .setData = NULL,
     83      .ulClock = LPC24XX_CCLK,
     84      .ulIntVector = LPC24XX_IRQ_UART_1
     85    },
     86  #endif
     87  #ifdef LPC24XX_CONFIG_UART_2
     88    {
     89      .sDeviceName = "/dev/ttyS2",
     90      .deviceType = SERIAL_NS16550,
     91      .pDeviceFns = &ns16550_fns,
     92      .deviceProbe = NULL,
     93      .pDeviceFlow = NULL,
     94      .ulMargin = 16,
     95      .ulHysteresis = 8,
     96      .pDeviceParams = (void *) LPC24XX_UART_BAUD,
     97      .ulCtrlPort1 = UART2_BASE_ADDR,
     98      .ulCtrlPort2 = 0,
     99      .ulDataPort = UART2_BASE_ADDR,
     100      .getRegister = lpc24xx_uart_register,
     101      .setRegister = lpc24xx_uart_set_register,
     102      .getData = NULL,
     103      .setData = NULL,
     104      .ulClock = LPC24XX_CCLK,
     105      .ulIntVector = LPC24XX_IRQ_UART_2
     106    },
     107  #endif
     108  #ifdef LPC24XX_CONFIG_UART_3
     109    {
     110      .sDeviceName = "/dev/ttyS3",
     111      .deviceType = SERIAL_NS16550,
     112      .pDeviceFns = &ns16550_fns,
     113      .deviceProbe = NULL,
     114      .pDeviceFlow = NULL,
     115      .ulMargin = 16,
     116      .ulHysteresis = 8,
     117      .pDeviceParams = (void *) LPC24XX_UART_BAUD,
     118      .ulCtrlPort1 = UART3_BASE_ADDR,
     119      .ulCtrlPort2 = 0,
     120      .ulDataPort = UART3_BASE_ADDR,
     121      .getRegister = lpc24xx_uart_register,
     122      .setRegister = lpc24xx_uart_set_register,
     123      .getData = NULL,
     124      .setData = NULL,
     125      .ulClock = LPC24XX_CCLK,
     126      .ulIntVector = LPC24XX_IRQ_UART_3
     127    },
     128  #endif
     129};
     130
     131#define LPC24XX_UART_NUMBER \
     132  (sizeof( Console_Port_Tbl) / sizeof( Console_Port_Tbl [0]))
     133
    44134unsigned long Console_Port_Count = LPC24XX_UART_NUMBER;
    45135
    46 rtems_device_minor_number  Console_Port_Minor = 0;
    47 
    48 console_data  Console_Port_Data [LPC24XX_UART_NUMBER];
    49 
    50 console_tbl Console_Port_Tbl [LPC24XX_UART_NUMBER] = {
    51   {
    52     .sDeviceName = "/dev/ttyS0",
    53     .deviceType = SERIAL_NS16550,
    54     .pDeviceFns = &ns16550_fns,
    55     .deviceProbe = NULL,
    56     .pDeviceFlow = NULL,
    57     .ulMargin = 16,
    58     .ulHysteresis = 8,
    59     .pDeviceParams = (void *) LPC24XX_UART_BAUD,
    60     .ulCtrlPort1 = UART0_BASE_ADDR,
    61     .ulCtrlPort2 = 0,
    62     .ulDataPort = UART0_BASE_ADDR,
    63     .getRegister = lpc24xx_uart_register,
    64     .setRegister = lpc24xx_uart_set_register,
    65     .getData = NULL,
    66     .setData = NULL,
    67     .ulClock = LPC24XX_CCLK,
    68     .ulIntVector = LPC24XX_IRQ_UART_0
    69   }
    70 };
     136console_data Console_Port_Data [LPC24XX_UART_NUMBER];
  • c/src/lib/libbsp/arm/lpc24xx/include/dma.h

    r9832a22 r7ae2775  
    88
    99/*
    10  * Copyright (c) 2008
    11  * Embedded Brains GmbH
     10 * Copyright (c) 2008, 2009
     11 * embedded brains GmbH
    1212 * Obere Lagerstr. 30
    1313 * D-82178 Puchheim
     
    2222#define LIBBSP_ARM_LPC24XX_DMA_H
    2323
    24 #include <stdbool.h>
     24#include <rtems.h>
    2525
    2626#ifdef __cplusplus
     
    2828#endif /* __cplusplus */
    2929
    30 void lpc24xx_dma_initialize( void);
     30void lpc24xx_dma_initialize(void);
    3131
    32 bool lpc24xx_dma_channel_obtain( unsigned channel);
     32rtems_status_code lpc24xx_dma_channel_obtain(unsigned channel);
    3333
    34 void lpc24xx_dma_channel_release( unsigned channel);
     34void lpc24xx_dma_channel_release(unsigned channel);
    3535
    36 void lpc24xx_dma_channel_disable( unsigned channel, bool force);
     36void lpc24xx_dma_channel_disable(unsigned channel, bool force);
    3737
    3838#ifdef __cplusplus
  • c/src/lib/libbsp/arm/lpc24xx/include/irq.h

    r9832a22 r7ae2775  
    6767#define LPC24XX_IRQ_I2S 31
    6868
     69#define LPC24XX_IRQ_PRIORITY_VALUE_MIN 0
     70#define LPC24XX_IRQ_PRIORITY_VALUE_MAX 15
     71
    6972/**
    7073 * @brief Minimum vector number.
     
    7780#define BSP_INTERRUPT_VECTOR_MAX LPC24XX_IRQ_I2S
    7881
     82void bsp_interrupt_dispatch( void);
     83
     84void lpc24xx_irq_set_priority( rtems_vector_number vector, unsigned priority);
     85
     86unsigned lpc24xx_irq_priority( rtems_vector_number vector);
     87
    7988/** @} */
    8089
  • c/src/lib/libbsp/arm/lpc24xx/include/lpc24xx.h

    r9832a22 r7ae2775  
    3939#define VICSWPrioMask  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x024))
    4040
    41 #define VICVectAddrBase ((uint32_t *) (VIC_BASE_ADDR + 0x100))
     41#define VICVectAddrBase ((volatile uint32_t *) (VIC_BASE_ADDR + 0x100))
    4242#define VICVectAddr0   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x100))
    4343#define VICVectAddr1   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x104))
     
    7373#define VICVectAddr31  (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x17C))
    7474
    75 #define VICVectPriorityBase ((uint32_t *) (VIC_BASE_ADDR + 0x200))
    76 #define VICVectPriority( i) (*((volatile uint32_t *) (VIC_BASE_ADDR + 0x200) + (i)))
     75#define VICVectPriorityBase ((volatile uint32_t *) (VIC_BASE_ADDR + 0x200))
    7776#define VICVectPriority0   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x200))
    7877#define VICVectPriority1   (*(volatile uint32_t *) (VIC_BASE_ADDR + 0x204))
     
    124123#define PINSEL9        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x24))
    125124#define PINSEL10       (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x28))
     125#define PINSEL11       (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x2C))
    126126
    127127#define PINMODE0        (*(volatile uint32_t *) (PINSEL_BASE_ADDR + 0x40))
     
    795795#define AD0GDR         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x04))
    796796#define AD0INTEN       (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x0C))
     797#define AD0_DATA_START ((volatile uint32_t *) (AD0_BASE_ADDR + 0x10))
    797798#define AD0DR0         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x10))
    798799#define AD0DR1         (*(volatile uint32_t *) (AD0_BASE_ADDR + 0x14))
     
    11221123#define MAC_MODULEID        (*(volatile uint32_t *) (MAC_BASE_ADDR + 0xFFC)) /* Module ID reg (RO) */
    11231124
     1125/* LCD Controller */   
     1126
     1127#define LCD_BASE_ADDR 0xFFE10000                               
     1128#define LCD_CFG       (*(volatile uint32_t *) 0xE01FC1B8)
     1129#define LCD_TIMH      (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x000))
     1130#define LCD_TIMV      (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x004))
     1131#define LCD_POL       (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x008))
     1132#define LCD_LE        (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x00C))
     1133#define LCD_UPBASE    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x010))
     1134#define LCD_LPBASE    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x014))
     1135#define LCD_CTRL      (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x018))
     1136#define LCD_INTMSK    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x01C))
     1137#define LCD_INTRAW    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x020))
     1138#define LCD_INTSTAT   (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x024))
     1139#define LCD_INTCLR    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x028))
     1140#define LCD_UPCURR    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x02C))
     1141#define LCD_LPCURR    (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x030))
     1142#define LCD_PAL_ADDR  (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x200))
     1143#define CRSR_IMG      (*(volatile uint32_t *) (LCD_BASE_ADDR + 0x800))
     1144#define CRSR_CTLR     (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC00))
     1145#define CRSR_CFG      (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC04))
     1146#define CRSR_PAL0     (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC08))
     1147#define CRSR_PAL1     (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC0C))
     1148#define CRSR_XY       (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC10))
     1149#define CRSR_CLIP     (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC14))
     1150#define CRSR_INTMSK   (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC20))
     1151#define CRSR_INTCLR   (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC24))
     1152#define CRSR_INTRAW   (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC28))
     1153#define CRSR_INTSTAT  (*(volatile uint32_t *) (LCD_BASE_ADDR + 0xC2C))
     1154
    11241155/* Register Fields */
    1125 
    1126 /* PCONP */
    1127 
    1128 #define PCONP_PCTIM0 0x00000002U
    1129 
    1130 #define PCONP_PCTIM1 0x00000004U
    1131 
    1132 #define PCONP_PCUART0 0x00000008U
    1133 
    1134 #define PCONP_PCUART1 0x00000010U
    1135 
    1136 #define PCONP_PCPWM0 0x00000020U
    1137 
    1138 #define PCONP_PCPWM1 0x00000040U
    1139 
    1140 #define PCONP_PCI2C0 0x00000080U
    1141 
    1142 #define PCONP_PCSPI 0x00000100U
    1143 
    1144 #define PCONP_PCRTC 0x00000200U
    1145 
    1146 #define PCONP_PCSSP1 0x00000400U
    1147 
    1148 #define PCONP_PCEMC 0x00000800U
    1149 
    1150 #define PCONP_PCAD 0x00001000U
    1151 
    1152 #define PCONP_PCCAN1 0x00002000U
    1153 
    1154 #define PCONP_PCCAN2 0x00004000U
    1155 
    1156 #define PCONP_PCI2C1 0x00080000U
    1157 
    1158 #define PCONP_PCLCD 0x00100000U
    1159 
    1160 #define PCONP_PCSSP0 0x00200000U
    1161 
    1162 #define PCONP_PCTIM2 0x00400000U
    1163 
    1164 #define PCONP_PCTIM3 0x00800000U
    1165 
    1166 #define PCONP_PCUART2 0x01000000U
    1167 
    1168 #define PCONP_PCUART3 0x02000000U
    1169 
    1170 #define PCONP_PCI2C2 0x04000000U
    1171 
    1172 #define PCONP_PCI2S 0x08000000U
    1173 
    1174 #define PCONP_PCSDC 0x10000000U
    1175 
    1176 #define PCONP_PCGPDMA 0x20000000U
    1177 
    1178 #define PCONP_PCENET 0x40000000U
    1179 
    1180 #define PCONP_PCUSB 0x80000000U
    11811156
    11821157/* CLKSRCSEL */
     
    20231998#define ETH_CMD_FULL_DUPLEX 0x00000400U
    20241999
     2000/* ETH_STAT */
     2001
     2002#define ETH_STAT_RX_ACTIVE 0x00000001U
     2003
     2004#define ETH_STAT_TX_ACTIVE 0x00000002U
     2005
    20252006/* AHBCFG */
    20262007
     
    21072088#define EMC_DYN_CTRL_CMD_NOP 0x00000180U
    21082089
     2090/* I2C */
     2091
     2092typedef struct {
     2093  uint32_t conset;
     2094  uint32_t stat;
     2095  uint32_t dat;
     2096  uint32_t adr;
     2097  uint32_t sclh;
     2098  uint32_t scll;
     2099  uint32_t conclr;
     2100} lpc24xx_i2c;
     2101
     2102#define LPC24XX_I2C_AA (1U << 2U)
     2103
     2104#define LPC24XX_I2C_SI (1U << 3U)
     2105
     2106#define LPC24XX_I2C_STO (1U << 4U)
     2107
     2108#define LPC24XX_I2C_STA (1U << 5U)
     2109
     2110#define LPC24XX_I2C_EN (1U << 6U)
     2111
     2112/* IO */
     2113
     2114typedef struct {
     2115  uint32_t dir;
     2116  uint32_t reserved [3];
     2117  uint32_t mask;
     2118  uint32_t pin;
     2119  uint32_t set;
     2120  uint32_t clr;
     2121} lpc24xx_fio;
     2122
     2123static volatile uint32_t * const LPC24XX_PINSEL = &PINSEL0;
     2124
     2125static volatile uint32_t * const LPC24XX_PINMODE = &PINMODE0;
     2126
     2127static volatile lpc24xx_fio * const LPC24XX_FIO = (volatile lpc24xx_fio *) FIO_BASE_ADDR;
     2128
    21092129#endif /* LIBBSP_ARM_LPC24XX_LPC24XX_H */
  • c/src/lib/libbsp/arm/lpc24xx/include/system-clocks.h

    r9832a22 r7ae2775  
    2828void lpc24xx_micro_seconds_delay( unsigned us);
    2929
     30unsigned lpc24xx_pllclk( void);
     31
    3032unsigned lpc24xx_cclk( void);
    3133
  • c/src/lib/libbsp/arm/lpc24xx/irq/irq.c

    r9832a22 r7ae2775  
    88
    99/*
    10  * Copyright (c) 2008
    11  * Embedded Brains GmbH
     10 * Copyright (c) 2008, 2009
     11 * embedded brains GmbH
    1212 * Obere Lagerstr. 30
    1313 * D-82178 Puchheim
     
    2424#include <bsp/lpc24xx.h>
    2525
    26 void ExecuteITHandler( void)
     26static inline bool lpc24xx_irq_is_valid( rtems_vector_number vector)
     27{
     28  return vector <= BSP_INTERRUPT_VECTOR_MAX;
     29}
     30
     31void lpc24xx_irq_set_priority( rtems_vector_number vector, unsigned priority)
     32{
     33  if (lpc24xx_irq_is_valid( vector)) {
     34    if (priority > LPC24XX_IRQ_PRIORITY_VALUE_MAX) {
     35      priority = LPC24XX_IRQ_PRIORITY_VALUE_MAX;
     36    }
     37
     38    VICVectPriorityBase [vector] = priority;
     39  }
     40}
     41
     42unsigned lpc24xx_irq_priority( rtems_vector_number vector)
     43{
     44  if (lpc24xx_irq_is_valid( vector)) {
     45    return VICVectPriorityBase [vector];
     46  } else {
     47    return LPC24XX_IRQ_PRIORITY_VALUE_MIN - 1;
     48  }
     49}
     50
     51void bsp_interrupt_dispatch( void)
    2752{
    2853  /* Read current vector number */
    2954  rtems_vector_number vector = VICVectAddr;
    3055
    31   /* Acknowledge interrupt */
    32   VICVectAddr = 0;
     56  /* Enable interrupts in program status register */
     57  uint32_t psr = arm_status_irq_enable();
    3358
    3459  /* Dispatch interrupt handlers */
    3560  bsp_interrupt_handler_dispatch( vector);
     61
     62  /* Restore program status register */
     63  arm_status_restore( psr);
     64
     65  /* Acknowledge interrupt */
     66  VICVectAddr = 0;
    3667}
    3768
    3869rtems_status_code bsp_interrupt_vector_enable( rtems_vector_number vector)
    3970{
    40   VICIntEnable = 1U << vector;
     71  if (lpc24xx_irq_is_valid( vector)) {
     72    VICIntEnable = 1U << vector;
     73  }
    4174
    4275  return RTEMS_SUCCESSFUL;
     
    4578rtems_status_code bsp_interrupt_vector_disable( rtems_vector_number vector)
    4679{
    47   VICIntEnClear = 1U << vector;
     80  if (lpc24xx_irq_is_valid( vector)) {
     81    VICIntEnClear = 1U << vector;
     82  }
    4883
    4984  return RTEMS_SUCCESSFUL;
    5085}
     86
     87/* FIXME */
     88void arm_exc_interrupt( void);
    5189
    5290rtems_status_code bsp_interrupt_facility_initialize( void)
     
    80118
    81119  /* Install the IRQ exception handler */
    82   _CPU_ISR_install_vector( ARM_EXCEPTION_IRQ, _ISR_Handler, NULL);
     120  _CPU_ISR_install_vector( ARM_EXCEPTION_IRQ, arm_exc_interrupt, NULL);
    83121
    84122  return RTEMS_SUCCESSFUL;
     
    87125void bsp_interrupt_handler_default( rtems_vector_number vector)
    88126{
    89   printk( "Spurious interrupt: %u\n", vector);
     127  printk( "spurious interrupt: %u\n", vector);
    90128}
  • c/src/lib/libbsp/arm/lpc24xx/misc/dma.c

    r9832a22 r7ae2775  
    88
    99/*
    10  * Copyright (c) 2008
    11  * Embedded Brains GmbH
     10 * Copyright (c) 2008, 2009
     11 * embedded brains GmbH
    1212 * Obere Lagerstr. 30
    1313 * D-82178 Puchheim
     
    2323#include <bsp/lpc24xx.h>
    2424#include <bsp/dma.h>
     25#include <bsp/io.h>
    2526
    2627/**
     
    3233 * @brief Initializes the general purpose DMA.
    3334 */
    34 void lpc24xx_dma_initialize( void)
     35void lpc24xx_dma_initialize(void)
    3536{
    3637  rtems_interrupt_level level;
    3738
    38   /* Enable power */
    39   rtems_interrupt_disable( level);
    40   PCONP = SET_FLAG( PCONP, PCONP_PCGPDMA);
    41   rtems_interrupt_enable( level);
     39  /* Enable module power */
     40  lpc24xx_module_enable(LPC24XX_MODULE_GPDMA, 0, LPC24XX_MODULE_PCLK_DEFAULT);
    4241
    4342  /* Disable module */
     
    6059
    6160/**
    62  * @brief Returns true if the channel @a channel was obtained.
     61 * @brief Tries to obtain the channel @a channel.
    6362 *
    64  * If the channel number @a channel is out of range the last valid channel will
    65  * be used.
     63 * @retval RTEMS_SUCCESSFUL Successful operation.
     64 * @retval RTEMS_INVALID_ID Invalid channel number.
     65 * @retval RTEMS_RESOURCE_IN_USE Channel already occupied.
    6666 */
    67 bool lpc24xx_dma_channel_obtain( unsigned channel)
     67rtems_status_code lpc24xx_dma_channel_obtain(unsigned channel)
    6868{
    69   rtems_interrupt_level level;
    70   bool occupation = true;
     69  if (channel < GPDMA_CH_NUMBER) {
     70    rtems_interrupt_level level;
     71    bool occupation = true;
    7172
    72   if (channel > GPDMA_CH_NUMBER) {
    73     channel = GPDMA_CH_NUMBER - 1;
     73    rtems_interrupt_disable(level);
     74    occupation = lpc24xx_dma_channel_occupation [channel];
     75    lpc24xx_dma_channel_occupation [channel] = true;
     76    rtems_interrupt_enable(level);
     77
     78    return occupation ? RTEMS_RESOURCE_IN_USE : RTEMS_SUCCESSFUL;
     79  } else {
     80    return RTEMS_INVALID_ID;
    7481  }
    75 
    76   rtems_interrupt_disable( level);
    77   occupation = lpc24xx_dma_channel_occupation [channel];
    78   lpc24xx_dma_channel_occupation [channel] = true;
    79   rtems_interrupt_enable( level);
    80 
    81   return !occupation;
    8282}
    8383
    8484/**
    85  * @brief Releases the channel @a channel.  You must have obtained this channel
    86  * with lpc24xx_dma_channel_obtain() previously.
     85 * @brief Releases the channel @a channel.
    8786 *
    88  * If the channel number @a channel is out of range the last valid channel will
    89  * be used.
     87 * You must have obtained this channel with lpc24xx_dma_channel_obtain()
     88 * previously.
     89 *
     90 * If the channel number @a channel is out of range nothing will happen.
    9091 */
    91 void lpc24xx_dma_channel_release( unsigned channel)
     92void lpc24xx_dma_channel_release(unsigned channel)
    9293{
    93   if (channel > GPDMA_CH_NUMBER) {
    94     channel = GPDMA_CH_NUMBER - 1;
     94  if (channel < GPDMA_CH_NUMBER) {
     95    lpc24xx_dma_channel_occupation [channel] = false;
    9596  }
    96 
    97   lpc24xx_dma_channel_occupation [channel] = false;
    9897}
    9998
     
    102101 *
    103102 * If @a force is false the channel will be halted and disabled when the
    104  * channel is inactive.  If the channel number @a channel is out of range the
    105  * last valid channel will be used.
     103 * channel is inactive.
     104 *
     105 * If the channel number @a channel is out of range the behaviour is undefined.
    106106 */
    107 void lpc24xx_dma_channel_disable( unsigned channel, bool force)
     107void lpc24xx_dma_channel_disable(unsigned channel, bool force)
    108108{
    109   volatile lpc24xx_dma_channel *ch = GPDMA_CH_BASE_ADDR( channel);
     109  volatile lpc24xx_dma_channel *ch = GPDMA_CH_BASE_ADDR(channel);
    110110  uint32_t cfg = ch->cfg;
    111111
    112112  if (!force) {
    113113    /* Halt */
    114     ch->cfg = SET_FLAG( cfg, GPDMA_CH_CFG_HALT);
     114    ch->cfg = SET_FLAG(cfg, GPDMA_CH_CFG_HALT);
    115115
    116116    /* Wait for inactive */
    117117    do {
    118118      cfg = ch->cfg;
    119     } while (IS_FLAG_SET( cfg, GPDMA_CH_CFG_ACTIVE));
     119    } while (IS_FLAG_SET(cfg, GPDMA_CH_CFG_ACTIVE));
    120120  }
    121121
    122122  /* Disable */
    123   ch->cfg = CLEAR_FLAG( cfg, GPDMA_CH_CFG_EN);
     123  ch->cfg = CLEAR_FLAG(cfg, GPDMA_CH_CFG_EN);
    124124}
  • c/src/lib/libbsp/arm/lpc24xx/misc/system-clocks.c

    r9832a22 r7ae2775  
    6969
    7070/**
    71  * @brief Returns the CPU clock frequency in [Hz].
     71 * @brief Returns the PLL output clock frequency in [Hz].
    7272 *
    73  * Return zero in case of an unexpected PLL input frequency.
     73 * Returns zero in case of an unexpected PLL input frequency.
    7474 */
    75 unsigned lpc24xx_cclk( void)
     75unsigned lpc24xx_pllclk( void)
    7676{
    7777  unsigned clksrc = GET_CLKSRCSEL_CLKSRC( CLKSRCSEL);
    7878  unsigned pllinclk = 0;
    7979  unsigned pllclk = 0;
    80   unsigned cclk = 0;
    8180
    8281  /* Get PLL input frequency */
     
    106105  }
    107106
    108   /* Get CPU clock frequency */
    109   cclk = pllclk / (GET_CCLKCFG_CCLKSEL( CCLKCFG) + 1);
     107  return pllclk;
     108}
     109
     110/**
     111 * @brief Returns the CPU clock frequency in [Hz].
     112 *
     113 * Returns zero in case of an unexpected PLL input frequency.
     114 */
     115unsigned lpc24xx_cclk( void)
     116{
     117  /* Get PLL output frequency */
     118  unsigned pllclk = lpc24xx_pllclk();
     119
     120  /* Get CPU frequency */
     121  unsigned cclk = pllclk / (GET_CCLKCFG_CCLKSEL( CCLKCFG) + 1);
    110122
    111123  return cclk;
  • c/src/lib/libbsp/arm/lpc24xx/network/network.c

    r9832a22 r7ae2775  
    4444#include <bsp/lpc24xx.h>
    4545#include <bsp/irq.h>
     46#include <bsp/io.h>
    4647#include <bsp/utility.h>
    4748
     
    142143    + LPC24XX_ETH_TRANSMIT_UNIT_NUMBER * ETH_TRANSMIT_STATUS_SIZE)
    143144
    144 #define LPC24XX_ETH_EVENT_TRANSMIT RTEMS_EVENT_1
    145 
    146 #define LPC24XX_ETH_EVENT_TRANSMIT_START RTEMS_EVENT_2
    147 
    148 #define LPC24XX_ETH_EVENT_TRANSMIT_ERROR RTEMS_EVENT_3
    149 
    150 #define LPC24XX_ETH_EVENT_RECEIVE RTEMS_EVENT_4
    151 
    152 #define LPC24XX_ETH_EVENT_RECEIVE_ERROR RTEMS_EVENT_5
    153 
    154 #define LPC24XX_ETH_TIMEOUT 10
     145#define LPC24XX_ETH_EVENT_INITIALIZE RTEMS_EVENT_1
     146
     147#define LPC24XX_ETH_EVENT_START RTEMS_EVENT_2
     148
     149#define LPC24XX_ETH_EVENT_INTERRUPT RTEMS_EVENT_3
    155150
    156151#define LPC24XX_ETH_INTERRUPT_RECEIVE \
    157152  (ETH_INT_RX_ERROR | ETH_INT_RX_FINISHED | ETH_INT_RX_DONE)
    158153
    159 #define LPC24XX_ETH_INTERRUPT_TRANSMIT (ETH_INT_TX_DONE | ETH_INT_TX_FINISHED | ETH_INT_TX_ERROR)
     154#define LPC24XX_ETH_INTERRUPT_TRANSMIT \
     155  (ETH_INT_TX_DONE | ETH_INT_TX_FINISHED | ETH_INT_TX_ERROR)
    160156
    161157#define LPC24XX_ETH_RX_STAT_ERRORS \
     
    273269  /* Check receive interrupts */
    274270  if (IS_FLAG_SET( is, ETH_INT_RX_OVERRUN)) {
    275     re = LPC24XX_ETH_EVENT_RECEIVE_ERROR;
     271    re = LPC24XX_ETH_EVENT_INITIALIZE;
    276272    ++e->receive_fatal_errors;
    277     /* FIXME */
    278     printk( "%s: fatal receive error\n", __func__);
    279     while (1);
    280273  } else if (IS_ANY_FLAG_SET( is, LPC24XX_ETH_INTERRUPT_RECEIVE)) {
    281     re = LPC24XX_ETH_EVENT_RECEIVE;
     274    re = LPC24XX_ETH_EVENT_INTERRUPT;
    282275    ie = SET_FLAGS( ie, LPC24XX_ETH_INTERRUPT_RECEIVE);
    283276  }
     
    291284  /* Check transmit interrupts */
    292285  if (IS_FLAG_SET( is, ETH_INT_TX_UNDERRUN)) {
    293     te = LPC24XX_ETH_EVENT_TRANSMIT_ERROR;
     286    te = LPC24XX_ETH_EVENT_INITIALIZE;
    294287    ++e->transmit_fatal_errors;
    295     /* FIXME */
    296     printk( "%s: fatal transmit error\n", __func__);
    297     while (1);
    298288  } else if (IS_ANY_FLAG_SET( is, LPC24XX_ETH_INTERRUPT_TRANSMIT)) {
    299     te = LPC24XX_ETH_EVENT_TRANSMIT;
     289    te = LPC24XX_ETH_EVENT_INTERRUPT;
    300290    ie = SET_FLAGS( ie, LPC24XX_ETH_INTERRUPT_TRANSMIT);
    301291  }
     
    380370  volatile lpc24xx_eth_transfer_descriptor *desc,
    381371  struct mbuf **mbuf_table,
    382   unsigned i,
     372  uint32_t i,
    383373  bool wait
    384374)
     
    417407  struct mbuf **const mbuf_table =
    418408    (struct mbuf **) LPC24XX_ETH_RECEIVE_MBUF_START;
    419   uint32_t index_max = e->receive_unit_number - 1;
     409  uint32_t index_max = 0;
    420410  uint32_t produce_index = 0;
    421411  uint32_t consume_index = 0;
     
    424414  LPC24XX_ETH_PRINTF( "%s\n", __func__);
    425415
    426   /* Disable receive interrupts */
    427   lpc24xx_eth_disable_receive_interrupts();
    428 
    429   /* Disable receiver */
    430   MAC_COMMAND = CLEAR_FLAG( MAC_COMMAND, ETH_CMD_RX_ENABLE);
    431 
    432   /* Clear receive interrupts */
    433   MAC_INTCLEAR = LPC24XX_ETH_INTERRUPT_RECEIVE;
    434 
    435   /* Fill receive queue */
    436   for (produce_index = 0; produce_index <= index_max; ++produce_index) {
    437     if (
    438       !lpc24xx_eth_add_new_mbuf( ifp, desc, mbuf_table, produce_index, false)
    439     ) {
    440       break;
    441     }
    442   }
    443 
    444   /* Check if the queue is full */
    445   if (produce_index == 0) {
    446     RTEMS_DO_CLEANUP(
    447       cleanup,
    448       "no buffers to fill receive queue: terminate receive task\n"
    449     );
    450   } else if (produce_index <= index_max) {
    451     /* Reduce the queue size */
    452     index_max = produce_index - 1;
    453 
    454     RTEMS_SYSLOG_ERROR( "not enough buffers to fill receive queue");
    455   }
    456 
    457   /* Receive descriptor table */
    458   MAC_RXDESCRIPTORNUM = index_max;
    459   MAC_RXDESCRIPTOR = (uint32_t) desc;
    460   MAC_RXSTATUS = (uint32_t) info;
    461 
    462   /* Initialize indices */
    463   produce_index = MAC_RXPRODUCEINDEX;
    464   consume_index = MAC_RXCONSUMEINDEX;
    465   receive_index = consume_index;
    466 
    467   /* Enable receiver */
    468   MAC_COMMAND = SET_FLAG( MAC_COMMAND, ETH_CMD_RX_ENABLE);
    469 
    470   /* Enable receive interrupts */
    471   lpc24xx_eth_enable_receive_interrupts();
    472 
    473416  /* Main event loop */
    474417  while (true) {
     
    477420    /* Wait for events */
    478421    sc = rtems_bsdnet_event_receive(
    479       LPC24XX_ETH_EVENT_RECEIVE,
     422      LPC24XX_ETH_EVENT_INITIALIZE | LPC24XX_ETH_EVENT_INTERRUPT,
    480423      RTEMS_EVENT_ANY | RTEMS_WAIT,
    481424      RTEMS_NO_TIMEOUT,
     
    486429    LPC24XX_ETH_PRINTF( "rx: wake up: 0x%08" PRIx32 "\n", events);
    487430
     431    /* Initialize receiver? */
     432    if (IS_FLAG_SET( events, LPC24XX_ETH_EVENT_INITIALIZE)) {
     433      /* Disable receive interrupts */
     434      lpc24xx_eth_disable_receive_interrupts();
     435
     436      /* Disable receiver */
     437      MAC_COMMAND = CLEAR_FLAG( MAC_COMMAND, ETH_CMD_RX_ENABLE);
     438
     439      /* Wait for inactive status */
     440      while (IS_FLAG_SET( MAC_STATUS, ETH_STAT_RX_ACTIVE)) {
     441        /* Wait */
     442      }
     443
     444      /* Reset */
     445      MAC_COMMAND = SET_FLAG( MAC_COMMAND, ETH_CMD_RX_RESET);
     446
     447      /* Clear receive interrupts */
     448      MAC_INTCLEAR = LPC24XX_ETH_INTERRUPT_RECEIVE;
     449
     450      /* Index maximum (determines queue size) */
     451      index_max = e->receive_unit_number - 1;
     452
     453      /* Move existing mbufs to the front */
     454      consume_index = 0;
     455      for (produce_index = 0; produce_index <= index_max; ++produce_index) {
     456        if (mbuf_table [produce_index] != NULL) {
     457          mbuf_table [consume_index] = mbuf_table [produce_index];
     458          ++consume_index;
     459        }
     460      }
     461
     462      /* Fill receive queue */
     463      for (produce_index = consume_index; produce_index <= index_max; ++produce_index) {
     464        if (
     465          !lpc24xx_eth_add_new_mbuf( ifp, desc, mbuf_table, produce_index, false)
     466        ) {
     467          break;
     468        }
     469      }
     470
     471      /* Check if the queue is full */
     472      if (produce_index == 0) {
     473        RTEMS_DO_CLEANUP(
     474          cleanup,
     475          "no mbufs to fill receive queue: terminate receive task\n"
     476        );
     477      } else if (produce_index <= index_max) {
     478        /* Reduce the queue size */
     479        index_max = produce_index - 1;
     480
     481        RTEMS_SYSLOG_ERROR( "not enough mbufs to fill receive queue");
     482      }
     483
     484      /* Receive descriptor table */
     485      MAC_RXDESCRIPTORNUM = index_max;
     486      MAC_RXDESCRIPTOR = (uint32_t) desc;
     487      MAC_RXSTATUS = (uint32_t) info;
     488
     489      /* Initialize indices */
     490      produce_index = MAC_RXPRODUCEINDEX;
     491      consume_index = MAC_RXCONSUMEINDEX;
     492      receive_index = consume_index;
     493
     494      /* Enable receiver */
     495      MAC_COMMAND = SET_FLAG( MAC_COMMAND, ETH_CMD_RX_ENABLE);
     496
     497      /* Enable receive interrupts */
     498      lpc24xx_eth_enable_receive_interrupts();
     499
     500      /* Wait for events */
     501      continue;
     502    }
     503
    488504    while (true) {
    489505      /* Clear receive interrupt status */
     
    497513        struct mbuf *m = mbuf_table [receive_index];
    498514        uint32_t stat = info [receive_index].status;
     515
     516        /* Remove mbuf from table */
     517        mbuf_table [receive_index] = NULL;
    499518
    500519        if (
     
    586605cleanup:
    587606
     607  /* Clear task ID */
     608  e->receive_task = RTEMS_ID_NONE;
     609
    588610  /* Release network semaphore */
    589611  rtems_bsdnet_semaphore_release();
     
    666688  LPC24XX_ETH_PRINTF( "%s\n", __func__);
    667689
    668   /* Disable transmit interrupts */
    669   lpc24xx_eth_disable_transmit_interrupts();
    670 
    671   /* Disable transmitter */
    672   MAC_COMMAND = CLEAR_FLAG( MAC_COMMAND, ETH_CMD_TX_ENABLE);
    673 
    674   /* Clear transmit interrupts */
    675   MAC_INTCLEAR = LPC24XX_ETH_INTERRUPT_TRANSMIT;
    676 
    677690  /* Initialize descriptor table */
    678691  for (produce_index = 0; produce_index <= index_max; ++produce_index) {
    679692    desc [produce_index].start =
    680693      (uint32_t) (buf + produce_index * LPC24XX_ETH_TRANSMIT_BUFFER_SIZE);
    681     desc [produce_index].control = 0;
    682   }
    683 
    684   /* Transmit descriptors */
    685   MAC_TXDESCRIPTORNUM = index_max;
    686   MAC_TXDESCRIPTOR = (uint32_t) desc;
    687   MAC_TXSTATUS = (uint32_t) status;
    688 
    689   /* Initialize indices */
    690   produce_index = MAC_TXPRODUCEINDEX;
    691   consume_index = MAC_TXCONSUMEINDEX;
    692 
    693   /* Frame buffer start */
    694   frame_buffer = (char *) desc [produce_index].start;
    695 
    696   /* Enable transmitter */
    697   MAC_COMMAND = SET_FLAG( MAC_COMMAND, ETH_CMD_TX_ENABLE);
     694  }
    698695
    699696  /* Main event loop */
     
    701698    /* Wait for events */
    702699    sc = rtems_bsdnet_event_receive(
    703       LPC24XX_ETH_EVENT_TRANSMIT | LPC24XX_ETH_EVENT_TRANSMIT_START,
     700      LPC24XX_ETH_EVENT_INITIALIZE
     701        | LPC24XX_ETH_EVENT_START
     702        | LPC24XX_ETH_EVENT_INTERRUPT,
    704703      RTEMS_EVENT_ANY | RTEMS_WAIT,
    705704      RTEMS_NO_TIMEOUT,
     
    709708
    710709    LPC24XX_ETH_PRINTF( "tx: wake up: 0x%08" PRIx32 "\n", events);
     710
     711    /* Initialize transmitter? */
     712    if (IS_FLAG_SET( events, LPC24XX_ETH_EVENT_INITIALIZE)) {
     713      /* Disable transmit interrupts */
     714      lpc24xx_eth_disable_transmit_interrupts();
     715
     716      /* Disable transmitter */
     717      MAC_COMMAND = CLEAR_FLAG( MAC_COMMAND, ETH_CMD_TX_ENABLE);
     718
     719      /* Wait for inactive status */
     720      while (IS_FLAG_SET( MAC_STATUS, ETH_STAT_TX_ACTIVE)) {
     721        /* Wait */
     722      }
     723
     724      /* Reset */
     725      MAC_COMMAND = SET_FLAG( MAC_COMMAND, ETH_CMD_TX_RESET);
     726
     727      /* Clear transmit interrupts */
     728      MAC_INTCLEAR = LPC24XX_ETH_INTERRUPT_TRANSMIT;
     729
     730      /* Transmit descriptors */
     731      MAC_TXDESCRIPTORNUM = index_max;
     732      MAC_TXDESCRIPTOR = (uint32_t) desc;
     733      MAC_TXSTATUS = (uint32_t) status;
     734
     735      /* Initialize indices */
     736      produce_index = MAC_TXPRODUCEINDEX;
     737      consume_index = MAC_TXCONSUMEINDEX;
     738
     739      /* Frame buffer start */
     740      frame_buffer = (char *) desc [produce_index].start;
     741
     742      /* Enable transmitter */
     743      MAC_COMMAND = SET_FLAG( MAC_COMMAND, ETH_CMD_TX_ENABLE);
     744    }
    711745
    712746    /* Free consumed fragments */
     
    750784        }
    751785
    752         /* Reinitialize control field */
    753         desc [c].control = 0;
    754 
    755786        /* Next consume index */
    756787        c = lpc24xx_eth_increment( c, index_max);
     
    850881cleanup:
    851882
     883  /* Clear task ID */
     884  e->transmit_task = RTEMS_ID_NONE;
     885
    852886  /* Release network semaphore */
    853887  rtems_bsdnet_semaphore_release();
     
    859893static void lpc24xx_eth_interface_init( void *arg)
    860894{
     895  rtems_status_code sc = RTEMS_SUCCESSFUL;
    861896  lpc24xx_eth_driver_entry *e = (lpc24xx_eth_driver_entry *) arg;
    862897  struct ifnet *ifp = &e->arpcom.ac_if;
     
    866901  if (e->state == LPC24XX_ETH_INITIALIZED) {
    867902    #ifndef LPC24XX_HAS_UBOOT
    868       rtems_interrupt_level level;
    869 
    870       rtems_interrupt_disable( level);
    871 
    872       /* Enable power */
    873       PCONP = SET_FLAGS( PCONP, 0x40000000);
    874 
    875       /* Set PIN selects */
     903      /* Enable module power */
     904      lpc24xx_module_enable(
     905        LPC24XX_MODULE_ETHERNET,
     906        0,
     907        LPC24XX_MODULE_PCLK_DEFAULT
     908      );
     909
     910      /* Module IO configuration */
    876911      #ifdef LPC24XX_ETHERNET_RMII
    877         PINSEL2 = SET_FLAGS( PINSEL2, 0x55555555);
     912        lpc24xx_io_config( LPC24XX_MODULE_ETHERNET, 0, 0);
    878913      #else
    879         PINSEL2 = SET_FLAGS( PINSEL2, 0x50150105);
     914        lpc24xx_io_config( LPC24XX_MODULE_ETHERNET, 0, 1);
    880915      #endif
    881       PINSEL3 = SET_FLAGS( PINSEL3, 0x05);
    882 
    883       rtems_interrupt_enable( level);
    884916
    885917      /* Soft reset */
    886918
    887919      /* Do soft reset */
     920      MAC_COMMAND = 0x38;
    888921      MAC_MAC1 = 0xcf00;
    889       MAC_COMMAND = 0x38;
    890922
    891923      /* Initialize PHY */
     
    920952      MAC_MAC1 = 0x03;
    921953    #else /* LPC24XX_HAS_UBOOT */
    922       uint32_t reg = 0;
    923 
    924       /* TODO */
     954      /* Reset receiver and transmitter */
     955      MAC_COMMAND = SET_FLAGS(
     956        MAC_COMMAND,
     957        ETH_CMD_RX_RESET | ETH_CMD_TX_RESET | ETH_CMD_REG_RESET
     958      );
    925959
    926960      /* MAC configuration */
    927961      MAC_MAC1 = 0x3;
    928 
    929       /* Disable and reset receiver and transmitter */
    930       reg = MAC_COMMAND;
    931       reg = CLEAR_FLAGS( reg, ETH_CMD_RX_ENABLE | ETH_CMD_TX_ENABLE);
    932       reg = SET_FLAGS( reg, ETH_CMD_RX_RESET | ETH_CMD_TX_RESET);
    933       MAC_COMMAND = reg;
    934962    #endif /* LPC24XX_HAS_UBOOT */
    935963
     
    942970        e
    943971      );
     972      sc = rtems_event_send( e->receive_task, LPC24XX_ETH_EVENT_INITIALIZE);
     973      RTEMS_SYSLOG_ERROR_SC( sc, "send receive initialize event");
    944974    }
    945975
     
    952982        e
    953983      );
     984      sc = rtems_event_send( e->transmit_task, LPC24XX_ETH_EVENT_INITIALIZE);
     985      RTEMS_SYSLOG_ERROR_SC( sc, "send transmit initialize event");
    954986    }
    955987
     
    9841016static void lpc24xx_eth_interface_stats( const lpc24xx_eth_driver_entry *e)
    9851017{
     1018  rtems_bsdnet_semaphore_release();
     1019
    9861020  printf( "received frames:                     %u\n", e->received_frames);
    9871021  printf( "receive interrupts:                  %u\n", e->receive_interrupts);
     
    10031037  printf( "transmit overflow errors:            %u\n", e->transmit_overflow_errors);
    10041038  printf( "transmit fatal errors:               %u\n", e->transmit_fatal_errors);
     1039
     1040  rtems_bsdnet_semaphore_obtain();
    10051041}
    10061042
     
    10521088  ifp->if_flags = SET_FLAG( ifp->if_flags, IFF_OACTIVE);
    10531089
    1054   sc = rtems_event_send( e->transmit_task, LPC24XX_ETH_EVENT_TRANSMIT_START);
     1090  sc = rtems_event_send( e->transmit_task, LPC24XX_ETH_EVENT_START);
    10551091  RTEMS_SYSLOG_ERROR_SC( sc, "send transmit start event");
    10561092}
  • c/src/lib/libbsp/arm/lpc24xx/preinstall.am

    r9832a22 r7ae2775  
    6666PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/irq-info.h
    6767
     68$(PROJECT_INCLUDE)/bsp/stackalloc.h: ../../shared/include/stackalloc.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     69        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/stackalloc.h
     70PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/stackalloc.h
     71
    6872$(PROJECT_INCLUDE)/bsp/tod.h: ../../shared/tod.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
    6973        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/tod.h
     
    102106PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/dma.h
    103107
     108$(PROJECT_INCLUDE)/bsp/idle.h: include/idle.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     109        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/idle.h
     110PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/idle.h
     111
     112$(PROJECT_INCLUDE)/bsp/i2c.h: include/i2c.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     113        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/i2c.h
     114PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/i2c.h
     115
     116$(PROJECT_INCLUDE)/bsp/io.h: include/io.h $(PROJECT_INCLUDE)/bsp/$(dirstamp)
     117        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/bsp/io.h
     118PREINSTALL_FILES += $(PROJECT_INCLUDE)/bsp/io.h
     119
    104120$(PROJECT_INCLUDE)/tm27.h: ../../shared/include/tm27.h $(PROJECT_INCLUDE)/$(dirstamp)
    105121        $(INSTALL_DATA) $< $(PROJECT_INCLUDE)/tm27.h
     
    113129        $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.base
    114130PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.base
    115 
    116 $(PROJECT_LIB)/linkcmds.rom: ../shared/startup/linkcmds.rom $(PROJECT_LIB)/$(dirstamp)
    117         $(INSTALL_DATA) $< $(PROJECT_LIB)/linkcmds.rom
    118 PREINSTALL_FILES += $(PROJECT_LIB)/linkcmds.rom
    119131
    120132$(PROJECT_LIB)/linkcmds.lpc2478: startup/linkcmds.lpc2478 $(PROJECT_LIB)/$(dirstamp)
  • c/src/lib/libbsp/arm/lpc24xx/rtc/rtc-config.c

    r9832a22 r7ae2775  
    2222
    2323#include <bsp/lpc24xx.h>
     24#include <bsp/io.h>
    2425
    2526#define LPC24XX_RTC_NUMBER 1
     
    2728static void lpc24xx_rtc_initialize( int minor)
    2829{
     30  rtems_interrupt_level level;
     31
     32  /* Enable module power */
     33  lpc24xx_module_enable( LPC24XX_MODULE_RTC, 0, LPC24XX_MODULE_PCLK_DEFAULT);
     34
    2935  /* Enable the RTC and use external clock */
    3036  RTC_CCR = RTC_CCR_CLKEN | RTC_CCR_CLKSRC;
  • c/src/lib/libbsp/arm/lpc24xx/startup/bspreset.c

    r9832a22 r7ae2775  
    1919 */
    2020
     21#include <rtems.h>
     22
    2123#include <bsp/bootcard.h>
    22 #include <bsp/start.h>
     24#include <bsp/lpc24xx.h>
    2325
    2426void bsp_reset( void)
    2527{
    26   start();
     28  rtems_interrupt_level level;
     29
     30  rtems_interrupt_disable( level);
     31
     32  /* Trigger watchdog reset */
     33  WDCLKSEL = 0;
     34  WDTC = 0xff;
     35  WDMOD = 0x3;
     36  WDFEED = 0xaa;
     37  WDFEED = 0x55;
     38
     39  while (true) {
     40    /* Do nothing */
     41  }
    2742}
  • c/src/lib/libbsp/arm/lpc24xx/startup/bspstart.c

    r9832a22 r7ae2775  
    2424#include <bsp/bootcard.h>
    2525#include <bsp/dma.h>
     26#include <bsp/io.h>
     27#include <bsp/irq-generic.h>
    2628#include <bsp/irq.h>
    2729#include <bsp/linker-symbols.h>
    2830#include <bsp/lpc24xx.h>
     31#include <bsp/stackalloc.h>
    2932#include <bsp/start.h>
    3033#include <bsp/system-clocks.h>
     
    3942static void lpc24xx_ram_test_32( void)
    4043{
    41   volatile unsigned *out = (volatile unsigned *) bsp_ram_ext_start;
    42 
    43   while (out < (volatile unsigned *) bsp_ram_ext_end) {
     44  const unsigned *end = (const unsigned *) bsp_region_data_end;
     45  unsigned *begin = (unsigned *) bsp_region_data_begin;
     46  unsigned *out = begin;
     47
     48  while (out != end) {
    4449    *out = (unsigned) out;
    4550    ++out;
    4651  }
    4752
    48   out = (volatile unsigned *) bsp_ram_ext_start;
    49   while (out < (volatile unsigned *) bsp_ram_ext_end) {
     53  out = begin;
     54  while (out != end) {
    5055    if (*out != (unsigned) out) {
    5156      lpc24xx_fatal_error();
     
    6671    uint32_t mode = 0;
    6772
    68     /* Enable power */
    69     PCONP = SET_FLAGS( PCONP, 0x0800);
    70 
    71     /* Set PIN selects */
    72     PINSEL5 = SET_FLAGS( PINSEL5, 0x05050555);
    73     PINSEL6 = SET_FLAGS( PINSEL6, 0x55555555);
    74     PINSEL8 = SET_FLAGS( PINSEL8, 0x55555555);
    75     PINSEL9 = SET_FLAGS( PINSEL9, 0x50555555);
     73    /* Enable module power */
     74    lpc24xx_module_enable( LPC24XX_MODULE_EMC, 0, LPC24XX_MODULE_PCLK_DEFAULT);
     75
     76    /* IO configuration */
     77    lpc24xx_io_config( LPC24XX_MODULE_EMC, 0, 0);
    7678
    7779    /* Enable module, normal memory map and normal power mode */
     
    167169    EMC_DYN_CFG0 |= 0x00080000;
    168170
    169     /* Static Memory 0 settings */
    170     EMC_STA_WAITWEN0 = 0x02;
    171     EMC_STA_WAITOEN0 = 0x02;
    172     EMC_STA_WAITRD0 = 0x1f;
    173     EMC_STA_WAITPAGE0 = 0x1f;
    174     EMC_STA_WAITWR0 = 0x1f;
    175     EMC_STA_WAITTURN0 = 0x0f;
    176     EMC_STA_CFG0 = 0x81;
     171    /* Extended wait register */
     172    EMC_STA_EXT_WAIT = 0;
    177173
    178174    /* Static Memory 1 settings */
     
    183179    EMC_STA_WAITWR1 = 0x08;
    184180    EMC_STA_WAITTURN1 = 0x0f;
    185     EMC_STA_CFG1 = 0x80;
     181    EMC_STA_CFG1 = 0x81;
    186182
    187183    /* RAM test */
    188184    lpc24xx_ram_test_32();
    189   #endif /* LPC24XX_EMC_MICRON */
     185  #endif
    190186}
    191187
     
    194190  #ifndef LPC24XX_HAS_UBOOT
    195191    /* Enable main oscillator */
    196     SCS = SET_FLAGS( SCS, 0x20);
     192    SCS = SET_FLAG( SCS, 0x20);
    197193    while (IS_FLAG_CLEARED( SCS, 0x40)) {
    198194      /* Wait */
     
    201197    /* Set PLL */
    202198    lpc24xx_set_pll( 1, 0, 11, 3);
    203   #endif /* LPC24XX_HAS_UBOOT */
     199  #endif
    204200}
    205201
     
    222218    PINSEL9 = 0;
    223219    PINSEL10 = 0;
     220    PINSEL11 = 0;
     221
     222    /* Set pin modes  */
     223    PINMODE0 = 0;
     224    PINMODE1 = 0;
     225    PINMODE2 = 0;
     226    PINMODE3 = 0;
     227    PINMODE4 = 0;
     228    PINMODE5 = 0;
     229    PINMODE6 = 0;
     230    PINMODE7 = 0;
     231    PINMODE8 = 0;
     232    PINMODE9 = 0;
    224233
    225234    /* Set periperal clocks */
     
    234243    MAMTIM = 4;
    235244
    236     /* Set general purpose IO */
    237     IODIR0 = 0;
    238     IODIR1 = 0;
    239     IOSET0 = 0xffffffff;
    240     IOSET1 = 0xffffffff;
     245    /* Enable fast IO for ports 0 and 1 */
     246    SCS = SET_FLAG( SCS, 0x1);
    241247
    242248    /* Set fast IO */
     
    246252    FIO3DIR = 0;
    247253    FIO4DIR = 0;
    248     FIO0SET = 0xffffffff;
    249     FIO1SET = 0xffffffff;
    250     FIO2SET = 0xffffffff;
    251     FIO3SET = 0xffffffff;
    252     FIO4SET = 0xffffffff;
    253 
    254     /* Initialize UART 0 */
    255     PCONP = SET_FLAGS( PCONP, 0x08);
    256     PCLKSEL0 = SET_FLAGS( PCLKSEL0, 0x40);
    257     PINSEL0 = SET_FLAGS( PINSEL0, 0x50);
    258     U0LCR = 0;
    259     U0IER = 0;
    260     U0LCR = 0x80;
    261     U0DLL = lpc24xx_cclk() / 16 / LPC24XX_UART_BAUD;
    262     U0DLM = 0;
    263     U0LCR = 0x03;
    264     U0FCR = 0x07;
     254    FIO0CLR = 0xffffffff;
     255    FIO1CLR = 0xffffffff;
     256    FIO2CLR = 0xffffffff;
     257    FIO3CLR = 0xffffffff;
     258    FIO4CLR = 0xffffffff;
     259
     260    /* Initialize console */
     261    #ifdef LPC24XX_CONFIG_CONSOLE
     262      lpc24xx_module_enable( LPC24XX_MODULE_UART, 0, LPC24XX_MODULE_CCLK);
     263      lpc24xx_io_config( LPC24XX_MODULE_UART, 0, LPC24XX_CONFIG_CONSOLE);
     264      U0LCR = 0;
     265      U0IER = 0;
     266      U0LCR = 0x80;
     267      U0DLL = lpc24xx_cclk() / 16 / LPC24XX_UART_BAUD;
     268      U0DLM = 0;
     269      U0LCR = 0x03;
     270      U0FCR = 0x07;
     271    #endif
    265272
    266273    /* Initialize Timer 1 */
    267     PCONP = SET_FLAGS( PCONP, 0x04);
    268     PCLKSEL0 = SET_FLAGS( PCLKSEL0, 0x10);
    269   #endif /* LPC24XX_HAS_UBOOT */
     274    lpc24xx_module_enable( LPC24XX_MODULE_TIMER, 1, LPC24XX_MODULE_CCLK);
     275  #endif
    270276}
    271277
     
    273279{
    274280  #ifndef LPC24XX_HAS_UBOOT
    275     unsigned *in = bsp_section_text_end;
    276     unsigned *out = bsp_section_data_start;
     281    const unsigned *end = (const unsigned *) bsp_section_data_end;
     282    unsigned *in = (unsigned *) bsp_section_data_load_begin;
     283    unsigned *out = (unsigned *) bsp_section_data_begin;
    277284
    278285    /* Copy data */
    279     while (out < bsp_section_data_end) {
     286    while (out != end) {
    280287      *out = *in;
    281288      ++out;
    282289      ++in;
    283290    }
    284   #endif /* LPC24XX_HAS_UBOOT */
     291  #endif
    285292}
    286293
    287294static void lpc24xx_clear_bss( void)
    288295{
    289   unsigned *out = bsp_section_bss_start;
     296  const unsigned *end = (const unsigned *) bsp_section_bss_end;
     297  unsigned *out = (unsigned *) bsp_section_bss_begin;
    290298
    291299  /* Clear BSS */
    292   while (out < bsp_section_bss_end) {
     300  while (out != end) {
    293301    *out = 0;
    294302    ++out;
     
    316324
    317325  /* Exceptions */
     326  /* FIXME
    318327  rtems_exception_init_mngt();
     328  */
    319329
    320330  /* Interrupts */
     
    327337  /* DMA */
    328338  lpc24xx_dma_initialize();
     339
     340  /* Task stacks */
     341  bsp_stack_initialize(
     342    bsp_section_stack_begin,
     343    (intptr_t) bsp_section_stack_size
     344  );
     345
     346  /* UART configurations */
     347  #ifdef LPC24XX_CONFIG_UART_1
     348    lpc24xx_module_enable( LPC24XX_MODULE_UART, 1, LPC24XX_MODULE_CCLK);
     349    lpc24xx_io_config( LPC24XX_MODULE_UART, 1, LPC24XX_CONFIG_UART_1);
     350  #endif
     351  #ifdef LPC24XX_CONFIG_UART_2
     352    lpc24xx_module_enable( LPC24XX_MODULE_UART, 2, LPC24XX_MODULE_CCLK);
     353    lpc24xx_io_config( LPC24XX_MODULE_UART, 2, LPC24XX_CONFIG_UART_2);
     354  #endif
     355  #ifdef LPC24XX_CONFIG_UART_3
     356    lpc24xx_module_enable( LPC24XX_MODULE_UART, 3, LPC24XX_MODULE_CCLK);
     357    lpc24xx_io_config( LPC24XX_MODULE_UART, 3, LPC24XX_CONFIG_UART_3);
     358  #endif
    329359}
    330360
  • c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds

    r9832a22 r7ae2775  
    1111}
    1212
     13REGION_ALIAS ("REGION_START", RAM_EXT);
     14REGION_ALIAS ("REGION_VECTOR", RAM_INT);
     15REGION_ALIAS ("REGION_TEXT", RAM_EXT);
     16REGION_ALIAS ("REGION_TEXT_LOAD", RAM_EXT);
     17REGION_ALIAS ("REGION_RODATA", RAM_EXT);
     18REGION_ALIAS ("REGION_RODATA_LOAD", RAM_EXT);
     19REGION_ALIAS ("REGION_DATA", RAM_EXT);
     20REGION_ALIAS ("REGION_DATA_LOAD", RAM_EXT);
     21REGION_ALIAS ("REGION_FAST", RAM_INT);
     22REGION_ALIAS ("REGION_FAST_LOAD", RAM_INT);
     23REGION_ALIAS ("REGION_BSS", RAM_EXT);
     24REGION_ALIAS ("REGION_WORK", RAM_EXT);
     25REGION_ALIAS ("REGION_STACK", RAM_INT);
     26
    1327INCLUDE linkcmds.base
  • c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc2478

    r9832a22 r7ae2775  
    1212}
    1313
     14REGION_ALIAS ("REGION_START", RAM_EXT);
     15REGION_ALIAS ("REGION_VECTOR", RAM_INT);
     16REGION_ALIAS ("REGION_TEXT", RAM_EXT);
     17REGION_ALIAS ("REGION_TEXT_LOAD", RAM_EXT);
     18REGION_ALIAS ("REGION_RODATA", RAM_EXT);
     19REGION_ALIAS ("REGION_RODATA_LOAD", RAM_EXT);
     20REGION_ALIAS ("REGION_DATA", RAM_EXT);
     21REGION_ALIAS ("REGION_DATA_LOAD", RAM_EXT);
     22REGION_ALIAS ("REGION_FAST", RAM_INT);
     23REGION_ALIAS ("REGION_FAST_LOAD", RAM_INT);
     24REGION_ALIAS ("REGION_BSS", RAM_EXT);
     25REGION_ALIAS ("REGION_WORK", RAM_EXT);
     26REGION_ALIAS ("REGION_STACK", RAM_INT);
     27
    1428INCLUDE linkcmds.base
  • c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc2478_ncs

    r9832a22 r7ae2775  
    22 * @file
    33 *
    4  * LPC2478 (NCS).
     4 * LPC2478 (NCS, bootloader configuration).
    55 */
    66
    77MEMORY {
    8         RAM_INT (AIW) : ORIGIN = 0x40000000, LENGTH = 64k
    9         RAM_EXT (AIW) : ORIGIN = 0xa0400000, LENGTH = 4M
     8        RAM_VEC (AIW) : ORIGIN = 0x40000000, LENGTH = 32k
     9        RAM_INT (AIW) : ORIGIN = 0x40008000, LENGTH = 32k
     10        RAM_EXT (AIW) : ORIGIN = 0xa0c00000, LENGTH = 4M
    1011        ROM_INT (RX)  : ORIGIN = 0x00000000, LENGTH = 512k - 8k
    1112        NIRVANA : ORIGIN = 0, LENGTH = 0
    1213}
    1314
    14 INCLUDE linkcmds.rom
     15REGION_ALIAS ("REGION_START", ROM_INT);
     16REGION_ALIAS ("REGION_VECTOR", RAM_VEC);
     17REGION_ALIAS ("REGION_TEXT", ROM_INT);
     18REGION_ALIAS ("REGION_TEXT_LOAD", ROM_INT);
     19REGION_ALIAS ("REGION_RODATA", ROM_INT);
     20REGION_ALIAS ("REGION_RODATA_LOAD", ROM_INT);
     21REGION_ALIAS ("REGION_DATA", RAM_EXT);
     22REGION_ALIAS ("REGION_DATA_LOAD", ROM_INT);
     23REGION_ALIAS ("REGION_FAST", RAM_INT);
     24REGION_ALIAS ("REGION_FAST_LOAD", RAM_INT);
     25REGION_ALIAS ("REGION_BSS", RAM_EXT);
     26REGION_ALIAS ("REGION_WORK", RAM_EXT);
     27REGION_ALIAS ("REGION_STACK", RAM_INT);
     28
     29INCLUDE linkcmds.base
  • c/src/lib/libbsp/arm/lpc24xx/startup/linkcmds.lpc2478_ncs_ram

    r9832a22 r7ae2775  
    77MEMORY {
    88        RAM_INT (AIW) : ORIGIN = 0x40000000, LENGTH = 64k
    9         RAM_EXT (AIW) : ORIGIN = 0xa0000000, LENGTH = 8M
     9        RAM_EXT (AIW) : ORIGIN = 0xa0000000, LENGTH = 16M
    1010        ROM_INT (RX)  : ORIGIN = 0x00000000, LENGTH = 512k - 8k
    1111        NIRVANA : ORIGIN = 0, LENGTH = 0
    1212}
    1313
     14REGION_ALIAS ("REGION_START", RAM_EXT);
     15REGION_ALIAS ("REGION_VECTOR", RAM_INT);
     16REGION_ALIAS ("REGION_TEXT", RAM_EXT);
     17REGION_ALIAS ("REGION_TEXT_LOAD", RAM_EXT);
     18REGION_ALIAS ("REGION_RODATA", RAM_EXT);
     19REGION_ALIAS ("REGION_RODATA_LOAD", RAM_EXT);
     20REGION_ALIAS ("REGION_DATA", RAM_EXT);
     21REGION_ALIAS ("REGION_DATA_LOAD", RAM_EXT);
     22REGION_ALIAS ("REGION_FAST", RAM_INT);
     23REGION_ALIAS ("REGION_FAST_LOAD", RAM_INT);
     24REGION_ALIAS ("REGION_BSS", RAM_EXT);
     25REGION_ALIAS ("REGION_WORK", RAM_EXT);
     26REGION_ALIAS ("REGION_STACK", RAM_INT);
     27
    1428INCLUDE linkcmds.base
Note: See TracChangeset for help on using the changeset viewer.