Changeset 797d88ba in rtems


Ignore:
Timestamp:
Dec 13, 2000, 10:12:06 PM (20 years ago)
Author:
Joel Sherrill <joel.sherrill@…>
Branches:
4.10, 4.11, 4.8, 4.9, 5, master
Children:
9928d08
Parents:
0289674
Message:

2000-12-13 Joel Sherrill <joel@…>

  • cpu.c: Removed duplicate declaration for _ISR_Vector_table.
  • cpu_asm.S: Removed assembly language to vector ISR handler on MIPS ISA I. Now call mips_vector_isr_handlers() in libcpu or BSP.
  • rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No longer a constant -- get the real value from libcpu.
Files:
8 edited

Legend:

Unmodified
Added
Removed
  • c/src/exec/score/cpu/mips/ChangeLog

    r0289674 r797d88ba  
     12000-12-13      Joel Sherrill <joel@OARcorp.com>
     2
     3        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
     4        * cpu_asm.S: Removed assembly language to vector ISR handler
     5        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
     6        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
     7        longer a constant -- get the real value from libcpu.
     8
    192000-12-13      Joel Sherrill <joel@OARcorp.com>
    210
  • c/src/exec/score/cpu/mips/cpu.c

    r0289674 r797d88ba  
    4343
    4444
    45 ISR_Handler_entry _ISR_Vector_table[ ISR_NUMBER_OF_VECTORS ];
    46 
    4745/*  _CPU_Initialize
    4846 *
  • c/src/exec/score/cpu/mips/cpu_asm.S

    r0289674 r797d88ba  
    793793        and k0,k1
    794794        and k0,CAUSE_IPMASK
    795         beq k0,zero,_ISR_Handler_exit /* external interrupt not enabled, ignore */
    796                                       /* but if it's not an exception or an interrupt,
    797                                       /* Then where did it come from??? */
     795        beq k0,zero,_ISR_Handler_exit
     796                /* external interrupt not enabled, ignore */
     797                /* but if it's not an exception or an interrupt, */
     798                /* Then where did it come from??? */
    798799        nop
    799800
     
    822823
    823824  /*
    824    *  while ( interrupts_pending(cause_reg) ) {
    825    *     vector = BITFIELD_TO_INDEX(cause_reg);
    826    *     (*_ISR_Vector_table[ vector ])( vector );
    827    *  }
    828    */
    829         /* k0 has the SR interrupt bits */
    830         la t3, _ISR_Vector_table
    831 
    832         /* The bits you look at can be prioritized here just by */
    833         /*  changing what bit is looked at. I.E. SR_IBITx */
    834         /* This code might become a loop, servicing all ints before returning.. */
    835         /*   Right now, it will go thru the whole list once */
    836 
    837 _ISR_check_bit_0:
    838         and k1, k0, SR_IBIT1
    839         beq k1, zero, _ISR_check_bit_1
     825   *  Call the CPU model or BSP specific routine to decode the
     826   *  interrupt source and actually vector to device ISR handlers.
     827   */
     828
     829        jal     mips_vector_isr_handlers
    840830        nop
    841         li  t1, ISR_VEC_SIZE*0
    842         add t3, t1
    843         jal t3 
    844         nop
    845 _ISR_check_bit_1:
    846         and k1, k0, SR_IBIT2
    847         beq k1, zero, _ISR_check_bit_2
    848         nop
    849         li  t1, ISR_VEC_SIZE*1
    850         add t3, t1
    851         jal t3
    852         nop
    853 _ISR_check_bit_2:
    854         and k1, k0, SR_IBIT3
    855         beq k1, zero, _ISR_check_bit_3
    856         nop
    857         li  t1, ISR_VEC_SIZE*2
    858         add t3, t1
    859         jal t3
    860         nop
    861 _ISR_check_bit_3:
    862         and k1, k0, SR_IBIT4
    863         beq k1, zero, _ISR_check_bit_4
    864         nop
    865         li  t1, ISR_VEC_SIZE*3
    866         add t3, t1
    867         jal t3
    868         nop
    869 _ISR_check_bit_4:
    870         and k1, k0, SR_IBIT5
    871         beq k1, zero, _ISR_check_bit_5
    872         nop
    873         li  t1, ISR_VEC_SIZE*4
    874         add t3, t1
    875         jal t3
    876         nop
    877 _ISR_check_bit_5:
    878         and k1, k0, SR_IBIT6
    879         beq k1, zero, _ISR_check_bit_6
    880         nop
    881         li  t1, ISR_VEC_SIZE*5
    882         add t3, t1
    883         jal t3
    884         nop
    885 _ISR_check_bit_6:
    886         and k1, k0, SR_IBIT7
    887         beq k1, zero, _ISR_check_bit_7
    888         nop
    889         li  t1, ISR_VEC_SIZE*6
    890         add t3, t1
    891         jal t3
    892         nop
    893 _ISR_check_bit_7:
    894         and k1, k0, SR_IBIT8
    895         beq k1, zero, _ISR_exit_int_check
    896         nop
    897         li  t1, ISR_VEC_SIZE*7
    898         add t3, t1
    899         jal t3
    900         nop
    901 
    902 _ISR_exit_int_check:
    903831
    904832  /*
  • c/src/exec/score/cpu/mips/rtems/score/cpu.h

    r0289674 r797d88ba  
    527527
    528528extern unsigned int mips_interrupt_number_of_vectors;
    529 #define CPU_INTERRUPT_NUMBER_OF_VECTORS      8
     529#define CPU_INTERRUPT_NUMBER_OF_VECTORS      (mips_interrupt_number_of_vectors)
    530530#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
    531531
  • cpukit/score/cpu/mips/ChangeLog

    r0289674 r797d88ba  
     12000-12-13      Joel Sherrill <joel@OARcorp.com>
     2
     3        * cpu.c: Removed duplicate declaration for _ISR_Vector_table.
     4        * cpu_asm.S: Removed assembly language to vector ISR handler
     5        on MIPS ISA I.  Now call mips_vector_isr_handlers() in libcpu or BSP.
     6        * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No
     7        longer a constant -- get the real value from libcpu.
     8
    192000-12-13      Joel Sherrill <joel@OARcorp.com>
    210
  • cpukit/score/cpu/mips/cpu.c

    r0289674 r797d88ba  
    4343
    4444
    45 ISR_Handler_entry _ISR_Vector_table[ ISR_NUMBER_OF_VECTORS ];
    46 
    4745/*  _CPU_Initialize
    4846 *
  • cpukit/score/cpu/mips/cpu_asm.S

    r0289674 r797d88ba  
    793793        and k0,k1
    794794        and k0,CAUSE_IPMASK
    795         beq k0,zero,_ISR_Handler_exit /* external interrupt not enabled, ignore */
    796                                       /* but if it's not an exception or an interrupt,
    797                                       /* Then where did it come from??? */
     795        beq k0,zero,_ISR_Handler_exit
     796                /* external interrupt not enabled, ignore */
     797                /* but if it's not an exception or an interrupt, */
     798                /* Then where did it come from??? */
    798799        nop
    799800
     
    822823
    823824  /*
    824    *  while ( interrupts_pending(cause_reg) ) {
    825    *     vector = BITFIELD_TO_INDEX(cause_reg);
    826    *     (*_ISR_Vector_table[ vector ])( vector );
    827    *  }
    828    */
    829         /* k0 has the SR interrupt bits */
    830         la t3, _ISR_Vector_table
    831 
    832         /* The bits you look at can be prioritized here just by */
    833         /*  changing what bit is looked at. I.E. SR_IBITx */
    834         /* This code might become a loop, servicing all ints before returning.. */
    835         /*   Right now, it will go thru the whole list once */
    836 
    837 _ISR_check_bit_0:
    838         and k1, k0, SR_IBIT1
    839         beq k1, zero, _ISR_check_bit_1
     825   *  Call the CPU model or BSP specific routine to decode the
     826   *  interrupt source and actually vector to device ISR handlers.
     827   */
     828
     829        jal     mips_vector_isr_handlers
    840830        nop
    841         li  t1, ISR_VEC_SIZE*0
    842         add t3, t1
    843         jal t3 
    844         nop
    845 _ISR_check_bit_1:
    846         and k1, k0, SR_IBIT2
    847         beq k1, zero, _ISR_check_bit_2
    848         nop
    849         li  t1, ISR_VEC_SIZE*1
    850         add t3, t1
    851         jal t3
    852         nop
    853 _ISR_check_bit_2:
    854         and k1, k0, SR_IBIT3
    855         beq k1, zero, _ISR_check_bit_3
    856         nop
    857         li  t1, ISR_VEC_SIZE*2
    858         add t3, t1
    859         jal t3
    860         nop
    861 _ISR_check_bit_3:
    862         and k1, k0, SR_IBIT4
    863         beq k1, zero, _ISR_check_bit_4
    864         nop
    865         li  t1, ISR_VEC_SIZE*3
    866         add t3, t1
    867         jal t3
    868         nop
    869 _ISR_check_bit_4:
    870         and k1, k0, SR_IBIT5
    871         beq k1, zero, _ISR_check_bit_5
    872         nop
    873         li  t1, ISR_VEC_SIZE*4
    874         add t3, t1
    875         jal t3
    876         nop
    877 _ISR_check_bit_5:
    878         and k1, k0, SR_IBIT6
    879         beq k1, zero, _ISR_check_bit_6
    880         nop
    881         li  t1, ISR_VEC_SIZE*5
    882         add t3, t1
    883         jal t3
    884         nop
    885 _ISR_check_bit_6:
    886         and k1, k0, SR_IBIT7
    887         beq k1, zero, _ISR_check_bit_7
    888         nop
    889         li  t1, ISR_VEC_SIZE*6
    890         add t3, t1
    891         jal t3
    892         nop
    893 _ISR_check_bit_7:
    894         and k1, k0, SR_IBIT8
    895         beq k1, zero, _ISR_exit_int_check
    896         nop
    897         li  t1, ISR_VEC_SIZE*7
    898         add t3, t1
    899         jal t3
    900         nop
    901 
    902 _ISR_exit_int_check:
    903831
    904832  /*
  • cpukit/score/cpu/mips/rtems/score/cpu.h

    r0289674 r797d88ba  
    527527
    528528extern unsigned int mips_interrupt_number_of_vectors;
    529 #define CPU_INTERRUPT_NUMBER_OF_VECTORS      8
     529#define CPU_INTERRUPT_NUMBER_OF_VECTORS      (mips_interrupt_number_of_vectors)
    530530#define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER  (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1)
    531531
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