Changeset 797d88ba in rtems
- Timestamp:
- 12/13/00 22:12:06 (21 years ago)
- Branches:
- 4.10, 4.11, 4.8, 4.9, 5, master
- Children:
- 9928d08
- Parents:
- 0289674
- Files:
-
- 8 edited
Legend:
- Unmodified
- Added
- Removed
-
c/src/exec/score/cpu/mips/ChangeLog
r0289674 r797d88ba 1 2000-12-13 Joel Sherrill <joel@OARcorp.com> 2 3 * cpu.c: Removed duplicate declaration for _ISR_Vector_table. 4 * cpu_asm.S: Removed assembly language to vector ISR handler 5 on MIPS ISA I. Now call mips_vector_isr_handlers() in libcpu or BSP. 6 * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No 7 longer a constant -- get the real value from libcpu. 8 1 9 2000-12-13 Joel Sherrill <joel@OARcorp.com> 2 10 -
c/src/exec/score/cpu/mips/cpu.c
r0289674 r797d88ba 43 43 44 44 45 ISR_Handler_entry _ISR_Vector_table[ ISR_NUMBER_OF_VECTORS ];46 47 45 /* _CPU_Initialize 48 46 * -
c/src/exec/score/cpu/mips/cpu_asm.S
r0289674 r797d88ba 793 793 and k0,k1 794 794 and k0,CAUSE_IPMASK 795 beq k0,zero,_ISR_Handler_exit /* external interrupt not enabled, ignore */ 796 /* but if it's not an exception or an interrupt, 797 /* Then where did it come from??? */ 795 beq k0,zero,_ISR_Handler_exit 796 /* external interrupt not enabled, ignore */ 797 /* but if it's not an exception or an interrupt, */ 798 /* Then where did it come from??? */ 798 799 nop 799 800 … … 822 823 823 824 /* 824 * while ( interrupts_pending(cause_reg) ) { 825 * vector = BITFIELD_TO_INDEX(cause_reg); 826 * (*_ISR_Vector_table[ vector ])( vector ); 827 * } 828 */ 829 /* k0 has the SR interrupt bits */ 830 la t3, _ISR_Vector_table 831 832 /* The bits you look at can be prioritized here just by */ 833 /* changing what bit is looked at. I.E. SR_IBITx */ 834 /* This code might become a loop, servicing all ints before returning.. */ 835 /* Right now, it will go thru the whole list once */ 836 837 _ISR_check_bit_0: 838 and k1, k0, SR_IBIT1 839 beq k1, zero, _ISR_check_bit_1 825 * Call the CPU model or BSP specific routine to decode the 826 * interrupt source and actually vector to device ISR handlers. 827 */ 828 829 jal mips_vector_isr_handlers 840 830 nop 841 li t1, ISR_VEC_SIZE*0842 add t3, t1843 jal t3844 nop845 _ISR_check_bit_1:846 and k1, k0, SR_IBIT2847 beq k1, zero, _ISR_check_bit_2848 nop849 li t1, ISR_VEC_SIZE*1850 add t3, t1851 jal t3852 nop853 _ISR_check_bit_2:854 and k1, k0, SR_IBIT3855 beq k1, zero, _ISR_check_bit_3856 nop857 li t1, ISR_VEC_SIZE*2858 add t3, t1859 jal t3860 nop861 _ISR_check_bit_3:862 and k1, k0, SR_IBIT4863 beq k1, zero, _ISR_check_bit_4864 nop865 li t1, ISR_VEC_SIZE*3866 add t3, t1867 jal t3868 nop869 _ISR_check_bit_4:870 and k1, k0, SR_IBIT5871 beq k1, zero, _ISR_check_bit_5872 nop873 li t1, ISR_VEC_SIZE*4874 add t3, t1875 jal t3876 nop877 _ISR_check_bit_5:878 and k1, k0, SR_IBIT6879 beq k1, zero, _ISR_check_bit_6880 nop881 li t1, ISR_VEC_SIZE*5882 add t3, t1883 jal t3884 nop885 _ISR_check_bit_6:886 and k1, k0, SR_IBIT7887 beq k1, zero, _ISR_check_bit_7888 nop889 li t1, ISR_VEC_SIZE*6890 add t3, t1891 jal t3892 nop893 _ISR_check_bit_7:894 and k1, k0, SR_IBIT8895 beq k1, zero, _ISR_exit_int_check896 nop897 li t1, ISR_VEC_SIZE*7898 add t3, t1899 jal t3900 nop901 902 _ISR_exit_int_check:903 831 904 832 /* -
c/src/exec/score/cpu/mips/rtems/score/cpu.h
r0289674 r797d88ba 527 527 528 528 extern unsigned int mips_interrupt_number_of_vectors; 529 #define CPU_INTERRUPT_NUMBER_OF_VECTORS 8529 #define CPU_INTERRUPT_NUMBER_OF_VECTORS (mips_interrupt_number_of_vectors) 530 530 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) 531 531 -
cpukit/score/cpu/mips/ChangeLog
r0289674 r797d88ba 1 2000-12-13 Joel Sherrill <joel@OARcorp.com> 2 3 * cpu.c: Removed duplicate declaration for _ISR_Vector_table. 4 * cpu_asm.S: Removed assembly language to vector ISR handler 5 on MIPS ISA I. Now call mips_vector_isr_handlers() in libcpu or BSP. 6 * rtems/score/cpu.h (CPU_INTERRUPT_NUMBER_OF_VECTORS): No 7 longer a constant -- get the real value from libcpu. 8 1 9 2000-12-13 Joel Sherrill <joel@OARcorp.com> 2 10 -
cpukit/score/cpu/mips/cpu.c
r0289674 r797d88ba 43 43 44 44 45 ISR_Handler_entry _ISR_Vector_table[ ISR_NUMBER_OF_VECTORS ];46 47 45 /* _CPU_Initialize 48 46 * -
cpukit/score/cpu/mips/cpu_asm.S
r0289674 r797d88ba 793 793 and k0,k1 794 794 and k0,CAUSE_IPMASK 795 beq k0,zero,_ISR_Handler_exit /* external interrupt not enabled, ignore */ 796 /* but if it's not an exception or an interrupt, 797 /* Then where did it come from??? */ 795 beq k0,zero,_ISR_Handler_exit 796 /* external interrupt not enabled, ignore */ 797 /* but if it's not an exception or an interrupt, */ 798 /* Then where did it come from??? */ 798 799 nop 799 800 … … 822 823 823 824 /* 824 * while ( interrupts_pending(cause_reg) ) { 825 * vector = BITFIELD_TO_INDEX(cause_reg); 826 * (*_ISR_Vector_table[ vector ])( vector ); 827 * } 828 */ 829 /* k0 has the SR interrupt bits */ 830 la t3, _ISR_Vector_table 831 832 /* The bits you look at can be prioritized here just by */ 833 /* changing what bit is looked at. I.E. SR_IBITx */ 834 /* This code might become a loop, servicing all ints before returning.. */ 835 /* Right now, it will go thru the whole list once */ 836 837 _ISR_check_bit_0: 838 and k1, k0, SR_IBIT1 839 beq k1, zero, _ISR_check_bit_1 825 * Call the CPU model or BSP specific routine to decode the 826 * interrupt source and actually vector to device ISR handlers. 827 */ 828 829 jal mips_vector_isr_handlers 840 830 nop 841 li t1, ISR_VEC_SIZE*0842 add t3, t1843 jal t3844 nop845 _ISR_check_bit_1:846 and k1, k0, SR_IBIT2847 beq k1, zero, _ISR_check_bit_2848 nop849 li t1, ISR_VEC_SIZE*1850 add t3, t1851 jal t3852 nop853 _ISR_check_bit_2:854 and k1, k0, SR_IBIT3855 beq k1, zero, _ISR_check_bit_3856 nop857 li t1, ISR_VEC_SIZE*2858 add t3, t1859 jal t3860 nop861 _ISR_check_bit_3:862 and k1, k0, SR_IBIT4863 beq k1, zero, _ISR_check_bit_4864 nop865 li t1, ISR_VEC_SIZE*3866 add t3, t1867 jal t3868 nop869 _ISR_check_bit_4:870 and k1, k0, SR_IBIT5871 beq k1, zero, _ISR_check_bit_5872 nop873 li t1, ISR_VEC_SIZE*4874 add t3, t1875 jal t3876 nop877 _ISR_check_bit_5:878 and k1, k0, SR_IBIT6879 beq k1, zero, _ISR_check_bit_6880 nop881 li t1, ISR_VEC_SIZE*5882 add t3, t1883 jal t3884 nop885 _ISR_check_bit_6:886 and k1, k0, SR_IBIT7887 beq k1, zero, _ISR_check_bit_7888 nop889 li t1, ISR_VEC_SIZE*6890 add t3, t1891 jal t3892 nop893 _ISR_check_bit_7:894 and k1, k0, SR_IBIT8895 beq k1, zero, _ISR_exit_int_check896 nop897 li t1, ISR_VEC_SIZE*7898 add t3, t1899 jal t3900 nop901 902 _ISR_exit_int_check:903 831 904 832 /* -
cpukit/score/cpu/mips/rtems/score/cpu.h
r0289674 r797d88ba 527 527 528 528 extern unsigned int mips_interrupt_number_of_vectors; 529 #define CPU_INTERRUPT_NUMBER_OF_VECTORS 8529 #define CPU_INTERRUPT_NUMBER_OF_VECTORS (mips_interrupt_number_of_vectors) 530 530 #define CPU_INTERRUPT_MAXIMUM_VECTOR_NUMBER (CPU_INTERRUPT_NUMBER_OF_VECTORS - 1) 531 531
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