Changeset 7920d156 in rtems


Ignore:
Timestamp:
Jun 2, 2009, 9:13:23 PM (10 years ago)
Author:
Eric Norum <WENorum@…>
Branches:
4.9
Children:
dda372da
Parents:
ee2e3a1
Message:

As per Freescale chip errata, disable buffered writes.

Location:
c/src/lib/libbsp/m68k/uC5282
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/m68k/uC5282/ChangeLog

    ree2e3a1 r7920d156  
     12009-06-02      Eric Norum <norume@aps.anl.gov>
     2
     3        * startup/bspstart.c: Turn off buffered writes.
     4
    152009-03-02      Till Straumann <strauman@slac.stanford.edu>
    26
  • c/src/lib/libbsp/m68k/uC5282/startup/bspstart.c

    ree2e3a1 r7920d156  
    5858 * corruption problem.
    5959 * DATECODES AFFECTED: All
     60 *
     61 *
     62 * Buffered writes must be disabled as described in "MCF5282 Chip Errata",
     63 * MCF5282DE, Rev. 6, 5/2009:
     64 *   SECF124: Buffered Write May Be Executed Twice
     65 *   Errata type: Silicon
     66 *   Affected component: Cache
     67 *   Description: If buffered writes are enabled using the CACR or ACR
     68 *                registers, the imprecise write transaction generated
     69 *                by a buffered write may be executed twice.
     70 *   Workaround: Do not enable buffered writes in the CACR or ACR registers:
     71 *               CACR[8] = DBWE (default buffered write enable) must be 0
     72 *               ACRn[5] = BUFW (buffered write enable) must be 0
     73 *   Fix plan: Currently, there are no plans to fix this.
    6074 */
    6175#define m68k_set_cacr_nop(_cacr) asm volatile ("movec %0,%%cacr\n\tnop" : : "d" (_cacr))
     
    6882 *   Split instruction/data or instruction-only
    6983 *   Allow CPUSHL to invalidate a cache line
    70  *   Enable buffered writes
     84 *   Disable buffered writes
    7185 *   No burst transfers on non-cacheable accesses
    7286 *   Default cache mode is *disabled* (cache only ACRx areas)
     
    7690                             MCF5XXX_CACR_DISD |
    7791#endif
    78                              MCF5XXX_CACR_DBWE |
    7992                             MCF5XXX_CACR_DCM;
    8093uint32_t mcf5282_acr0_mode = 0;
     
    270283                      MCF5XXX_ACR_AM((uint32_t)_RamSize-1)   |
    271284                      MCF5XXX_ACR_EN                         |
    272                       MCF5XXX_ACR_BWE                        |
    273285                      MCF5XXX_ACR_SM_IGNORE;
    274286  m68k_set_acr0(mcf5282_acr0_mode);
Note: See TracChangeset for help on using the changeset viewer.