Changeset 78e529a6 in rtems


Ignore:
Timestamp:
Dec 22, 2013, 7:49:52 PM (5 years ago)
Author:
Daniel Ramirez <javamonn@…>
Branches:
4.11, master
Children:
9543fdbb
Parents:
c0f731d
git-author:
Daniel Ramirez <javamonn@…> (12/22/13 19:49:52)
git-committer:
Gedare Bloom <gedare@…> (12/22/13 20:39:55)
Message:

arm_rtl22xx: added new doxygen

Location:
c/src/lib/libbsp/arm/rtl22xx
Files:
1 added
2 edited

Legend:

Unmodified
Added
Removed
  • c/src/lib/libbsp/arm/rtl22xx/console/lpc22xx_uart.h

    rc0f731d r78e529a6  
    1 /*
    2  *  Definitions for LPC22xx/LPC21xx
     1/**
     2 * @file
     3 * @ingroup rtl22xx_uart
     4 * @brief UART support.
    35 */
    46
    57#ifndef LPC22XX_UART_H
    68#define LPC22XX_UART_H
     9
     10/**
     11 * @defgroup rtl22xx_uart UART Support
     12 * @ingroup arm_rtl22xx
     13 * @brief UART (Universal Asynchronous Reciever/Transmitter) Support
     14 * @{
     15 */
    716
    817#define FIFODEEP    16
     
    1221#define BD9600      9600
    1322
    14 #define U0_PINSEL       (0x00000005)    /* PINSEL0 Value for UART0 */
    15 #define U0_PINMASK      (0x0000000F)    /* PINSEL0 Mask for UART0 */
    16 #define U1_PINSEL       (0x00050000)    /* PINSEL0 Value for UART1 */
    17 #define U1_PINMASK      (0x000F0000)    /* PINSEL0 Mask for UART1 */
     23/** @brief PINSEL0 Value for UART0 */
     24#define U0_PINSEL       (0x00000005)
     25/** @brief PINSEL0 Mask for UART0 */
     26#define U0_PINMASK      (0x0000000F)
     27/** @brief PINSEL0 Value for UART1 */
     28#define U1_PINSEL       (0x00050000)
     29/** @brief PINSEL0 Mask for UART1 */
     30#define U1_PINMASK      (0x000F0000)
    1831
    19 /* Uart line control register bit descriptions */
     32/**
     33 * @name Uart line control register bit descriptions
     34 * @{
     35 */
     36
    2037#define LCR_WORDLENTH_BIT         0
    2138#define LCR_STOPBITSEL_BIT        2
     
    2441#define LCR_BREAKCONTROL_BIT      6
    2542#define LCR_DLAB_BIT              7
    26 // Line Control Register bit definitions
    27 #define ULCR_CHAR_5         (0 << 0)    // 5-bit character length
    28 #define ULCR_CHAR_6         (1 << 0)    // 6-bit character length
    29 #define ULCR_CHAR_7         (2 << 0)    // 7-bit character length
    30 #define ULCR_CHAR_8         (3 << 0)    // 8-bit character length
    31 #define ULCR_STOP_0         (0 << 2)    // no stop bits
    32 #define ULCR_STOP_1         (1 << 2)    // 1 stop bit
    33 #define ULCR_PAR_NO         (0 << 3)    // No Parity
    34 #define ULCR_PAR_ODD        (1 << 3)    // Odd Parity
    35 #define ULCR_PAR_EVEN       (3 << 3)    // Even Parity
    36 #define ULCR_PAR_MARK       (5 << 3)    // MARK "1" Parity
    37 #define ULCR_PAR_SPACE      (7 << 3)    // SPACE "0" Paruty
    38 #define ULCR_BREAK_ENABLE   (1 << 6)    // Output BREAK line condition
    39 #define ULCR_DLAB_ENABLE    (1 << 7)    // Enable Divisor Latch Access
    40 // Modem Control Register bit definitions
    41 #define UMCR_DTR            (1 << 0)    // Data Terminal Ready
    42 #define UMCR_RTS            (1 << 1)    // Request To Send
    43 #define UMCR_LB             (1 << 4)    // Loopback
    4443
    45 // Line Status Register bit definitions
    46 #define ULSR_RDR            (1 << 0)    // Receive Data Ready
    47 #define ULSR_OE             (1 << 1)    // Overrun Error
    48 #define ULSR_PE             (1 << 2)    // Parity Error
    49 #define ULSR_FE             (1 << 3)    // Framing Error
    50 #define ULSR_BI             (1 << 4)    // Break Interrupt
    51 #define ULSR_THRE           (1 << 5)    // Transmit Holding Register Empty
    52 #define ULSR_TEMT           (1 << 6)    // Transmitter Empty
    53 #define ULSR_RXFE           (1 << 7)    // Error in Receive FIFO
     44/** @} */
     45
     46/**
     47 * @name Line Control Register bit definitions
     48 * @{
     49 */
     50
     51/** @brief 5-bit character length */
     52#define ULCR_CHAR_5         (0 << 0)
     53/** @brief 6-bit character length */
     54#define ULCR_CHAR_6         (1 << 0)
     55/** @brief 7-bit character length */
     56#define ULCR_CHAR_7         (2 << 0)
     57/** @brief 8-bit character length */
     58#define ULCR_CHAR_8         (3 << 0)
     59/** @brief no stop bits */
     60#define ULCR_STOP_0         (0 << 2)
     61/** @brief 1 stop bit */
     62#define ULCR_STOP_1         (1 << 2)
     63/** @brief No Parity */
     64#define ULCR_PAR_NO         (0 << 3)
     65/** @brief Odd Parity */
     66#define ULCR_PAR_ODD        (1 << 3)
     67/** @brief Even Parity */
     68#define ULCR_PAR_EVEN       (3 << 3)
     69/** @brief MARK "1" Parity */
     70#define ULCR_PAR_MARK       (5 << 3)
     71/** @brief SPACE "0" Paruty */
     72#define ULCR_PAR_SPACE      (7 << 3)
     73/** @brief Output BREAK line condition */
     74#define ULCR_BREAK_ENABLE   (1 << 6)
     75/** @brief Enable Divisor Latch Access */
     76#define ULCR_DLAB_ENABLE    (1 << 7)
     77
     78/** @} */
     79
     80/**
     81 * @name Modem Control Register bit definitions
     82 * @{
     83 */
     84
     85/** @brief Data Terminal Ready */
     86#define UMCR_DTR            (1 << 0)
     87/** @brief Request To Send */
     88#define UMCR_RTS            (1 << 1)
     89/** @brief Loopback */
     90#define UMCR_LB             (1 << 4)
     91
     92/** @} */
     93
     94/**
     95 * @name  Line Status Register bit definitions
     96 * @{
     97 */
     98
     99/** @brief Receive Data Ready */
     100#define ULSR_RDR            (1 << 0)
     101/** @brief Overrun Error */
     102#define ULSR_OE             (1 << 1)
     103/** @brief Parity Error */
     104#define ULSR_PE             (1 << 2)
     105/** @brief Framing Error */
     106#define ULSR_FE             (1 << 3)
     107/** @brief Break Interrupt */
     108#define ULSR_BI             (1 << 4)
     109/** @brief Transmit Holding Register Empty */
     110#define ULSR_THRE           (1 << 5)
     111/** @brief Transmitter Empty */
     112#define ULSR_TEMT           (1 << 6)
     113/** @brief Error in Receive FIFO */
     114#define ULSR_RXFE           (1 << 7)
    54115#define ULSR_ERR_MASK       0x1E
    55116
    56 // Modem Status Register bit definitions
    57 #define UMSR_DCTS           (1 << 0)    // Delta Clear To Send
    58 #define UMSR_DDSR           (1 << 1)    // Delta Data Set Ready
    59 #define UMSR_TERI           (1 << 2)    // Trailing Edge Ring Indicator
    60 #define UMSR_DDCD           (1 << 3)    // Delta Data Carrier Detect
    61 #define UMSR_CTS            (1 << 4)    // Clear To Send
    62 #define UMSR_DSR            (1 << 5)    // Data Set Ready
    63 #define UMSR_RI             (1 << 6)    // Ring Indicator
    64 #define UMSR_DCD            (1 << 7)    // Data Carrier Detect
     117/** @} */
    65118
    66 /* Uart Interrupt Identification */
     119/**
     120 * @name Modem Status Register bit definitions
     121 * @{
     122 */
     123
     124/** @brief Delta Clear To Send */
     125#define UMSR_DCTS           (1 << 0)
     126/** @brief Delta Data Set Ready */
     127#define UMSR_DDSR           (1 << 1)
     128/** @brief Trailing Edge Ring Indicator */
     129#define UMSR_TERI           (1 << 2)
     130/** @brief Delta Data Carrier Detect */
     131#define UMSR_DDCD           (1 << 3)
     132/** @brief Clear To Send */
     133#define UMSR_CTS            (1 << 4)
     134/** @brief Data Set Ready */
     135#define UMSR_DSR            (1 << 5)
     136/** @brief Ring Indicator */
     137#define UMSR_RI             (1 << 6)
     138/** @brief Data Carrier Detect */
     139#define UMSR_DCD            (1 << 7)
     140
     141/** @} */
     142
     143/**
     144 * @name Uart Interrupt Identification
     145 * @{
     146 */
     147
    67148#define IIR_RSL                   0x3
    68149#define IIR_RDA                   0x2
     
    70151#define IIR_THRE                  0x1
    71152
    72 /* Uart Interrupt Enable Type*/
     153/** @} */
     154
     155/**
     156 * @name  Uart Interrupt Enable Type
     157 * @{
     158 */
     159
    73160#define IER_RBR                   0x1
    74161#define IER_THRE                  0x2
    75162#define IER_RLS                   0x4
    76163
    77 /* Uart Receiver Errors*/
     164/** @} */
     165
     166/**
     167 * @name Uart Receiver Errors
     168 * @{
     169 */
     170
    78171#define RC_FIFO_OVERRUN_ERR       0x1
    79172#define RC_OVERRUN_ERR            0x2
     
    82175#define RC_BREAK_IND              0x10
    83176
     177/** @} */
     178
    84179typedef enum {
    85180  UART0 = 0,
    86181  UART1
    87182} LPC_UartChanel_t;
     183
     184/** @} */
     185
    88186#endif
    89187
  • c/src/lib/libbsp/arm/rtl22xx/include/bsp.h

    rc0f731d r78e529a6  
     1/**
     2 * @file
     3 * @ingroup arm_rtl22xx
     4 * @brief Global BSP definitions.
     5 */
     6
    17/*
    28 * Philips LPC22XX/LPC21xx BSP header file
     
    1824#include <bsp/default-initial-extension.h>
    1925
     26/**
     27 * @defgroup arm_rtl22xx RTL22XX Support
     28 * @ingroup bsp_arm
     29 * @brief RTL22XX Support Package
     30 * @{
     31 */
     32
    2033#define BSP_SMALL_MEMORY 1
    2134
     
    3144/* cco = cclk*2*P       */
    3245
    33 /* system clk frequecy,<=60Mhz, defined in system configuration */
     46/** @brief system clk frequecy,<=60Mhz, defined in system configuration */
    3447#define LPC22xx_Fcclk   CONFIG_ARM_CLK
    3548
    3649/* Fcco 156M~320Mhz*/
    37 /* system clk frequecy,<=60Mhz, defined in system configuration */
     50/** @brief system clk frequecy,<=60Mhz, defined in system configuration */
    3851#define LPC22xx_Fcclk   CONFIG_ARM_CLK
    3952#define LPC22xx_Fcco    LPC22xx_Fcclk * 4
    40 /*VPB clk frequency,1,1/2,1/4 times of Fcclk */
     53/** @brief VPB clk frequency,1,1/2,1/4 times of Fcclk */
    4154#define LPC22xx_Fpclk   (LPC22xx_Fcclk /4) *1
    4255
    4356
    4457
    45 /* Fcclk range: 10MHz ~ MCU allowed frequency */
     58/**
     59 * @name Fcclk range: 10MHz ~ MCU allowed frequency
     60 * @{
     61 */
     62
    4663#define Fcclk_MIN           10000000L
    4764#define Fcclk_MAX           60000000L
    4865
    49 /* Fcco range: 156MHz ~ 320MHz */
     66/** @} */
     67
     68/**
     69 * @name Fcco range: 156MHz ~ 320MHz
     70 * @{
     71 */
     72
    5073#define Fcco_MIN            156000000L
    5174#define Fcco_MAX            320000000L
    5275
     76/** @} */
     77
    5378#define PLLFEED_DATA1       0xAA
    5479#define PLLFEED_DATA2       0x55
    5580
    56 /* PLL PLLCON register bit descriptions */
     81/**
     82 * @name PLL PLLCON register bit descriptions
     83 * @{
     84 */
     85
    5786#define PLLCON_ENABLE_BIT   0
    5887#define PLLCON_CONNECT_BIT  1
    5988
    60 /* PLL PLLSTAT register bit descriptions */
     89/** @} */
     90
     91/**
     92 * @name PLL PLLSTAT register bit descriptions
     93 * @{
     94 */
     95
    6196#define PLLSTAT_ENABLE_BIT  8
    6297#define PLLSTAT_CONNECT_BIT 9
    6398#define PLLSTAT_LOCK_BIT    10
    6499
    65 /* PM Peripheral Type */
     100/** @} */
     101
     102/**
     103 * @name PM Peripheral Type
     104 * @{
     105 */
     106
    66107#define PC_TIMER0           0x2
    67108#define PC_TIMER1           0x4
     
    73114#define PC_RTC              0x200
    74115
    75 // OSC [Hz]
     116/** @} */
     117
     118/** @brief OSC [Hz] */
    76119#define FOSC              11059200
    77 // Core clk [Hz]
     120/** @brief Core clk [Hz] */
    78121#define FCCLK             FOSC<<2
    79 /**
    80 * help file
    81 */
    82 /* System configure, Fosc Fcclk Fcco Fpclk must be defined*/
    83 #define Fosc    11059200          // osc freq,10MHz~25MHz,
    84                                   //    change to real one if needed
    85 #define Fcclk   (Fosc << 2)       //system freq 2^n time of  Fosc(1~32) <=60MHZ
    86 #define Fcco    (Fcclk <<2)       //CCO freq 2,4,8,16 time of Fcclk 156MHz~320MHz
    87 #define Fpclk   (Fcclk >>2) * 1   //VPB freq only(Fcclk / 4) 1~4
     122
     123/**
     124 * @name System Configure
     125 * @{
     126 */
     127
     128/** @brief osc freq,10MHz~25MHz, change to a real one if needed */
     129#define Fosc    11059200
     130/** @brief system freq 2^n time of  Fosc(1~32) <=60MHZ */
     131#define Fcclk   (Fosc << 2)
     132/** @brief CCO freq 2,4,8,16 time of Fcclk 156MHz~320MHz */
     133#define Fcco    (Fcclk <<2)
     134/** @brief VPB freq only(Fcclk / 4) 1~4 */
     135#define Fpclk   (Fcclk >>2) * 1
    88136/* This was M.  That is a BAD BAD public constant.  I renamed it to
    89137 * JOEL_M so it wouldn't conflict with user code.  If you can find
    90138 * a better name, fix this.  But nothing I found uses it.
    91139 */
     140
     141/** @} */
     142
    92143#define JOEL_M       Fcclk / Fosc
    93144#define P_min   Fcco_MIN / (2*Fcclk) + 1;
    94145#define P_max   Fcco_MAX / (2*Fcclk);
    95146
    96 
    97 
    98147#define  UART_BPS       115200
    99148
    100 // Time Precision time [us]
     149/** @brief Time Precision time [us] */
    101150#define TIMER_PRECISION   10
    102151
    103 // I2C Speed [bit/s]
     152/** @brief I2C Speed [bit/s] */
    104153#define I2CSPEED          20000         // 20 Kbit/s
    105154
    106 // Uarts buffers size
     155/**
     156 * @name Uarts buffers size
     157 * @{
     158 */
     159
    107160#define RXBUFSIZE         32
    108161#define TXBUFSIZE         32
    109162
    110 // SPI Speed [bit/s]
     163/** @} */
     164
     165/** @brief SPI Speed [bit/s] */
    111166#define SPISPEED          1500000       // 1.5 Mbit/s
    112 // SPI EEPROM CS pin (SSEL is not suitable for CS, because is used by SPI module for multi master SPI interface)
     167/** @brief SPI EEPROM CS pin
     168 *
     169 *  (SSEL is not suitable for CS, because is used by SPI module for multi master SPI interface)
     170 */
    113171#define SPI_CS_PIN        P0_13
    114172#define SPI_CS_PIN_FUNC   PINSEL0_bit.SPI_CS_PIN
    115173
    116 // Flash definition
     174/**
     175 * @name Flash definition
     176 * @{
     177 */
     178
    117179//#define FLASH_SIZE      (0x200000-FLASH_BOOT)   // Total area of Flash region in words 8 bit
    118 #define FLASH_SIZE        (0x80000-FLASH_BOOT)   // Total area of Flash region in words 8 bit
     180/** @brief Total area of Flash region in words 8 bit */
     181#define FLASH_SIZE        (0x80000-FLASH_BOOT)
    119182//#define FLASH_SIZE      (0x80000-FLASH_BOOT)      // Total area of Flash region in words 8 bit
    120183#define FLASH_BEGIN       0x80000000
    121 #define FLASH_BASE        (FLASH_BEGIN+FLASH_BOOT)   //First 0x8000 bytes reserved for boot loader etc.
    122 
    123 // SRAM definition
    124 #define SRAM_SIZE         0x100000                  // Total area of Flash region in words 8 bit
    125 #define SRAM_BASE         0x81000000                //First 0x8000 bytes reserved for boot loader etc.
    126 
    127 // CS8900A definition
     184/** @brief First 0x8000 bytes reserved for boot loader etc. */
     185#define FLASH_BASE        (FLASH_BEGIN+FLASH_BOOT)
     186
     187/** @} */
     188
     189/**
     190 * @name SRAM definition
     191 * @{
     192 */
     193
     194/** @brief Total area of Flash region in words 8 bit */
     195#define SRAM_SIZE         0x100000
     196/** @brief First 0x8000 bytes reserved for boot loader etc. */
     197#define SRAM_BASE         0x81000000
     198
     199/** @} */
     200
     201/** @brief CS8900A definition */
    128202#define CS8900A_BASE      0x82000000
    129 // RTL8019AS definition
     203/** @brief RTL8019AS definition */
    130204#define RTL8019AS_BASE    0x82000000
    131205
     
    134208                          int                          attaching);
    135209
    136 /*
    137  * Network driver configuration
    138  */
     210/**
     211 * @name Network driver configuration
     212 * @{
     213 */
     214
    139215#define RTEMS_BSP_NETWORK_DRIVER_NAME   "eth0"
    140216#define RTEMS_BSP_NETWORK_DRIVER_ATTACH cs8900_driver_attach
     217
     218/** @} */
     219
     220/** @} */
    141221
    142222#ifdef __cplusplus
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