Changeset 78cac9b in rtems

Timestamp:
11/16/15 13:13:28 (8 years ago)
Author:
Daniel Cederman <cederman@…>
Branches:
5, master
Children:
836803f
Parents:
06ef76e3
git-author:
Daniel Cederman <cederman@…> (11/16/15 13:13:28)
git-committer:
Sebastian Huber <sebastian.huber@…> (11/16/15 13:48:54)
Message:

sparc: Fix context switch on SMP

We must not load registers (e.g. PSR) from the heir context area before
the heir stopped execution.

With this patch the write to PSR is divided into two steps. We first update
the current window pointer and then we restore the status registers and
enable traps. This allows us to move the first write to PSR to be before
the write to WIM, as there is now no risk that we get an interrupt where
the CWP and WIM would be inconsistent. We only need to make sure that we
do not use any of the non-global registers or instructions that affects
CWP for three instructions after the write.

In the earlier code the non-global %o1 register was used right after the
write to PSR, which required the use of three nop:s.

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